KR20100074683A - Semiconductor device and manufacturing method of the same - Google Patents

Abstract

PURPOSE: A semiconductor device and a method for manufacturing the same are provided to prevent the bridge between contact plugs in a contact hole by forming a spacer on the upper side of the sidewall of the contact hole. CONSTITUTION: An insulating layer including a contact hole is formed on the upper side of a semiconductor substrate. A lower contact plug(131) is formed in the contact hole. The height is lower than that of the contact hole. Spacers are formed on the upper sidewall of the contact hole. An upper contact plug(137) is formed between the spacer and fills the contact hole. A plurality of gate patterns is formed between the insulating layer and the semiconductor substrate. Junction regions(101a) are formed through around the gate patterns on the semiconductor substrate. The contact hole exposes the junction regions.

Description

Semiconductor device and manufacturing method of the same

The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a method for forming a contact plug inside a contact hole.

In the semiconductor device, a plurality of conductive patterns are formed in a stacked form with an insulating film interposed therebetween. When electrical connection is required between the conductive patterns of different layers, a contact plug is formed on the insulating film between the conductive patterns of the different layers requiring the connection. Accordingly, the conductive patterns of different layers are electrically connected via the contact plugs.

The contact plug deposits an insulating film to insulate the lower conductive pattern, and then forms a contact hole that exposes the lower conductive pattern by etching the insulating layer, and fills the inside of the contact hole with a conductive material, followed by chemical mechanical polishing. It will be formed through a series of processes to leave the conductive material only inside the contact hole by the "CMP" method.

As described above, in order to form a contact hole defining a region in which the contact plug is to be formed, the insulating film on the conductive pattern to be exposed must be etched. However, as semiconductor devices are highly integrated, the ratio of the width to height of the insulating layer to be etched to form the contact holes (ie, the aspect ratio) is increasing, making it difficult to stably form the contact holes. Hereinafter, the difficulty of the process of forming the contact hole due to the high integration of the semiconductor device will be described in detail with reference to the contact hole exposing the junction region of the flash memory device.

The flash memory device includes stacked gates in which a conductive film for a floating gate, a dielectric film, and a conductive film for a control gate are stacked. The stacked gate includes a source select gate, a drain select gate, and a plurality of memory cell gates connected in series between the source select gate and the drain select gate. The stacked gate is formed on the semiconductor substrate with a gate insulating film interposed therebetween, and is connected by junction regions formed between the stacked gates. The junction region includes a source formed between neighboring source select gates and a drain formed between neighboring drain select gates.

An insulating film is formed on the semiconductor substrate including the stacked gates and the junction regions described above. The insulating layers formed on the source and the drain are etched to form contact holes exposing the source and the drain. In this case, the contact hole is formed by forming a photoresist pattern on the insulating film and then etching the insulating film using the photoresist pattern as an etching barrier. The photoresist patterns should be formed in a pattern that can open the source or drain between the stacked gates, so they are spaced at very narrow intervals. Accordingly, since the etching material used in the etching process for forming the contact hole becomes difficult to penetrate into the insulating film exposed between the photoresist patterns, a defect in which the source or drain is not opened through the contact hole occurs. In order to solve this problem, the contact hole is formed by adjusting the etching degree of the insulating layer so that the source or the drain may be exposed. In this case, a bowing phenomenon occurs in which sidewalls of the contact holes are concave. This bowing phenomenon becomes a problem by causing a bridge between contact plugs formed in each contact hole.

The present invention provides a semiconductor device capable of preventing a bridge between contact plugs from occurring even if a bowing phenomenon occurs in the process of forming a contact hole, and a method of manufacturing the same.

The semiconductor device according to the present invention includes a contact hole and an insulating film formed on an upper portion of the semiconductor substrate, a lower contact plug formed inside the contact hole at a lower level than the contact hole, a spacer formed on the sidewall of the contact hole on the lower contact plug, and a lower portion. An upper contact plug is formed between the spacers on the contact plug and fills the contact hole.

A method of manufacturing a semiconductor device according to the present invention includes forming an insulating film including a contact hole on an upper portion of a semiconductor substrate, forming a lower contact plug having a lower height than a contact hole in a contact hole, Forming a spacer on the exposed sidewall of the contact hole, and forming an upper contact plug between the spacers that fills the contact hole and is connected to the lower contact plug.

Prior to forming the insulating layer, a plurality of gate patterns including select gates of the select transistor and cell gates of the memory cell are formed on the semiconductor substrate, and junction regions are formed on the semiconductor substrate between the gate patterns.

The contact hole exposes the junction region between the select gates.

An etch stop film is formed between the insulating film and the gate pattern.

The forming of the insulating film including the contact hole on the upper portion of the semiconductor substrate may include forming the etch stop layer using a nitride layer on the semiconductor substrate including the junction region and the gate pattern, and using the oxide layer on the etch stop layer. Forming an insulating film, and forming a contact hole by etching the insulating film and the etch stop film.

Forming the contact hole is performed using a CF ₄ gas of 10sccm to 20sccm.

In the forming of the contact hole, the etch stop layer is etched in a range in which the electrode temperature in the etching chamber is 0 ° C to 10 ° C.

In the forming of the contact hole, the etch stop layer is etched using Ar gas of 100 sccm to 200 sccm.

The forming of the lower contact plug having a lower height than the contact hole in the contact hole may include forming a conductive film on the insulating film including the contact hole so that the contact hole is embedded, and planarizing the surface of the conductive film until the insulating film is exposed. And lowering the height of the conductive film remaining inside the contact hole.

The voids generated in the conductive film in the step of forming the conductive film on the insulating film including the contact hole are removed in the step of lowering the height of the conductive film remaining inside the contact hole.

The spacer is formed using a nitride film.

The present invention forms a lower contact plug having a lower height than the contact hole, forms a spacer on the sidewall of the contact hole exposed from the upper portion of the lower contact plug, and forms an upper contact plug between the spacers formed on the lower contact plug.

As described above, the present invention can form a spacer on an upper sidewall of the contact hole, which is a part in which the bowing phenomenon occurs, to secure the spacing between neighboring contact holes, thereby preventing the occurrence of bridges between contact plugs formed in the contact hole.

In addition, the present invention may remove voids that may occur in the lower contact plug formed inside the contact hole having a high aspect ratio in the process of etching the lower contact plug to lower the lower contact plug height than the contact hole. As a result, since the upper contact plug is formed on the upper portion of the lower contact plug, a contact plug having a significantly reduced void can be formed, so that an appropriate level of resistance (Rc) can be secured and the profile of the contact plug can be equalized. Can be.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, the present invention is not limited to the embodiments disclosed below, but can be embodied in various other forms, and only the present embodiments make the disclosure of the present invention complete and the scope of the invention to those skilled in the art. It is provided to inform you completely.

1 is a layout diagram illustrating a contact plug of a semiconductor device according to the present invention, and FIGS. 2A to 2E are cut along the line "I-I" shown in FIG. 1 to contact a semiconductor device according to the present invention. Sectional drawing for demonstrating the plug formation method. Hereinafter, a contact plug connected to a junction region of a flash memory device will be described as an example.

Referring to FIG. 1, contact plugs 139 of a semiconductor device according to the present invention are formed in contact holes formed between select lines SL, respectively. The contact plug 139 may include a lower contact plug (not shown) formed at a lower level than the contact hole, a spacer 135 formed on sidewalls of the contact hole exposed from the upper contact plug, and a contact hole formed from the upper contact plug. An upper contact plug 137 formed between 135.

The select line SL connects select transistors included in a string structure of a flash memory device, and may be a drain select line of a drain select transistor or a source select line of a source select transistor. The string structure of a flash memory device includes a drain select transistor, a source select transistor, and memory cells connected in series between the drain select transistor and the source select transistor. The string structure is formed in plurality in parallel with each other. The parallel string drain select transistors are connected through the drain select line, and the parallel string source select transistors are connected through the source select line, and the parallel string memory cells are connected through the word line WL. do.

The gate of the source select transistor, the gate of the drain select transistor, and the gate of the memory cell are formed in a structure in which a charge storage film, a dielectric film, and a conductive film for a control gate are stacked. At this time, the conductive film for the control gate is connected to become a source select line, a drain select line, or a word line.

As described above, the contact plug 139 according to the present invention includes a lower contact plug having a lower height than the contact hole and an upper contact plug 137 connected to the lower contact plug to fill the upper portion of the contact hole. In this case, the upper contact plug 137 is formed on the contact hole where a bowing phenomenon occurs, and is formed between the second spacers 135 formed on the upper sidewall of the contact hole. As a result, even if a bowing phenomenon occurs, the gap between adjacent contact holes may be secured by the second spacer 135, thereby preventing the bridge between the adjacent upper contact plugs 137.

Hereinafter, the method of forming the contact plug described above with reference to FIG. 1 will be described in more detail.

Referring to FIG. 2A, a plurality of gate patterns SG and CG are formed, and a semiconductor substrate 101 having a junction region 101a formed between the gate patterns SG and CG is provided. Thereafter, an insulating film 127 including a contact hole 129 is formed on the semiconductor substrate 101.

The semiconductor substrate 101 may use a well formed (not shown) and an ion implantation process for adjusting the threshold voltage.

The gate patterns include a select gate SG of the select transistor and a cell gate CG of the memory cells. The select gate SG may be a drain select gate of the drain select transistor or a source select gate of the source select transistor. The gate patterns SG and CG are stacked on the semiconductor substrate 101 with the gate insulating layer 103 interposed therebetween, and the charge storage layer 105, the dielectric layer 107, and the conductive layer 114 for the control gate are formed. ) May be formed in a stacked structure. The capping layer 115 and the gate hard mask pattern 117 may be further stacked on the conductive gate 114 for the control gate. The capping film 115 is formed to prevent oxidation of the control gate conductive film 114 when a metal film or a metal silicide film is introduced into the control gate conductive film 114.

As described above, the gate patterns SG and CG having the stacked structure include the gate insulating film 103, the charge storage film 105, the dielectric film 107, and the control gate conductive film 114 on the semiconductor substrate 101. After the gate hard mask pattern 117 is formed, the gate hard mask pattern 117 may be patterned by an etching process using the gate hard mask pattern 117 as an etching barrier. In this case, the gate insulating layer 103 and the charge storage layer 105 may be patterned in the process of forming an isolation layer (not shown), and the charge storage layer 105 may use the gate hard mask pattern 117. By further patterning through an etching process, it may be formed in a plurality of separate patterns rather than lines. The gate insulating film 103 may be formed using an oxide film, and the charge storage film 105 may be formed using polysilicon as a conductive film for the floating gate. The dielectric film 107 may be formed as a stacked structure of an oxide film, a nitride film, and an oxide film, and includes a hole exposing the charge storage film 105 in a region where the cell gate SG is formed. The hole is formed by stacking the first conductive layer 109 and the photoresist pattern used as the lower layer of the control gate conductive layer 117 on the dielectric layer 107 and then using the photoresist pattern as an etching barrier. In some embodiments, the first conductive layer 109 and the dielectric layer 107 may be etched and a photoresist pattern may be removed. Here, the first conductive layer 109 serves to prevent the remaining dielectric layer 107 from being damaged in the process of forming the hole except for the region where the hole is formed, and may be formed using polysilicon. The control gate conductive film 114 may be formed by stacking the first conductive film 109, the second conductive film 111, and the third conductive film 113. The second conductive layer 111 may be formed using polysilicon, and the third conductive layer 113 may be introduced to improve the operating speed of the semiconductor device by improving the resistance of the conductive layer 114 for the control gate. It can be formed using tungsten (W).

After the gate patterns SG and CG are formed in the same manner as described above, an oxidation process is performed to remove damage occurring on the sidewalls of the gate patterns SG and CG during the etching of the gate patterns SG and CG. As a result, the sidewall oxide film 119 is formed on the sidewalls of the gate patterns SG and CG. Thereafter, impurity ions are implanted into the semiconductor substrate 101 between the gate patterns SG and CG to form the junction region 101a. At this time, the junction region 101a between the select gates SG is defined as a source or a drain. In more detail, the junction region between the source select gates is defined as a source, and the junction region between the drain select gates is defined as a drain. After the junction region 101a is formed, the first spacer 121 is formed on the sidewalls of the gate patterns SG and CG with the sidewall oxide film 119 therebetween. The first spacer 121 may prevent the gate patterns SG and CG from being exposed during the subsequent contact hole forming process. In addition, the gap between the select gate SG and the cell gate CG and the gap between the cell gates CG are smaller than the gap between the select gates SG, and thus may be filled by the first spacer 121. . Thereafter, an etch stop layer 125 is formed on the surfaces of the first spacer 121 and the gate patterns SG and CG. The etch stop layer 125 may be formed using a nitride layer. In addition, in order to relieve stress when forming the etch stop layer 125, the etch stop layer 125 may be formed with the buffer oxide layer 123 interposed between the first spacer 121 and the gate patterns SG and CG. have.

As described above, a contact hole may be formed on the semiconductor substrate 101 on which the gate patterns SG and CG, the junction region 101a, the sidewall oxide layer 119, the first spacer 121, and the etch stop layer 123 are formed. An insulating film 127 including the 129 is formed. The insulating layer 127 may be formed using an oxide layer to insulate the gate patterns SG and CG. In addition, the insulating layer 127 is formed to a sufficient thickness to fill the gap between the gate patterns SG and CG. The contact hole 129 includes an insulating layer 127 and an etch stop layer 125 formed on the junction region 101a between the select gates SG so that the junction region 101a between the select gates SG may be exposed. ) Can be formed by etching. The contact hole 129 may be formed through one etching process or may be formed through a step etching process. In the case where the contact hole 129 is formed using a stepped etching process, a process of etching using an etching material having an etch ratio of 1: 1 to an oxide film and a nitride film up to the height of the capping film 115, and an etch stop layer 125 ) Is exposed using the etching material that etches the oxide film faster than the nitride film, the etching stop film 125 is etched, and the junction region 101a is exposed until the junction region 101a is exposed. The contact hole 129 is formed by performing a series of processes of etching the remaining buffer film 123 and the sidewall oxide film 119 on the top of the substrate.

CF ₄ gas of 10 sccm to 20 sccm during the etching process for forming the contact hole 129 in order to minimize the bowing phenomenon occurring on the upper sidewall of the contact hole 129 in the process of forming the contact hole 129 described above It is preferable to use.

In order to minimize the inclination occurring on the sidewalls of the contact hole 129 during the formation of the contact hole 129, the etch stop layer 125 may be etched in a range of 0 ° C. to 10 ° C. in the electrode chamber. It is preferable. In addition, the etch stop layer 125 is preferably etched using Ar gas of 100sccm to 200sccm.

For reference, there is a method of introducing cobalt silicide (CoSi ₂ ) into the control gate conductive film 114. Although not shown in the drawings, the method of forming the gate patterns SG and CG in the case of introducing cobalt silicide into the control gate conductive film 114 is as follows. First, before forming the gate hard mask pattern, a second conductive film made of polysilicon is stacked on the semiconductor substrate 101, and a gate hard mask pattern is formed on the second conductive film. Thereafter, the second conductive film, the first conductive film, the dielectric film, and the charge storage film are etched by an etching process using the gate hard mask pattern as an etching barrier. Subsequently, after forming the junction region, a sidewall oxide film, a first spacer, a first buffer oxide film, and a first etch stop film are formed. Subsequently, an HDP (High Density Plasma) oxide film is formed to fill the gap between the select gates SG. Then, the gate hard mask pattern is removed to expose the top and side surfaces of the second conductive film made of polysilicon, and the heights of the sidewall oxide film, the first spacer, the first buffer oxide film, and the first etch stop film are lowered. Thereafter, a cobalt film is formed on the exposed surface of the second conductive film, and then cobalt and silicon are reacted to form a cobalt silicide film. Thereafter, cobalt films remaining without reaction are removed. Here, a capping layer may be further formed on the cobalt silicide layer to prevent oxidation of the cobalt silicide layer. Through such a series of processes, the gate patterns SG and CG including the cobalt silicide layer are formed. Thereafter, a second etch stop layer is formed on the exposed surface of the gate patterns SG and CG and the exposed surface of the HDP oxide film. The second etch stop layer may be formed on the exposed surface of the gate patterns SG and CG and the exposed surface of the HDP oxide layer with the second buffer oxide layer interposed therebetween. When the cobalt silicide layer is introduced as described above, the resistance of the gate patterns SG and CG can be further lowered. In this case, the insulating layer including the contact hole may include a gate pattern (SG, CG), a junction region, a first buffer oxide film, a first spacer, a first etch stop film, an HDP oxide film, a second buffer oxide film, and a second etch stop film. It is formed on top of the formed semiconductor substrate.

Referring to FIG. 2B, a lower contact plug 131 having a first height H1 is formed in the contact hole 129 of FIG. 2A. The lower contact plug 131 of the first height H1 forms a conductive film on the insulating film 127 including the contact hole (129 of FIG. 2A) so that the contact hole (129 of FIG. 2A) may be filled. The planarization process may be performed by planarizing the conductive layer until the insulating layer 127 is exposed through a planarization process such as a chemical mechanical polishing method. At this time, tungsten (W) can be used as the conductive film.

A void 133 may be formed on the upper portion of the lower contact plug 131. As the aspect ratio of the contact hole (129 of FIG. 2A) increases, the void 133 has an upper sidewall of the contact hole (129 of FIG. 2A) due to a bowing phenomenon occurring during the etching process of forming the contact hole (129 of FIG. 2A). Occurs because is formed concave.

Referring to FIG. 2C, the height of the lower contact plug 131 is set to be the second height H2 lower than the first height H1 to remove the void. To this end, the lower contact plug 131 is etched using an etching material that etches metal faster than the oxide film. As a result, the height of the lower contact plug 131 is lower than the height of the contact hole.

Referring to FIG. 2D, the second spacer 135 is formed on the sidewall of the contact hole exposed from the upper portion of the lower contact plug 131. The second spacer 135 may be formed using a nitride film. When a boeing phenomenon occurs and the upper portion of the sidewall of the contact hole is concave, the second spacer 135 may fill the recessed portion of the contact hole to secure a gap between neighboring contact holes.

Referring to FIG. 2E, an upper contact plug 137 is formed to fill a contact hole between the second spacers 135 formed on the lower contact plug 131. The upper contact plug 137 is connected to the lower contact plug 131 and may be formed of the same conductive material as the lower contact plug 131. As a result, a contact plug 139 including a lower contact plug 131, a second spacer 135, and an upper contact plug 137 is formed on the semiconductor substrate 101.

In the present invention, the upper contact plug 135 is formed between the second spacers 135 with the second spacers 135 formed on the sidewalls of the contact holes. Accordingly, even if a boeing occurs and the upper sidewall of the contact hole is concave, the bridge phenomenon in which neighboring contact plugs 139 are electrically connected to each other can be prevented. This is because the upper contact plug 135 is formed in a state where a space between neighboring contact holes is sufficiently secured by the second spacer 135.

In the above description, a method of forming a contact plug connected to a junction region of a flash memory device has been described as an example. However, the present invention is not limited thereto, and when the contact plug is to be formed inside a contact hole having a high aspect ratio, it is applicable to any known semiconductor device. Can be.

Although the technical spirit of the present invention described above has been described in detail in a preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, the present invention will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

1 is a layout for explaining a contact plug of a semiconductor device according to the present invention.

2A to 2E are cross-sectional views illustrating a method for forming a contact plug of a semiconductor device according to the present invention by cutting along the line “I-I ′” shown in FIG. 1.

<Explanation of symbols for the main parts of the drawings>

101: semiconductor substrate 101a: junction region

103: gate insulating film 105: charge storage film

107 dielectric film 109 first conductive film

111: second conductive film 113: third conductive film

114: conductive film for control gate 115: capping film

117: gate hard mask pattern 119: sidewall oxide film

121: first spacer 123: buffer oxide film

125: etch stop film 127: insulating film

129 contact hole 131 lower contact plug

133: void 135: second spacer

137: upper contact plug 139: contact plug

SG: Select Gate CG: Cell Gate

Claims (16)

An insulating film including a contact hole and formed over the semiconductor substrate; A lower contact plug formed in the contact hole at a lower height than the contact hole; A spacer formed on a sidewall of the contact hole above the lower contact plug; And And an upper contact plug formed between the spacers on the lower contact plug and filling the contact hole. The method of claim 1, A plurality of gate patterns are formed between the insulating layer and the semiconductor substrate, and junction regions are formed in the semiconductor substrate between the gate patterns. The contact hole exposes the junction region. The method of claim 2, The gate patterns include a select gate of a select transistor and a cell gate of a memory cell, wherein the contact hole exposes a junction region between the select gates. The method of claim 2, An etch stop layer is formed between the gate patterns and the insulating layer. The method of claim 1, The spacer includes a nitride film. Forming an insulating film including a contact hole on the semiconductor substrate; Forming a lower contact plug having a lower height than the contact hole in the contact hole; Forming a spacer on a sidewall of the contact hole exposed from an upper portion of the lower contact plug; And Forming an upper contact plug between the spacers that fills the contact hole and is connected to the lower contact plug. The method of claim 6, Before forming the insulating film A plurality of gate patterns including select gates of select transistors and cell gates of memory cells are formed on the semiconductor substrate, and junction regions are formed in the semiconductor substrate between the gate patterns. The method of claim 7, wherein And the contact hole exposes a junction region between the select gates. The method of claim 7, wherein And a etch stop layer is formed between the insulating layer and the gate pattern. The method of claim 9, Forming an insulating layer including a contact hole on the semiconductor substrate; Forming the etch stop layer by using a nitride film on the semiconductor substrate including the junction region and the gate pattern; Forming the insulating layer on the etch stop layer by using an oxide film; And And forming the contact hole by etching the insulating layer and the etch stop layer. The method of claim 10, The forming of the contact hole is a method of manufacturing a semiconductor device using a CF ₄ gas of 10sccm to 20sccm. The method of claim 10, In the forming of the contact hole, the etch stop layer is etched in the range of the electrode temperature in the etching chamber is 0 ℃ to 10 ℃. The method of claim 10, The method of claim 1, wherein the etching stop layer is etched using Ar gas of 100 sccm to 200 sccm in the forming of the contact hole. The method of claim 6, Forming a lower contact plug having a lower height than the contact hole in the contact hole; Forming a conductive film on the insulating film including the contact hole to fill the contact hole; Planarizing the surface of the conductive film until the insulating film is exposed; And And lowering the height of the conductive layer remaining in the contact hole. The method of claim 14, The voids generated in the conductive film in the step of forming a conductive film on the insulating film including the contact hole And lowering the height of the conductive film remaining inside the contact hole. The method of claim 6, The spacer is formed using a nitride film.

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