KR20100073579A - Semi-conductor wafer and method of preparation thereof - Google Patents

Abstract

PURPOSE: A semiconductor wafer and a method for manufacturing the same are provided to prevent chipping defects of a wafer by maintaining edge profiles in curve shape after a back grinding process. CONSTITUTION: A first region(100) is located on the upper side of a wafer. The first region is a region to be a chip. A second region(200) is located on the lower side of the first region. The second region is polished during a back-grinding process. The edge profiles(101, 102) of the first region are curve shape. The lateral profile(103) of the first region is curve shape.

Description

Semi-conductor wafer and method of preparation thereof

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor wafer and a method of manufacturing the same. Specifically, the edge profile of a region located above the vertical cross section of the wafer is curved so as to be curved even after back grinding. Or it relates to a semiconductor wafer and a method of manufacturing the same, which prevents damage during handling of the wafer after back grinding.

When the silicon is crystallized into large boules that are generally cylindrical over almost all lengths, they are cut into thin circular disks with a diameter of 25 to 30 mm, called silicon wafers. This silicon wafer is mounted to a vacuum chuck in an edge grinder, and the peripheral edge of the wafer is precisely grounded to form an accurate circular shape and precise edge profile with respect to the center of the wafer. Often notches are formed at one location along the circular perimeter. The thickness is uniform over the area of most of the wafer and the wafer circumference is ground in a triangular cross section, where the vertices of the triangle form the outermost diameter of the wafer and are typically located midway between the two parallel faces of the wafer.

Such disks are used to fabricate semiconductor devices. In the semiconductor package fabrication process, back grinding technology is well known in which wafers are packaged at the wafer level with very thin wafers. This back-grinding technology is usually performed by laser, etching, or mechanical grinding method on the back side of the wafer, that is, the surface where the pattern is not formed, and the remaining manufacturing processes such as circuit board attaching process, electrical connection process, encapsulation and input / output. It is a technique for performing terminal forming and sawing processes. However, when the back surface of the wafer is scraped as described above, there is a problem in that chipping of the wafer occurs.

1A shows a cross section of a typical semiconductor wafer. When the back grinding process is performed on such a wafer, the wafer has a shape as shown in FIG. 1B. As shown in FIG. 1B, the back side of the wafer is sharpened after back grinding, so that breakage frequently occurs during handling of the wafer. In addition, the risk of chipping is high because the edge portion of the wafer acts as a weak point at the back of the wafer than the center portion of the wafer. Due to such a problem, the defects of the wafer during back grinding and after back grinding increase, resulting in very low semiconductor package production yield.

An object of the present invention to solve the above problems is to provide a semiconductor wafer and a method of manufacturing a semiconductor wafer having an improved edge profile of the region to be formed as a chip located above the vertical cross section of the wafer so that no damage occurs during back grinding or after back grinding of the wafer. To provide.

The present invention to achieve the above object,

A first region located above the vertical cross section of the wafer and formed into a chip, and a second region located below the first region and polished in a back grinding process,

A semiconductor wafer is provided in which the edge profile of the first region is curved.

The side profile of the first region may be curved.

The edge profile and the side profile of the first region may be connected to form an arc shape.

The present invention to achieve another object of the present invention,

An edge polishing step of grinding the edge of the wafer so that the edge profile of the first area to be formed into a chip is located above the vertical cross section of the wafer to be curved; And

And a back grinding step of grinding the second region located below the first region to leave only the first region.

The method may further include polishing a side surface of the first region to polish the side profile of the first region to have a curved shape before the back grinding step.

When using a wafer having a curved edge profile of an upper region formed of a chip based on a vertical cross section of the wafer of the present invention, the back surface of the wafer is not sharpened during the back grinding process, and the edge region is smoothed to reduce wafer breakage. . In addition, since the edges and sides of the wafer become smooth curves after back grinding, breakage is prevented during wafer handling.

As a result, the manufacturing yield and productivity of the semiconductor package are improved, and the cost of the device is reduced by reducing downtime of the device.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention.

First, the semiconductor wafer of this invention is demonstrated.

2A is a cross-sectional view of a semiconductor wafer according to an embodiment of the present invention, and FIG. 2B is a cross-sectional view after performing a back grinding process on the semiconductor wafer of FIG. 2A. As shown in FIG. 2A, the semiconductor wafer of the present invention includes a first region 100 positioned above and a second region 200 positioned below the first region based on a vertical cross section of the wafer. . In addition, the edge profiles 101 and 102 of the first region and the side profile 103 of the first region may be curved. Since the edge profile of the first region is curved to form a wafer as shown in FIG. 2B after the back grinding process, the semiconductor wafer is prevented from chipping during handling of the wafer during the back grinding process or after the back grinding process.

The first region 100 is positioned above the vertical section of the wafer. The first region 100 is a region in which a chip is formed after being left without being ground in a back grinding process. The thickness of the first region can be appropriately adjusted by those skilled in the art as necessary.

The edge profiles 101 and 102 of the first region 100 may be formed in a curved shape, preferably in an arc shape. The edge means a first edge 101 which is an area including an edge where an upper surface of the wafer and a side of the first area meet, or a second edge 102 which is an area including side boundary points of the first area and the second area. do. There is no limit to the length of the edges and the edge profile can be formed by including the sides as required by those skilled in the art.

The side profile 103 of the first region may be formed in a curved shape, preferably in an arc shape. The edge profiles 101 and 102 of the first region and the side profile 103 of the first region may be connected to form a curved line, and preferably an arc shape.

The second region 200 is located below the first region. The second area 200 is an area that is ground in the back grinding process. The thickness of the second region may vary depending on the thickness of the first region. In the case of forming a thin chip, the thickness of the first region becomes thin and the thickness of the second region becomes relatively thick.

The edge profiles 201 and 202 of the second region 200 are not limited in shape and may be appropriately selected according to the needs of those skilled in the art. Can be. The edge means a first edge 201 which is a region including side boundary points of the first region and a second region, and a second edge 202 which is a region including an edge where a side of a bottom surface and a second region of the wafer meet. do.

The side profile 203 of the second region 200 is not limited in shape, but it is advantageous that the side profile 203 is curved in terms of preventing breakage during handling of the wafer. The edge profiles 201 and 202 of the second region and the side profile 203 of the second region may be connected to form a curve, and preferably may form an arc shape.

Hereinafter, the manufacturing method of the semiconductor wafer of this invention is demonstrated.

3 is a schematic diagram illustrating a method of manufacturing a semiconductor wafer according to an embodiment of the present invention. Referring to FIG. 3, in the method of manufacturing a semiconductor wafer of the present invention, the edge polishing step S10 of the first region, the side polishing step S20 of the first region, the edge polishing step S30 of the second region, Lateral polishing step S40 and back grinding step S50 are included.

The edge polishing step (S10) of the first area is a step of polishing the edge of the wafer so that the edge profile (101, 102) of the first area to be formed as a chip is positioned above the vertical cross section of the wafer. Preferably the polishing is such that the edge profile of the first region is in the shape of an arc. The edge polishing method can be used without limitation methods known in the art, and typically, the edge polishing is performed using a wafer polishing equipment. In the edge polishing step S10 of the first region, the side surface may be polished.

The side polishing step S20 of the first region is a step of polishing the side profile 103 of the first region to be curved. The side profile 103 of the first region is not particularly limited as long as it is curved, but may be polished to have an arc shape. The side profile 103 of the first region may be polished to form an arc shape that is connected to the edge profiles 101 and 102.

The edge polishing step S30 of the second region is a step of polishing the edge profiles 201 and 202 of the second region to be curved. Preferably, the edge profiles 201 and 202 of the second region may be polished to have an arc shape. Edge polishing of the second region may be performed in the same manner as the edge polishing method of the first region. The edge of the second region may be polished including the side surface.

The side polishing step S40 of the second region is a step of polishing the side surface of the second region. The side profile 203 of the second region may be arbitrarily formed by those skilled in the art, but may be formed in a curved shape, and more preferably in an arc shape. Side polishing of the second region may be performed in the same manner as the side polishing method of the first region.

The back grinding step S50 is a step of grinding the second region 200. In the back grinding step S50, the second region is ground to uniformly correct the thickness of the wafer before the assembling process. Thus, only the first region to be formed of the chip remains. The back grinding may be performed by conventional methods known in the art, specifically, may be automatically performed by a grinding wheel.

By this step, the semiconductor wafer of the present invention is manufactured. That is, the edges and side profiles of the first region are curved to prevent breakage of the wafer during the back grinding process, and the edges of the wafer are sharpened after the back grinding process, thereby making it easy to break. In addition, a phenomenon in which the wafers collide with each other during the handling of the wafer may be reduced.

1A is a cross-sectional view of a semiconductor wafer having a conventional conventional edge profile.

FIG. 1B is a cross-sectional view after the back grinding process of the semiconductor wafer of FIG. 1A.

2A is a cross-sectional view of a semiconductor wafer having an edge profile in accordance with one embodiment of the present invention.

FIG. 2B is a cross-sectional view after the back grinding process of the semiconductor wafer of FIG. 2A.

3 is a schematic diagram illustrating a method of manufacturing a semiconductor wafer according to an embodiment of the present invention.

Claims (5)

A first region located above the vertical cross section of the wafer and formed into a chip, and a second region located below the first region and polished in a back grinding process, And wherein the edge profile of the first region is curved. The method of claim 1, And the side profile of the first region is curved. The method of claim 1, And an edge profile of the first region and a side profile of the first region to form an arc shape. An edge polishing step of the first area for grinding the edges of the wafer such that the edge profile of the first area, which is located above the vertical cross section of the wafer and is to be formed into chips, is curved; And And grinding the second region located below the first region to leave only the first region. The method of claim 4, wherein And a side polishing step of the first area for polishing the side profile of the first area to be curved before the back grinding step.

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