KR20100064906A - Test enable signal generation circuit and semicon ductor memory device using the same - Google Patents

Abstract

PURPOSE: A test enable signal generation circuit and a semiconductor memory device are provided to implement the test with same pattern regardless of a normal cell array and a redundancy cell array of a column redundancy domain by selecting the cell array tested according to the state of an input signal. CONSTITUTION: A first input pad(30) is inputted a first input signal. A second input pad(31) is inputted a second input signal. A buffer(32) generates a first and a second inner signal with buffering the first and the second input signal inputted from the first and the second input pad. An enable signal generator(33) is inputted the first and the second inner signal, and a first and a second test signal and a parallel test signal. The enable signal generator generates the first enable signal and the second enable signal. The first enable signal is enabled to test a redundancy cell array of a row redundancy domain.

Description

Test enable signal generation circuit and semiconductor memory device using the same {TEST ENABLE SIGNAL GENERATION CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE USING THE SAME}

The present invention relates to a semiconductor memory device, and more particularly, to a test enable signal generation circuit which enables a normal cell array and a redundant cell array to be tested in the same pattern in a parallel test.

1 is a diagram illustrating a configuration of a semiconductor memory device for performing a parallel test according to the prior art.

As illustrated, the semiconductor memory device according to the related art decodes the internal clock signal ICLK, the address signal ADD, and the command signal CMD to decode the first test signal TM_XRED and the second test signal TM_YRED. And a test mode decoder 12 for generating a parallel test signal TMPARA. Here, the first test signal TM_XRED is enabled at a high level to test the redundancy cell array of the row redundancy area, and the second test signal TM_YRED is of the column redundancy area. A signal that is enabled at a high level to test a redundant cell array. The row redundancy area refers to the area where the redundancy cell array is formed in the row direction of the area where the normal cell array is located, and the column redundancy area refers to the column of the area where the normal cell array is located. The region in which the redundancy cell array is formed in the (column) direction. When the normal cell array is tested, the first test signal TM_XRED and the second test signal TM_YRED are at a low level. In addition, the parallel test signal TMPARA is a signal which is enabled at a high level in order to enter the test mode performed by the parallel test, that is, the first test signal TM_XRED and the second test signal TM_YRED.

When the parallel test is performed in the conventional semiconductor memory device described above, when both the first test signal TM_XRED and the second test signal TM_YRED are high level, the test of the redundancy cell array is performed and the first test signal is performed. When both the TM_XRED and the second test signal TM_YRED are at the low level, the normal cell array is tested. In addition, when the first test signal TM_XRED is high level and the second test signal TM_YRED is low level, a test is performed on the redundancy cell array in the low redundancy region, and the first test signal TM_XRED is low level, When the second test signal TM_YRED is at a high level, a test is performed on the redundancy cell array in the column redundancy region.

In the case of the conventional semiconductor memory device, the test pattern is different according to the generation levels of the first test signal TM_XRED and the second test signal TM_YRED. Therefore, there is a problem in that the test cannot be performed with the same test pattern on the normal cell array and the redundant cell array.

Test signal for testing the normal cell array and the redundancy cell array in the same pattern by performing a test on the redundant cell array or the normal cell array according to the input signal input through the pad while the test signal is enabled. A generation circuit and a semiconductor memory device using the same are disclosed.

To this end, the present invention includes a first input pad for receiving a first input signal; A second input pad configured to receive a second input signal; A buffer configured to buffer first and second input signals input through the first and second input pads to generate first and second internal signals; And a redundancy cell of a first enable signal and a column redundancy area enabled to receive the first and second internal signals, the first and second test signals, and the parallel test signal to test a redundancy cell array of a low redundancy area. A test enable signal generation circuit is provided that includes an enable signal generator that generates a second enable signal that is enabled for testing an array.

The present invention also includes a test mode decoder configured to receive an internal clock, an address signal, a command signal, and a status signal to generate first and second test signals; Receiving the first and second test signals, the parallel test signal, and the first and second input signals to generate first and second enable signals, wherein the first enable signal is a redundancy cell array in a low redundancy region; A test enable signal generator including an enable signal generator enabled to test a second enable signal, the second enable signal enabled to test a redundant cell array of a column redundancy region; A row path controller for selectively enabling word lines in response to the first enable signal; And a column path controller configured to selectively enable output enable signals for controlling data input / output between the memory cell array and the input / output line in response to the second enable signal.

Hereinafter, the present invention will be described in more detail with reference to Examples. These embodiments are only for illustrating the present invention, and the scope of rights of the present invention is not limited by these embodiments.

2 is a diagram illustrating a configuration of a semiconductor memory device for performing a parallel test according to an embodiment of the present invention.

As shown in FIG. 2, the semiconductor memory device performing the parallel test according to the present embodiment includes a first buffer 20, a state machine 21, a test mode decoder 22, a low pass controller 23, and a column. The path control section 24, the memory core 25, the data control section 27, the DQ pad 27 and the test enable signal generation section (3).

The first buffer 20 receives the clock signal CLK and the command address signals CA <0: 9> and generates an internal clock signal ICLK, an address signal ADD, and a command signal CMD. Here, the command address signals CA <0: 9> are input signals including both the address signal and the command signal in accordance with the LPDDR2 specification. The first buffer 20 extracts the address signal ADD and the command signal CMD from the command address signals CA <0: 9> according to the clock signal CLK.

The state machine 21 receives the internal clock signal ICLK, the address signal ADD and the command signal CMD, and includes the state information STS and the low address XADD including information on whether to enter the parallel test. Create a column address (YADD).

The test mode decoder 22 receives an internal clock signal ICLK, an address signal ADD, a command signal CMD, and status information STS, and receives a first test signal TM_XRED and a second test signal TM_YRED. And generate a parallel test signal TM_PARA. Here, the first test signal TM_XRED is enabled at a high level to test the redundancy cell array of the row redundancy area, and the second test signal TM_YRED is the column of the redundancy area of the column redundancy area. A signal that is enabled at a high level to test a redundant cell array. The row redundancy area refers to the area where the redundancy cell array is formed in the row direction of the area where the normal cell array is located, and the column redundancy area refers to the column of the area where the normal cell array is located. The region in which the redundancy cell array is formed in the (column) direction. When the normal cell array is tested, the first test signal TM_XRED and the second test signal TM_YRED are at a low level. In addition, the parallel test signal TMPARA is a signal that is enabled at a high level to perform the parallel test.

The low path controller 23 receives the low address signal XADD and the first enable signal XREDEN to selectively enable the word lines WL <1: n> and the column path controller 24. In response to the column address signal YADD and the second enable signal YREDEN, the output enable signals YI <1: m> are selectively enabled. The output enable signals YI <1: m> are control signals that turn on a switch connected between an input / output line (not shown) and a memory cell array to allow data to be input and output.

The memory core 25 includes a column redundancy region in which data stored in the cell array and a redundancy cell array of a low redundancy region connected to a word line separated from the normal cell array and output enable signals distinguished from the normal cell array are inputted and outputted. A redundancy cell array of is formed. The data controller 26 is responsible for data exchange between the memory core 25 and the DQ pad 27.

The test enable signal generator 3 includes a first input pad 30, a second input pad 31, a second buffer 32, and an enable signal generator 33. The first input pad 30 receives a first input signal XRED, and the second input pad 31 receives a second input signal YRED. Here, the first input signal XRED is enabled and input at a high level when the redundancy cell array is tested in the low redundancy area, and the second input signal YRED is high when the redundancy cell array is tested in the column redundancy area. Input is enabled with level. The second buffer 32 buffers the first input signal XRED and the second input signal YRED input through the first input pad 30 and the second input pad 31 to form the first internal input signal ( XREDI) and second internal input signal YREDI are generated.

As shown in FIG. 3, the enable signal generator 33 includes a first enable signal generator 330 and a second enable signal generator 331. The first enable signal generator 330 receives the first internal input signal XREDI and the first test signal TM_XRED and performs NAND gate ND30 for performing a negative logic multiplication operation, and an output of the NAND gate ND30. And a NOR gate NR30 that receives an inverted signal of the signal and the parallel test signal TMPARA and performs a negative logic sum operation. The second enable signal generator 331 receives the second internal input signal YREDI and the second test signal TM_YRED, and performs NAND gate ND31 and negative output operation, and outputs of the NAND gate ND31. And a NOR gate NR31 that receives an inverted signal of the signal and the parallel test signal TMPARA and performs a negative logic sum operation. The first enable signal generator 330 is high in parallel testing, that is, when the parallel test signal TMPARA is at a high level, when both the first internal input signal XREDI and the first test signal TM_XRED are at a high level. The first enable signal XREDEN of the level is generated. In addition, the second enable signal generator 331 generates a high enable level second enable signal YREDEN when both of the second internal input signal YREDI and the second test signal TM_YRED are high level during the parallel test. do.

Unlike the related art, in the configuration of the semiconductor memory device according to the present exemplary embodiment, the first enable signal XREDEN is input to the low pass controller 23 instead of the first test signal TM_XRED, and the column pass controller 24 is input to the low pass controller 23. The second enable signal YREDEN is input instead of the second test signal TM_YRED. That is, the first enable signal XREDEN is changed by changing the levels of the first internal input signal XREDI and the second internal input signal YREDI in predetermined states of the first test signal TM_XRED and the second test signal TM_YRED. ) And the second enable signal YREDEN may be changed to test the same test pattern.

The parallel test operation in the semiconductor memory device configured as described above will be described with reference to FIGS. 2 to 4.

Referring to FIG. 2, when a command address signal CA <0: 9> for performing a parallel test is input, an internal clock signal ICLK, an address signal ADD, and a command signal CMD are received through the first buffer 20. The state machine 21 receiving the input generates a state signal STS including information on entering the parallel test, and the test mode decoder 22 generates a high level first test signal TM_XRED and a second test signal. (TM_YRED) and the parallel test signal TM_PARA are generated.

In this state, when the first input signal XRED is input at a high level and the second input signal YRED is at a low level, the first input signal XRED is at a low level and the second input signal YRED is at a low level. When the high level is input, when the first input signal XRED and the second input signal YRED are both input at the high level, and when the first input signal XRED and the second input signal YRED are both The operation in the case of being input at the low level will be described as follows.

First, an operation when the first input signal XRED is input at high level and the second input signal YRED is input at low level will be described below.

When the first input signal XRED is input at the high level and the second input signal YRED is input at the low level, the first internal input signal XREDI generated through the second buffer 32 is at the high level and the second internal. The input signal YREDI goes low. Therefore, the first enable signal XREDEN generated by the enable signal generator 33 shown in FIG. 3 is at a high level, and the second enable signal YREDEN is at a low level. 4A when the first enable signal XREDEN input to the low pass controller 23 is at a high level and the second enable signal YREDEN input to the column path controller 24 is at a low level. As shown in FIG. 3, a test is performed on the redundancy cell array in the low redundancy region.

A test is performed on the redundancy cell array of the selected low redundancy region, and the test writes predetermined data to the redundancy cell array of the selected low redundancy region (for example, high-level data is written to the redundancy cell array of all low redundancy regions). The data may be written, or written to the redundancy cell array by crossing the data of the high level and the low level, and then the stored data may be read to measure the degree of disturbance between the redundancy cells. Referring to FIG. 4, a test performed when the first test signal TM_XRED, the second test signal TM_YRED, and the parallel test signal TM_PARA are all generated at a high level is performed in an active operation, a write operation, a precharge operation, and an active state. The same test pattern proceeds in the order of operation-lead operation-precharge operation.

Next, an operation in the case where the first input signal XRED is input at the low level and the second input signal YRED is input at the high level is as follows.

When the first input signal XRED is input at the low level and the second input signal YRED is input at the high level, the first internal input signal XREDI generated through the second buffer 32 is at the low level and the second internal. The input signal YREDI is at a high level. Accordingly, the first enable signal XREDEN generated by the enable signal generator 33 shown in FIG. 3 is at a low level, and the second enable signal YREDEN is at a high level. 4B when the first enable signal XREDEN input to the low pass controller 23 is at a low level, and the second enable signal YREDEN input to the column path controller 24 is at a high level. As shown in FIG. 3, a test is performed on the redundancy cell array in the column redundancy region.

Next, an operation in the case where both the first input signal XRED and the second input signal YRED are input at a high level will be described.

When both of the first input signal XRED and the second input signal YRED are input at a high level, the first internal input signal XREDI and the second internal input signal YREDI generated through the second buffer 32 are generated. Are all at a high level. Therefore, both the first enable signal XREDEN and the second enable signal YREDEN generated by the enable signal generator 33 shown in FIG. 3 are also at a high level. When the first enable signal XREDEN input to the low pass control unit 23 and the second enable signal YREDEN input to the column path control unit 24 are both at a high level, the first enable signal XREDEN shown in FIG. As described, tests are performed on the redundancy cell array in the column redundancy area and the redundancy cell array in the low redundancy area.

Next, an operation in the case where both the first input signal XRED and the second input signal YRED are input at a low level will be described.

When both of the first input signal XRED and the second input signal YRED are input at a low level, the first internal input signal XREDI and the second internal input signal YREDI generated through the second buffer 32 are generated. Are all at the low level. Accordingly, both the first enable signal XREDEN and the second enable signal YREDEN generated by the enable signal generator 33 shown in FIG. 3 are also at a low level. When the first enable signal XREDEN input to the low path controller 23 and the second enable signal YREDEN input to the column path controller 24 are both at low level, the first enable signal XREDEN input to the low path controller 23 is shown in FIG. As shown, a test is performed on the normal cell array.

As described above, in the parallel test performed by the semiconductor memory device according to the present exemplary embodiment, the first test signal TM_XRED, the second test signal TM_YRED, and the parallel test signal TM_PARA generated by the test mode decoder 22 are used. ) Are both at a high level, depending on the state of the first input signal XRED input through the first input pad 30 and the second input signal YRED input through the second input pad 31. Select the cell array on which the test was performed. Therefore, it is possible to test with the same pattern irrespective of the redundancy cell array of the low redundancy area, the redundancy cell array of the column redundancy area, and the normal cell array. This is because the test of the same test pattern is performed when the first test signal TM_XRED, the second test signal TM_YRED and the parallel test signal TM_PARA are at the same level.

1 is a diagram illustrating a configuration of a semiconductor memory device for performing a parallel test according to the prior art.

2 is a diagram illustrating a configuration of a semiconductor memory device for performing a parallel test according to an embodiment of the present invention.

FIG. 3 is a circuit diagram of an enable signal generator included in the semiconductor memory device shown in FIG. 2.

4 is a timing diagram for describing a parallel test performed by the semiconductor memory device shown in FIG. 2.

<Description of the symbols for the main parts of the drawings>

20: first buffer 21: state machine

22: test mode decoder 23: low pass control unit

24: column path controller 25: memory core

26: data control unit 27: DQ pad

3: test enable signal generator 30: first input pad

31: second input pad 32: second buffer

33: enable signal generator

Claims (11)

A first input pad configured to receive a first input signal; A second input pad configured to receive a second input signal; A buffer configured to buffer first and second input signals input through the first and second input pads to generate first and second internal signals; And The redundancy cell array of the first enable signal and the column redundancy area enabled to receive the first and second internal signals, the first and second test signals, and the parallel test signal to test the redundancy cell array of the low redundancy area. A test enable signal generation circuit comprising an enable signal generator for generating a second enable signal that is enabled to test. The method of claim 1, wherein the enable signal generator A first enable signal generator configured to generate the first enable signal enabled when both the first internal signal and the first test signal are enabled in a parallel test; And And a second enable signal generator configured to generate the second enable signal that is enabled when both the second internal signal and the second test signal are enabled in a parallel test. The method of claim 2, wherein the first enable signal generator A first logic element configured to receive the first internal signal and the first test signal and perform a logic operation; And And a second logic element configured to receive an output signal of the first logic element and the parallel test signal and perform logic operation. The method of claim 2, wherein the second enable signal generator A first logic element configured to receive the second internal signal and the second test signal and perform a logic operation; And And a second logic element configured to receive an output signal of the first logic element and the parallel test signal and perform logic operation. The test enable signal generation circuit of claim 1, wherein a test for a normal cell array is performed when both the first and second enable signals are disabled in a parallel test. A test mode decoder configured to receive an internal clock, an address signal, a command signal, and a status signal and generate first and second test signals; Receiving the first and second test signals, the parallel test signal, and the first and second input signals to generate first and second enable signals, wherein the first enable signal is a redundancy cell array in a low redundancy region; A test enable signal generator including an enable signal generator enabled to test a second enable signal, the second enable signal enabled to test a redundant cell array of a column redundancy region; A row path controller for selectively enabling word lines in response to the first enable signal; And And a column path controller configured to selectively enable output enable signals for controlling data input / output between the memory cell array and the input / output line in response to the second enable signal. The method of claim 6, wherein the test enable signal generation unit A first input pad configured to receive the first input signal; A second input pad configured to receive the second input signal; A buffer configured to buffer first and second input signals input through the first and second input pads to generate first and second internal signals; And And an enable signal generator configured to receive the first and second internal signals, the first and second test signals, and the parallel test signal to generate the first and second enable signals. The method of claim 7, wherein the enable signal generator A first enable signal generator configured to generate the first enable signal enabled when both the first internal signal and the first test signal are enabled in a parallel test; And And a second enable signal generator configured to generate the second enable signal enabled when both the second internal signal and the second test signal are enabled in a parallel test. The method of claim 8, wherein the first enable signal generator A first logic element configured to receive the first internal signal and the first test signal and perform a logic operation; And And a second logic element configured to receive an output signal of the first logic element and the parallel test signal to perform logic operation. The method of claim 8, wherein the second enable signal generator A first logic element configured to receive the second internal signal and the second test signal and perform a logic operation; And And a second logic element configured to receive an output signal of the first logic element and the parallel test signal to perform logic operation. 8. The semiconductor memory device of claim 7, wherein a test is performed on a normal cell array when both of the first and second enable signals are disabled in a parallel test.

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