KR20100059179A - Hybrid nano-logic circutis and the method of manufacturing the same - Google Patents

Abstract

PURPOSE: A hybrid type nano-logic circuits and a method for manufacturing the same are provided to accurately control the threshold voltage of a transistor by manufacturing the nano-logic circuits using an n-type nanowire transistor and a p-type carbon nanotube transistor. CONSTITUTION: A silicon oxide film(220) is formed on a silicon substrate(210). A p-type carbon nanotube transistor is formed into a source electrode, a drain electrode and a semiconductor carbon nano tube(250). An n-type nanowire transistor is formed into the source electrode, the drain electrode and a semiconductor nanowire(240). A metal line connects the drain electrode of the p-type semiconductor carbon nanotube transistor with the drain electrode of the n-type semiconductor nanowire transistor.

Description

Hybrid nano-logic logic circuit and its manufacturing method {Hybrid nano-logic circutis and the method of manufacturing the same}

The present invention relates to a hybrid nanodevice logic circuit, and more particularly, by manufacturing a hybrid nanodevice logic circuit using an n-type semiconductor nanowire transistor and a p-type semiconductor carbon nanotube transistor, a circuit without any additional device A low voltage, high performance hybrid type nano device logic circuit capable of precisely controlling the threshold voltage of a transistor constituting the transistor, irradiating the proton beam, and selectively adjusting a driving voltage of the nano device logic circuit according to the dose of the proton beam to be irradiated; The manufacturing method is related.

In the conventional semiconductor manufacturing technology, lithography technology for forming a pattern on a wafer designed using light of a constant wavelength and a top-down method for manufacturing a device based on an etching process are mainly used. As the size and integration of semiconductor devices are rapidly progressing, due to physical and technical limitations in the reduction of classical complementary metal oxide semiconductor (CMOS) devices, a new paradigm may be provided. Interest and research on bottom-up technology using nanostructures are being actively conducted.

In particular, as a part of the bottom-up method, semiconductor nanowire and carbon nanotube related technologies are considered as one of the top ten new technologies that will change the world, and are currently considered as one of the most efficient fields in nanotechnology.

Some reports have been made on the development of nanowire and carbon nanotube logic circuits that fabricate transistors composed of nanowires and carbon nanotube channels in electronic device applications using nanostructures, and explore the potential of next generation CMOS technology. . However, all these attempts are fundamentally guaranteed for the transistor's threshold voltage controllability, so that the voltage and current of the transistors that make up the logic circuit must be matched to improve the power consumption and performance of the logic circuit. You can expect

Recently, Ma's team [Ma e al., Nano Lett. 7, 3300. (2007) published an Inverter or Not logic circuit using n-type nanowires, and Bachtold's team [Bachtold et al., Science 9, 1317. (2001)]. A study on the inverter logic circuit using carbon nanotubes was reported. Zhang et al., Nano Lett. 7, 3603. (2007)] Complementary nanodevice inverters have been reported using carbon nanotubes with controlled n-type and p-type.

However, in the implementation of logic circuits using nanowires and carbon nanotubes, it is difficult to accurately control the threshold voltages of transistors constituting the logic circuits, which brings great limitations to proper logic device operation. For example, the drive of the inverter logic circuit should output the output value corresponding to logical 1 when the input voltage is logical 0. If the operating voltage of the wrong logic circuit is correct, the operation of the circuit will be correct. Can't. In this case, a problem can be solved by installing a level shifting element as an additional device. However, since the complexity and power consumption of the circuit are increased, it is a disadvantage in implementing a highly integrated circuit.

In addition, nanostructures such as nanowires and carbon nanotubes have limitations in controlling n-type and p-type semiconductors having the same electrical properties for a single material. For example, carbon nanotube transistors show excellent p-type semiconductor characteristics, but the electrical characteristics of relatively low n-type semiconductor carbon nanotube transistors and unstable device characteristics in the atmosphere cause changes in electrical characteristics over time.

As described above, the technical difficulty of precisely controlling the electrical characteristics of nanodevices through complementary doping of nanostructures using conventional techniques is a limitation in implementing high performance logic circuits using nanodevices.

The present invention is to solve the above problems according to the prior art. That is, an object of the present invention is to manufacture a hybrid nanodevice logic circuit using an n-type semiconductor nanowire transistor and a p-type semiconductor carbon nanotube transistor, thereby accurately adjusting the threshold voltage of the transistor constituting the circuit without any additional device. The present invention provides a low-voltage, high-performance hybrid nanodevice logic circuit capable of controlling and selectively controlling a driving voltage of a nanodevice logic circuit according to the dose of the proton beam to be irradiated by irradiating the proton beam, and a method of manufacturing the same.

As a technical idea for achieving the above object, the present invention provides a p-type semiconductor carbon nanotube comprising a silicon substrate on which a silicon oxide film is formed, a source electrode and a drain electrode formed on one side of the substrate, and a semiconductor carbon nanotube connecting the same. An n-type semiconductor nanowire transistor comprising a transistor, a source electrode and a drain electrode formed on the other side of the substrate, and a semiconductor nanowire connecting the same; and a drain electrode of the p-type semiconductor carbon nanotube transistor and the n-type semiconductor nanowire transistor. It provides a hybrid nano-device logic circuit comprising a metal line connecting the drain electrode.

In addition, the present invention is a step of applying a semiconductor carbon nanotube to a predetermined region on a silicon substrate on which a silicon oxide film is formed, forming a source electrode and a drain electrode on the coated semiconductor carbon nanotube, and the source Removing carbon nanotubes in the remaining region except for the semiconductor carbon nanotubes of a predetermined portion that is applied between the electrode and the drain electrode to connect the source electrode and the drain electrode; Applying a wire, forming a source electrode and a drain electrode on the coated semiconductor nanowire, and connecting a drain electrode connected to the semiconductor carbon nanotube and a drain electrode connected to the semiconductor nanowire with a metal line Characterized in that it is formed, including Provides a method for manufacturing a hybrid nano device logic circuit.

According to the present invention, a hybrid nanodevice logic circuit and a method of manufacturing the same are provided by irradiating a proton beam to a hybrid nanodevice logic circuit manufactured using an n-type semiconductor nanowire transistor and a p-type semiconductor carbon nanotube transistor. The driving voltage of the nanodevice logic circuit can be selectively adjusted according to the dose of the proton beam, and it is possible to easily implement the correct circuit driving, the power consumption of the device, and the performance improvement.

In addition, the present invention provides a circuit design method for controlling the threshold voltage of the transistors constituting the circuit without any additional device to the logic circuit by using the proton beam, and improve the operation and performance of the correct circuit according to the dose of the proton beam. do.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 and 2 are flowcharts sequentially illustrating a process of manufacturing a hybrid nanodevice logic circuit according to an embodiment of the present invention, and FIG. 3 is a bottom manufactured according to the process shown in FIGS. 1 and 2. A cross-sectional view showing a process of irradiating a proton beam to a complementary inverter circuit composed of a n-type semiconductor nanowire having a gate structure and a hybrid channel of a p-type semiconductor carbon nanotube.

In order to manufacture a hybrid nanodevice logic circuit, first, a p-type semiconductor carbon nanotube 250 dispersed as shown in FIG. 2A is coated on a silicon substrate 210 on which a silicon oxide film 220 is formed (S110). . At this time, except for the region where the p-type semiconductor carbon nanotubes 250 are applied, the semiconductor nanowire region to be applied later is distinguished from the semiconductor carbon nanotube region by covering by using a photoresist 280.

In the process of manufacturing semiconductor carbon nanotubes, arc-discharge, plasma reaction, chemical vapor deposition, single-walled carbon nanotubes, multi-walled carbon nanotubes, carbon nano Any method of manufacturing a tube bundle can be used.

As a coating method, a solution drop method or a spin coating method for dropping carbon nanotubes together with a solution and then evaporating the solution may be used. Ultrasonication, ball milling, polishing and friction, dispersion using high shear forces, dispersion with solvents and dispersants, dispersion with strong acids, dispersion with polymers, and the like can be used. FIG. 4 is an atomic force microscope photograph of a single-walled carbon nanotube network dispersed by sonication in a dichlorobenzene (1,2-diclhlorobenzene) solution and sprayed onto a substrate according to an embodiment of the present invention. to be.

Thereafter, after removing the photoresist 280, heat treatment is performed for 24 hours in a vacuum oven at 180 ℃ to remove dichlorobenzene used as a dispersion and coating solution on the surface of the carbon nanotubes.

Subsequently, as shown in FIG. 2B, a source electrode 230a and a drain electrode 230b of the semiconductor carbon nanotubes are formed through a lithography process (S120). In this case, the distance between the source electrode 230a and the drain electrode 230b is preferably about 3-4 μm and the thickness is about 100 nm to 200 nm, and in order to minimize contact resistance with the semiconductor carbon nanotubes, It is formed of a metal layer forming an ohmic contact (Ohmic Contact). Preferably, the source electrode 230a and the drain electrode 230b may have an ohmic contact layer 232 such as titanium (Ti), platinum (Pt), gold (Au), and palladium (Pd) having a thickness of 50 nm to 100 nm. And an antioxidant film 234 formed of metal such as gold (Au), platinum (Pt), or palladium (Pd) at a thickness of 50 nm to 100 nm thereon.

Thereafter, as illustrated in FIG. 2C, after the carbon nanotubes are connected between the source electrode 230a and the drain electrode 230b to cover a region formed using the photoresist 280, a carbon dioxide snow jet washing method is performed. (CO ₂ Snow Jet cleaning) or chemical ion etching (RIE) to remove the carbon nanotubes outside the photoresist coating area. Thereafter, as shown in FIG. 2D, the photoresist 280 in the carbon nanotube region is removed. 5 is an atomic force micrograph of a semiconductor carbon nanotube transistor having a source and a drain electrode formed thereon as an embodiment of the present invention. As shown in FIG. 5, in the semiconductor carbon nanotube transistor according to the present invention, it can be seen that a plurality of semiconductor carbon nanotubes form a network and connect the source and drain electrodes.

Next, as shown in FIG. 2E, the region in which the p-type semiconductor carbon nanotube transistor is formed is covered by using a photoresist 280, and the n-type semiconductor nanowire 240 is formed on the silicon oxide film 220. It is applied on the silicon substrate 210 (S130).

Here, when nanowires and carbon nanotubes are used as semiconductor channels of logic circuits, the current density of each carbon nanotube is relatively lower than that of nanowires, so the current between the nanowire transistor and the carbon nanotube transistor is In order to balance the density, it is stable to form a channel using a single nanowire in the case of a nanowire transistor, and form a channel through a plurality of carbon nanotubes in the case of a carbon nanotube transistor.

The semiconductor nanowires are grown by synthesizing the semiconductor nanowires on a substrate for synthesizing the semiconductor nanowires such as a silicon substrate and an alumina substrate, and in synthesizing the semiconductor nanowires, chemical vapor deposition (CVD), organometallic chemistry Catalyst or non-catalyst methods can be used, such as the vapor deposition method (Metalorganic Chemical Vapor Deposition), Pulsed Laser Deposition (PLD), Molecular Beam Epitaxy (MBE), etc. . FIG. 6 is a scanning electron micrograph of zinc oxide (ZnO) nanowires grown vertically on a gold catalyst coated alumina substrate according to an embodiment of the present invention. When the nanowires are synthesized and grown, the semiconductor nanowire substrate is immersed in a solution, and the synthesized nanowires are separated from the substrate by ultrasonic vibration.

The coating method may include a solution drop method or a spin coating method of dropping semiconductor nanowires together with a solution and then evaporating the solution. Examples of the solution may include distilled water, ethanol, acetone, Methanol and the like can be used.

Subsequently, as shown in FIG. 2F, a source electrode 230d and a drain electrode 230c of the semiconductor nanowire are formed through a lithography process (S140). In this case, the distance between the source electrode 230d and the drain electrode 230c is preferably about 3-4 μm, and the thickness is about 100 nm to 200 nm, and the semiconductor nanowire and ohmic contact are minimized to minimize contact resistance with the semiconductor nanowire. It is formed of a metal layer forming an ohmic contact.

Preferably, the source electrode 230d and the drain electrode 230c may have a work function such as titanium (Ti), tantalum (Ta), aluminum (Al), and niobium (Nb) having a thickness of 50 nm to 100 nm. And an ohmic contact layer 232 formed of small metals, and an antioxidant film 234 formed of metal such as gold (Au), platinum (Pt), or palladium (Pd) in a thickness of 50 nm to 100 nm. 7 is a scanning electron micrograph of a zinc oxide (ZnO) nanowire transistor having a source and a drain electrode formed thereon as an embodiment of the present invention.

Subsequently, as shown in FIG. 2G, the drain electrode 230c of the n-type semiconductor nanowire transistor and the drain electrode 230b of the p-type semiconductor carbon nanotube transistor are formed through a lithography process or a shadow mask. An inverter circuit is configured by connecting to 260 (S150). Preferably, the metal line 260 is made of metal such as aluminum (Al), gold (Au), platinum (Pt), or copper having a thickness of 50 nm to 100 nm.

As shown in FIG. 3, the proton beam 270 is irradiated to the nanodevice inverter circuit manufactured as described above (S160). The irradiation of the proton beam is for precisely adjusting the threshold voltage of the n-type semiconductor nanowire transistor in the logic circuit formed as described above, so as to specify the electrical characteristics of the logic circuit appropriately for use, and to drive the logic circuit. Enables modeling of changes in voltage In this regard, it will be described in more detail in the description related to FIGS. 8 to 10 to be described later.

In this example, the amount of protons irradiated to the circuit was adjusted to about 10 ¹¹ to 10 ¹² protons / cm ² by irradiating a proton beam having an energy of 10MeV for 6 to 60 minutes. In addition, in the present embodiment, after the fabrication of the nano device inverter consisting of the n-type semiconductor nanowire transistor and the p-type semiconductor carbon nanotube transistor is completed, the proton beam is irradiated to the manufactured nano device inverter. It does not need to be performed after the inverter is manufactured, and may be performed at any time after applying nanowires and carbon nanotubes on a silicon substrate.

Hereinafter, the threshold voltage change of the transistor and the drive voltage change of the logic circuit according to the proton beam irradiation in the hybrid type complementary logic circuit formed in this manner will be described with reference to FIGS. 8 to 10.

FIG. 8 illustrates a comparison of electrical characteristics of transistor devices according to irradiation of proton beams to n-type semiconductor nanowire transistors and p-type semiconductor carbon nanotube transistors constituting a hybrid complementary logic circuit according to an embodiment of the present invention. As a graph, in order to examine the change of the source-drain current according to the gate voltage, the proton beam was irradiated to the nanowire transistor and the carbon nanotube transistor at the dose amounts of 10 ¹¹ protons / cm ² and 10 ¹² protons / cm ² , respectively. The source and drain currents are shown according to the gate voltage.

As shown in FIG. 8, in the case of the n-type semiconductor nanowire transistor, a white bead representing a source-drain current irradiated with a proton beam and a red bead representing a source-drain current irradiated with a proton beam are compared. ^The graph shifts 2.19 V in the positive direction of the threshold voltage for a low dose of ¹¹ protons / cm ² and 4.42 V in the positive direction of the threshold voltage for a high dose of 10 ¹² protons / cm ² . It can be seen that a larger change in the threshold voltage appears. In contrast, in the case of a p-type semiconductor carbon nanotube transistor, when comparing a white bead representing a source-drain current not irradiated with a proton beam and a blue bead representing a source-drain current irradiated with a proton beam, 10 ¹¹ protons / cm ^The proton beams were irradiated with doses of ² and 10 ¹² protons / cm ² , respectively.

As described above, the magnitude of the threshold voltage change of the n-type semiconductor nanowire transistor can be adjusted according to the dose of the proton beam. In other words, it can be seen that the threshold voltage changes only for the n-type semiconductor nanowire transistor selectively according to the proton beam irradiation. It becomes possible.

Therefore, due to the structure that can only change the threshold voltage of the n-type semiconductor nanowire transistor by using the proton beam, after the fabrication of a logic circuit such as an inverter using a nanowire and carbon nanotube hybrid channel, The characteristic change can be predicted more easily, and the modeling of the change of the driving voltage of the logic circuit after the proton beam irradiation is made possible.

9 is a graph showing a change in driving voltage and switching characteristics according to irradiation of a proton beam by irradiating a proton beam to a hybrid complementary inverter logic circuit composed of nanowires and carbon nanotube nanodevices according to an embodiment of the present invention. In this paper, the proton beam is irradiated with the dose of 10 ¹¹ protons / cm ² and 10 ¹² protons / cm ² , respectively. As shown in FIG. 9, the threshold voltage change of the n-type semiconductor nanowire transistor was larger at a dose of 10 ¹² protons / cm ² than at a dose of 10 ¹¹ protons / cm ² . It can be seen that the drive voltage of the inverter is greater at the dose of 10 ¹² protons / cm ² than at the dose of ¹¹ protons / cm ² .

Preferably, as mentioned above, it can be seen that the threshold voltage change of the transistor according to the change of the dose amount, which can easily predict the magnitude of the operating voltage change of the inverter logic circuit. It also shows that the operating voltage of a faulty nanodevice logic circuit can be changed to an inverter logic circuit that shows the correct drive without a separate additional device, a level shifting element. In addition, it can be seen that the inverter gain is greatly increased after the proton beam irradiation and the switching characteristics of the logic circuit are also improved. Increasing the inverter gain means that the change from logical 1 to logical 0 changes more rapidly, which improves the noise margin and provides high reliability in the implementation of highly integrated logic circuits.

The characteristic change of the logic circuit may vary according to the energy and the amount of irradiation of the proton beam to be irradiated, and various characteristics by irradiating a proton beam having an energy of about 10 KeV ~ 800MeV in the range of 10 ⁸ to 10 ¹⁴ protons / cm ² . It can make a difference.

Therefore, by selectively irradiating a proton beam having a different dose amount to each inverter element to match the threshold voltage between the n-type semiconductor nanowire transistor and the p-type semiconductor carbon nanotube transistor, the desired operation without additional equipment Inverter circuits can be designed and changed in the voltage range, which reduces power consumption, improves inverter gain and noise margin, and enables the characteristics of logic devices with excellent performance. High reliability and realism.

FIG. 10 is a graph showing a structure of a NOR gate and a NAND gate composed of n-type semiconductor nanowires and p-type semiconductor carbon nanotube hybrid channels and time-output voltage results after irradiation of a proton beam according to an embodiment of the present invention. When a proton beam is irradiated to a NOR gate or a NAND gate composed of a hybrid channel, as shown in FIG. 10, the logic gate shows a preferable output result. The logic gate is a logic circuit that processes binary information input as 0 or 1, and includes two or more input terminals and one output terminal.

NOR gate is output 0 when one or more inputs is 1, output is 1 when all inputs are 0. In the NAND gate, the output is 0 when one or more of the inputs is 0, and when all inputs are 1, the output becomes 0. Such a logic gate requires a good match between the current and the threshold voltage between the semiconductor devices constituting the logic gate to obtain a desirable output result. In the present invention, it is possible to selectively control the threshold voltages of the nanowire transistors and the carbon nanotube transistors constituting the logic gate by using a proton beam, thereby showing a preferable driving result of the hybrid complementary logic circuit.

1 and 2 illustrate an inverter structure including a nanowire transistor and a carbon nanotube transistor having a bottom-gate structure and a manufacturing process thereof, but the present invention is not limited to a transistor and an inverter having a bottom-gate structure. In addition, the inverter is composed of an inverter composed of a transistor having a top-local gate structure, and an inverter composed of a structure in which a metal gate electrode is directly contacted with a nanowire transistor and a carbon nanotube transistor. Of course it is possible.

11 is a cross-sectional view of a hybrid complementary inverter with a top-local gate structure in accordance with another embodiment of the present invention.

In the hybrid type complementary inverter having a top-local gate structure shown in FIG. 11, an n-type semiconductor nanowire 240 and a p-type semiconductor carbon nanotube 250 are coated on a silicon substrate 210 on which a silicon oxide film 220 is formed. Afterwards, the source and drain electrodes 230 are formed. In addition, a gate insulating layer 310 is formed on the coated n-type semiconductor nanowire 240 and the p-type semiconductor carbon nanotube 250, and a top gate electrode 320 is formed on the gate insulating layer 310. The gate insulating layer 310 may use one of a silicon oxide film, an aluminum oxide film (Al ₂ O ₃ ), a hafnium oxide film (Hf ₂ 0), a zirconium oxide film (ZrO ₂ ), and a polymer insulating film, and a sputtering deposition It is formed to a thickness of 10 nm to 300 nm using a method such as atomic layer deposition (LP), low pressure chemical vapor deposition (LPCVD).

Subsequently, an inverter circuit is connected by connecting the drain electrode 230c of the n-type semiconductor nanowire transistor and the drain electrode 230b of the p-type semiconductor carbon nanotube transistor with a metal line 260 through a lithography process or a shadow mask. Configure.

12 illustrates a semiconductor nanowire and a carbon nanotube transistor having a structure in which a metal top-local gate electrode is in direct contact with an n-type semiconductor nanowire and a p-type semiconductor carbon nanotube hybrid channel. A diagram of a hybrid complementary inverter.

As shown in FIG. 12, a hybrid complementary inverter including an n-type semiconductor nanowire transistor and a p-type semiconductor carbon nanotube transistor having a structure in which a metal gate electrode is directly contacted with a transistor channel includes a silicon oxide film 220. After the n-type semiconductor nanowires 240 and the p-type semiconductor carbon nanotubes 250 are coated on the silicon substrate 210, the source and drain electrodes 230 are formed, and the coated n-type semiconductor nanowires 240 are formed. The top gate electrode 320 is formed on the p-type semiconductor carbon nanotube 250 and is in direct contact with the n-type semiconductor nanowire 240 and the p-type semiconductor carbon nanotube 250.

Subsequently, an inverter circuit is connected by connecting the drain electrode 230c of the n-type semiconductor nanowire transistor and the drain electrode 230b of the p-type semiconductor carbon nanotube transistor with a metal line 260 through a lithography process or a shadow mask. Configure.

In the inverter composed of a nanowire transistor and a carbon nanotube transistor as shown in FIGS. 11 and 12, the driving voltage is selectively adjusted by irradiating a proton beam to reduce the correct operating voltage and power consumption of the logic circuit. It can be used as a method for improving device performance as described above.

The present invention described above is not limited to the above-described embodiment and the accompanying drawings, and do not depart from the spirit of the present invention. It will be apparent to those skilled in the art that various substitutions, modifications, and alterations are possible within the scope of the present invention.

According to the present invention, a threshold voltage change of a transistor can be known according to a change in the dose of a proton beam, which facilitates circuit design by easily predicting and controlling the magnitude of an operating voltage change of an inverter logic circuit.

In addition, it provides a way for the inverter circuit to show the correct calculation result only by irradiation of the proton beam without any additional device in the logic circuit, and improves the switching characteristics of the inverter with high inverter gain and excellent noise margin to realize low power consumption and logic circuit. It enables to provide high reliability and realism for the practical use of highly integrated logic circuit using nano devices.

1 is a flowchart sequentially showing a process of manufacturing a hybrid nanodevice logic circuit according to an embodiment of the present invention.

2 is a view sequentially showing a process of manufacturing a hybrid nano device logic circuit according to an embodiment of the present invention.

3 is a cross-sectional view illustrating a process of irradiating a proton beam to a complementary inverter circuit composed of an n-type semiconductor nanowire having a bottom-gate structure and a p-type semiconductor carbon nanotube hybrid channel;

Figure 4 is an atomic force micrograph of a single-walled carbon nanotube network sprayed on a substrate in accordance with an embodiment of the present invention.

5 is an atomic force micrograph of a semiconductor carbon nanotube transistor having a source and a drain electrode formed thereon as an embodiment of the present invention.

6 is a scanning electron micrograph of zinc oxide (ZnO) nanowires grown vertically on a gold catalyst coated alumina substrate in accordance with one embodiment of the present invention.

7 is a scanning electron micrograph of a semiconductor nanowire transistor having a source and a drain electrode formed thereon as an embodiment of the present invention.

8 is a graph showing a comparison of electrical characteristics of a transistor device according to irradiation of a proton beam in a hybrid complementary inverter logic circuit composed of nanowires and carbon nanotube nanodevices according to an embodiment of the present invention.

9 is a graph showing a change in driving voltage and switching characteristics according to an irradiation amount of a proton beam irradiated to a hybrid complementary inverter logic circuit composed of nanowires and carbon nanotube nanodevices according to an embodiment of the present invention.

10 is a graph showing the NOR gate and NAND gate structure composed of n-type semiconductor nanowires and p-type semiconductor carbon nanotube hybrid channels and time-output voltage results after irradiation of a proton beam according to an embodiment of the present invention.

11 is a cross-sectional view of a hybrid complementary inverter with a top-local gate structure in accordance with another embodiment of the present invention.

12 illustrates a semiconductor nanowire and a carbon nanotube transistor having a structure in which a metal top-local gate electrode is in direct contact with an n-type semiconductor nanowire and a p-type semiconductor carbon nanotube hybrid channel. Drawing of hybrid type complementary inverter.

* Description of the symbols for the main parts of the drawings *

210: silicon substrate 220: silicon oxide film

230: source / drain electrodes 240: semiconductor nanowires

250: semiconductor carbon nanotube 260: metal line

270 proton beam 280 photoresistor

310: gate insulating film 320: top gate electrode

Claims (9)

In the hybrid nano device logic circuit, A silicon substrate on which a silicon oxide film is formed; A p-type semiconductor carbon nanotube transistor formed of a source electrode and a drain electrode formed on one side of the substrate and semiconductor carbon nanotubes connecting the same; An n-type semiconductor nanowire transistor comprising a source electrode and a drain electrode formed on the other side of the substrate and semiconductor nanowires connecting the same; A metal line connecting the drain electrode of the p-type semiconductor carbon nanotube transistor and the drain electrode of the n-type semiconductor nanowire transistor; Hybrid nano device logic circuit, characterized in that consisting of. The method of claim 1, The p-type semiconductor carbon nanotube transistor, Hybrid nano device logic circuit comprising a plurality of semiconductor carbon nanotubes are configured in the form of a network connecting the source electrode and the drain electrode. The method of claim 1, Semiconductor nanowires forming the n-type semiconductor nanowire transistor, Hybrid nano device logic circuit, characterized in that the zinc oxide (ZnO) nanowires. In the method of manufacturing a hybrid nano-device logic circuit, Applying a semiconductor carbon nanotube to a predetermined region on a silicon substrate on which a silicon oxide film is formed; Forming a source electrode and a drain electrode on the coated semiconductor carbon nanotubes; Removing the carbon nanotubes in the remaining region except for the semiconductor carbon nanotubes of a predetermined portion that is applied between the source electrode and the drain electrode to connect the source electrode and the drain electrode; Applying a semiconductor nanowire to a predetermined region on the silicon substrate; Forming a source electrode and a drain electrode on the coated semiconductor nanowire; Connecting a drain electrode connected to the semiconductor carbon nanotube and a drain electrode connected to the semiconductor nanowire with a metal line; Hybrid nano device logic circuit manufacturing method characterized in that it is formed, including. The method of claim 4, wherein The hybrid nano device logic circuit manufacturing method, Method of manufacturing a hybrid nano-device logic circuit characterized in that the balance of the current density between the semiconductor nanowires and the semiconductor carbon nanotubes by forming a plurality of networks of semiconductor carbon nanotubes connecting the source electrode and the drain electrode . The method of claim 4, wherein The hybrid nano device logic circuit manufacturing method, And irradiating a proton beam to the semiconductor carbon nanotubes and the semiconductor nanowires formed on the substrate. The method of claim 6, The proton beam is irradiated with a dose of 10 ⁸ ~ 10 ¹⁴ protons / cm ² proton beam having an energy of 10 KeV ~ 800 MeV, hybrid nano device logic circuit using a proton beam. The method of claim 6, The method of claim 1, wherein the proton beam is irradiated during the manufacturing process after coating the semiconductor nanowires and the semiconductor carbon nanotubes on a silicon substrate. The method of claim 6, The method of claim 1, wherein the irradiation of the proton beam is performed after the manufacture of the hybrid nano device logic circuit is completed.

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