KR20100058230A - Liquid crystal display device - Google Patents

Liquid crystal display device Download PDF

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Publication number
KR20100058230A
KR20100058230A KR1020080116972A KR20080116972A KR20100058230A KR 20100058230 A KR20100058230 A KR 20100058230A KR 1020080116972 A KR1020080116972 A KR 1020080116972A KR 20080116972 A KR20080116972 A KR 20080116972A KR 20100058230 A KR20100058230 A KR 20100058230A
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KR
South Korea
Prior art keywords
printed circuit
substrate
group
bump
circuit pad
Prior art date
Application number
KR1020080116972A
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Korean (ko)
Inventor
김동규
Original Assignee
엘지디스플레이 주식회사
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Priority to KR1020080116972A priority Critical patent/KR20100058230A/en
Publication of KR20100058230A publication Critical patent/KR20100058230A/en

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13452—Conductors connecting driver circuitry and terminals of panels
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13458—Terminal pads

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

PURPOSE: An LCD device is provided to minimize loss of a circuit or a defect causing risk, thereby improving production yield. CONSTITUTION: A liquid crystal layer is located between the first substrate(110) and the second substrate. A substrate pad array is located on the first substrate. An external circuit board(188) comprises an external circuit pad array(EPA). A PCB(Printed Circuit Board)(140) comprises printed circuit pad arrays(PPA1,PPA2). The printed circuit pad arrays are respectively connected to the substrate pad array and the external circuit pad array. The width of at least one of printed circuit pads in the printed circuit pad arrays is narrower than an adjacent printed circuit pad.

Description

[0001] The present invention relates to a liquid crystal display device,

An embodiment of the present invention relates to a liquid crystal display device.

With the development of information technology, the market for a display device, which is a connection medium between a user and information, is growing. Accordingly, flat panel displays (FPDs), such as liquid crystal displays (LCDs), organic light emitting diodes (OLEDs), and plasma display panels (PDPs), may be used. Usage is increasing. Among them, a liquid crystal display device capable of realizing high resolution and capable of large size as well as small size is widely used.

Liquid crystal displays are classified into light receiving displays. The LCD may display an image by receiving a light source from a backlight unit disposed under the liquid crystal panel. The LCD includes a liquid crystal panel including a color filter substrate and a transistor array substrate, and a backlight unit for providing light to the liquid crystal panel. In the case of the liquid crystal panel included in the liquid crystal display, a driving signal is supplied from the driver. The driver may include a data driver for supplying a data signal to the liquid crystal panel and a gate driver for supplying a gate signal.

The transistor array substrate and the driver of the liquid crystal panel are electrically connected by a pad-to-pad connection through a tape automated bonding (TAB) process. When the TAB process is completed, a TAB inspection process is performed to check whether the liquid crystal display is operating normally. In the case of the TAB process, the operator picks up the liquid crystal display using an adsorber and then places the TAB portion on the inspection circuit board mounted on the inspection equipment to check whether the liquid crystal display is operating normally. However, in the conventional liquid crystal display device, if a misalignment occurs between the pad formed in the driver and the pad formed on the inspection circuit board, there is a risk of loss or defect of the circuit and improvement thereof is required.

An embodiment of the present invention for solving the above problems of the background art is to provide a liquid crystal display device that can minimize the risk of circuit loss or defects even if a misalignment occurs between pads in the TAB inspection process.

Embodiments of the present invention by means of the above-mentioned problem solving means, the first substrate with a transistor formed; A second substrate facing the first substrate and spaced apart from the first substrate; A liquid crystal layer positioned between the first substrate and the second substrate; A substrate pad group on the first substrate; An external circuit board connected to the first substrate and including an external circuit pad group; A printed circuit board including a printed circuit pad group connected to a substrate pad group and an external circuit pad group, respectively, wherein at least one of the printed circuit pads included in the printed circuit pad group is narrower than a width of an adjacent printed circuit pad. A liquid crystal display device is provided.

The printed circuit pad having a width narrower than the width of the printed circuit pad positioned in the periphery of the printed circuit pad group may be located in an area connected to the external circuit pad group.

The printed circuit pads connected to the substrate pad group among the printed circuit pad groups may have a width narrower than the width of the printed circuit pads connected to the external circuit pad group.

Among the printed circuit pad groups, a printed circuit pad that transmits a low voltage and a neighboring printed circuit pad may have a width smaller than that of an adjacent printed circuit pad.

The printed circuit pad having a narrow width among the printed circuit pad groups may be a pad that transmits a high voltage.

On the other hand, in another aspect, an embodiment of the present invention, the first substrate on which the transistor is formed; A second substrate facing the first substrate and spaced apart from the first substrate; A liquid crystal layer positioned between the first substrate and the second substrate; A substrate pad group on the first substrate; An external circuit board connected to the first substrate and including an external circuit pad group; And a printed circuit board including a PCB pad group, a printed circuit pad group connected to the external circuit pad group, a bump group on which a driving chip is mounted, and a connection wiring group connecting the printed circuit pad group and the bump group. A bump to which a low voltage is transmitted among the bump groups provides a liquid crystal display including a first bump connected to a printed circuit pad group and a second bump electrically connected to the printed circuit pad group.

The first bump and the second bump of the bump group may be located in an area that is connected to the external circuit pad group.

The second bumps may be connected to the first bumps by dummy wires positioned in the center area of the bump group.

The second bump may be located between the bumps through which the high voltage is transmitted.

The connection wiring defined to connect the printed circuit pad group and the second bump among the connection wiring groups may be disconnected or omitted on the printed circuit board.

According to an exemplary embodiment of the present invention, even if a misalignment occurs between pads in a TAB inspection process, there is an effect of providing a liquid crystal display device which can minimize a risk of loss or defect of a circuit. In addition, the embodiment of the present invention can minimize the risk of causing a loss or defect of the circuit has the effect of improving the production yield.

Hereinafter, with reference to the accompanying drawings, the specific content for the practice of the present invention will be described.

1 is an exploded perspective view of a liquid crystal display device.

As illustrated in FIG. 1, the liquid crystal display device may include a liquid crystal panel 130, a driver 189, and a backlight unit 179.

The liquid crystal panel 130 may have a structure in which the first substrate 110 having the transistor array and the second substrate 120 having the color filter are bonded to each other with the liquid crystal layer interposed therebetween. In the liquid crystal panel 130, subpixels driven independently by a transistor are arranged in a matrix, and each subpixel is applied to a difference voltage between a common voltage supplied to a common electrode and a data signal supplied to a pixel electrode connected to the transistor. Accordingly, an image can be displayed by controlling the liquid crystal array to adjust the light transmittance.

The backlight unit 179 may include a cover bottom 180, a lamp 171, a diffusion plate 172, a diffusion sheet 173, an optical sheet 174, a protective sheet 175, and the like. Herein, in the case of the lamp 171, a cold cathode fluorescent lamp (CCFL), a hot cathode fluorescent lamp (HCFL), an external electrode fluorescent lamp (EEFL), a light emitting diode ( Light Emitting Diode: LED) may be used, but is not limited thereto. In the optical sheet 174, a sheet such as a prism, a lenticular lens, a micro lens, or the like may be used, but is not limited thereto.

The driving unit 189 includes a plurality of printed circuit boards 140 mounted on a driving chip 150 for supplying driving signals to data lines and gate lines connected to the liquid crystal panel 130 and connected to one side of the first substrate 110. ) And an external circuit board 188 connected to the first substrate 110. The printed circuit pad sub-group formed on the plurality of printed circuit boards 140 includes the external circuit pad sub-group and the first substrate formed on the external circuit board 188 to electrically connect the external circuit board 188 and the first substrate 110. It is connected to the board | substrate pad part group formed on the 110, respectively. As such, the printed circuit board 140 on which the driving chip 150 is mounted may be positioned in a chip on film (COF) or tape carrier package (TCP) method. However, the driving chip 150 may be directly mounted on the first substrate 110 by a chip on glass (COG) method or may be formed and embedded on the first substrate 110 in a transistor forming process.

The liquid crystal panel 130 and the backlight unit 179 displaying the abnormal image may be accommodated by the cover top 190 and the cover bottom 180. The cover top 190 may accommodate the liquid crystal panel 130, and the cover bottom 170 may receive the backlight unit 179. Meanwhile, the liquid crystal panel 130 may be positioned at a predetermined interval on the backlight unit 179. The liquid crystal panel 130 and the backlight unit 179 may be fixed and protected by the cover top 190 fastened to the cover bottom 180. Here, an opening for exposing the image display area of the liquid crystal panel 130 may be provided on the upper surface of the cover top 190.

The liquid crystal panel 130 described above may display an image on each subpixel according to a scan signal supplied through the gate lines and a data voltage supplied through the data lines. The scan signal may be, but is not limited to, a pulse signal in which the gate high voltage supplied for one horizontal time and the gate low voltage supplied for the remaining time are alternated.

The transistor included in the subpixel may be turned on when a gate high voltage is supplied from the gate lines, and may supply a data voltage applied from the data lines to the liquid crystal layer. Accordingly, when the transistor of each subpixel is turned on and the data voltage is applied to the pixel electrode, the liquid crystal display may display an image while charging the difference voltage between the data voltage and the common voltage in the liquid crystal layer.

On the contrary, when the gate low voltage is supplied from the gate lines, the transistor may be turned off and the data voltage charged in the liquid crystal layer may be maintained by the storage capacitor for one frame period. Meanwhile, the liquid crystal panel 130 may repeat different operations according to the scan signal supplied through the gate wirings.

Hereinafter, the liquid crystal panel will be described.

2 is a cross-sectional view of the liquid crystal panel. 2 is only for the understanding of the liquid crystal panel, the liquid crystal panel according to the exemplary embodiment of the present invention is not limited thereto.

Referring to FIG. 2, the liquid crystal panel may have a bonded structure with the liquid crystal layer 125 positioned between the first substrate 110 and the second substrate 120 interposed therebetween.

The gate 111 may be located on one surface of the first substrate 110. The gate 111 is any one selected from the group consisting of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu). It may be made of one or an alloy thereof. In addition, the gate 111 may include molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). It may be a multilayer made of any one or alloys thereof. In addition, the gate 111 may be a double layer of molybdenum / aluminum-neodymium or molybdenum / aluminum.

The first insulating layer 112 may be positioned on the gate 111. The first insulating layer 112 may be a silicon oxide layer (SiOx), a silicon nitride layer (SiNx), or a multilayer thereof, but is not limited thereto.

An active layer 114a positioned in a region corresponding to the gate 111 may be positioned on the first insulating layer 112, and an ohmic contact layer 114b lowering a contact resistance may be disposed in the active layer 114a. have. In addition, a data pad 113 to which a data voltage is supplied may be positioned on the first insulating layer 112, but is not limited thereto.

The source 115 and the drain 116 may be positioned on the active layer 114a. The source 115 and the drain 116 may be formed of a single layer or multiple layers. When the source 115 and the drain 116 are a single layer, molybdenum (Mo), aluminum (Al), chromium (Cr), and gold may be used. (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu) may be made of any one or an alloy thereof selected from the group consisting of. In addition, when the source 115 and the drain 116 are multiple layers, the double layer of molybdenum / aluminum-neodymium and the triple layer of molybdenum / aluminum / molybdenum or molybdenum / aluminum-neodymium / molybdenum may be used.

The second insulating layer 117 may be positioned on the source 115 and the drain 116. The second insulating layer 117 may be a silicon oxide layer (SiOx), a silicon nitride layer (SiNx), or a multilayer thereof, but is not limited thereto. The second insulating layer 117 may be a passivation layer.

The pixel electrode 118 connected to the source 115 or the drain 116 may be positioned on the second insulating layer 117. The pixel electrode 118 may be one of indium tin oxide (ITO), indium zinc oxide (IZO), or zinc oxide (ZnO).

The common electrode (not shown) may be positioned on the second insulating layer 117 to face the pixel electrode 118. The common electrode may be located on the first substrate 110 or the second substrate 120 according to the driving method.

A spacer 119 may be positioned on the first substrate 110 to maintain a cell gap with the second substrate 120 on the second insulating layer 117 corresponding to the source 115 and the drain 116. have.

The black matrix 121 may be positioned on one surface of the second substrate 120. The black matrix 121 is a non-display area and may be positioned to correspond to the area where the spacer 119 is located. The black matrix 121 is made of a photosensitive organic material to which a black pigment is added, and as the black pigment, carbon black or titanium oxide may be used.

The color filters 120R, 120G, and 120B may be positioned between the black matrices 121. The color filters 120R, 120G, and 120B may have other colors as well as red (120R), green (120G), and blue (120B).

The overcoat layer 122 may be disposed on the black matrix 121 and the color filters 120R, 120G, and 120B. The overcoating layer 122 may be omitted depending on the structure of the second substrate 120 having the black matrix 121 and the color filters 120R, 120G, and 120B.

The common electrode 123 to which the common voltage is supplied may be positioned on the overcoat layer 122. The common electrode 123 is an electrode for controlling the liquid crystal layer 125 together with the pixel electrode 118 and may be positioned on the first substrate 110 according to the structure.

3 is a partially exploded perspective view of the liquid crystal panel.

Referring to FIG. 3, a data driver 189a is connected to one side of the first substrate 110 where the display area AA is located, and a gate driver 189b is connected to the other side of the first substrate 110. The data driver 189a may include a first printed circuit board 140a and a first external circuit board 188a on which the data driver chip 150a is mounted. The gate driver 189b may include a second printed circuit board 140b and a second external circuit board 188b on which the gate driver chip 150b is mounted. However, according to the structure, the gate driver 189b may be mounted on the first substrate 110, but the gate driver 189b is connected to the first substrate 110 in an embodiment of the present invention.

EMBODIMENT OF THE INVENTION Hereinafter, the Example of this invention is described.

First Embodiment

4 is a view for explaining a first embodiment of the present invention, Figure 5 is an enlarged view of the region Y in FIG.

Referring to FIG. 4, a plurality of pad groups SPA, PPA1, PPA2, and EPA and printed circuit boards 140 disposed on the first substrate 110, the printed circuit board 140, and the external circuit board 188. A bump group ICA is shown and mounted on the drive chip. The arrangement of the plurality of pad groups SPA, PPA1, PPA2, and EPA shown and the arrangement of the bump group ICA and the connection wiring group L formed on the printed circuit board 140 are provided only for better understanding of the description. It is not limited.

The substrate pad group SPA is disposed on the first substrate 110, and the printed circuit pad groups PPA1 and PPA2 are positioned on the printed circuit board 140, and the external circuit pad group EPA is the external circuit board 188. Located in the phase. Here, the first substrate 110 and the external circuit board 188 are connected by two printed circuit pad groups PPA1 and PPA2 and the connection wiring group L positioned on the printed circuit board 140.

Printed circuit pad groups PPA1 and PPA2 positioned on the printed circuit board 140 may include a first printed circuit pad group PPA1 connected to an external circuit pad group EPA and a substrate pad group SPA. The printed circuit pad group PPA2 may be included. At least one of the printed circuit pads included in the printed circuit pad groups PPA1 and PPA2 may have a width smaller than that of the adjacent printed circuit pads. Here, the printed circuit pad having a width smaller than the width of the adjacent printed circuit pads among the printed circuit pad groups PPA1 and PPA2 is the first printed circuit pad group PPA1 positioned in an area connected to the external circuit pad group EPA. ) May be included.

Referring to FIG. 5, printed circuit pads VCC and VDD having a narrow width among the first printed circuit pad groups PPA1 are pads that transmit a high voltage. Here, the narrow width printed circuit pads VSS and VDD may be pads adjacent to the printed circuit pad VSS that transmits a low voltage among the printed circuit pad group PPA1.

Hereinafter, the first embodiment of the present invention and the prior art will be described.

6 is a view for explaining the prior art and the first embodiment.

Referring to FIG. 6, pad groups VCC, VSS, and VDD formed on a tape automated bonding (TAB) inspection circuit board 160 and printed circuit pad groups VCC, VSS, and the like formed on a printed circuit board 140. VDD) is shown. FIG. 6A shows a prior art, and FIG. 6B shows an embodiment.

In the prior art illustrated in FIG. 6A, the widths of the plurality of pad groups VCC, VSS, and VDD formed on the test circuit board 160 and the printed circuit board 140 are the same. In the prior art, the pad groups VCC, VSS and VDD formed on the inspection circuit board 160 and the pad groups VCC, VSS and VDD formed on the printed circuit board 140 may be interconnected in the TAB inspection process. When a miss align occurs, a short ST occurs between adjacent pad groups VSS and VDD. As such, when the short ST is generated between the adjacent pad groups VSS and VDD, an overcurrent is applied to the pad VSS to which the low voltage is transmitted, thereby causing a loss or a defect of a circuit.

On the other hand, in the exemplary embodiment illustrated in FIG. 6B, the widths of the plurality of pad groups VCC, VSS, and VDD formed on the test circuit board 160 and the printed circuit board 140 are different. That is, the widths of the pads VCC and VSS that are adjacent to the pad VSS that transmits the low voltage are high. In the exemplary embodiment, when the pad groups VCC, VSS and VDD formed on the inspection circuit board 160 and the pad groups VCC, VSS and VDD formed on the printed circuit board 140 are interconnected in the TAB inspection process. Even if a misalignment occurs, since the width of the adjacent pad groups VSS and VDD is narrow, the short ST does not occur under the same conditions as in the prior art. Therefore, in the case of the embodiment, it is possible to eliminate the risk of loss or defect of the circuit due to the short ST than the prior art.

Second Embodiment

FIG. 7 is a view for explaining a second embodiment of the present invention, and FIG. 8 is an enlarged view of the Z region of FIG. 7.

Referring to FIG. 7, a plurality of pad groups SPA, PPA1, PPA2, and EPA and printed circuit boards 240 disposed on the first substrate 210, the printed circuit board 240, and the external circuit board 288. A bump group ICA is shown and mounted on the drive chip. The arrangement of the plurality of pad groups SPA, PPA1, PPA2, and EPA shown and the arrangement of the bump group ICA and the connection wiring group L formed on the printed circuit board 140 are provided only for better understanding of the description. It is not limited.

The substrate pad group SPA is disposed on the first substrate 210, the printed circuit pad groups PPA1 and PPA2 are positioned on the printed circuit board 240, and the external circuit pad group EPA is the external circuit board 288. Located in the phase. Here, the first substrate 210 and the external circuit board 288 are connected by the two printed circuit pad groups PPA1 and PPA2 and the connection wiring group L positioned on the printed circuit board 240.

Among the bump groups ICA positioned on the printed circuit board 240, bumps to which low voltage is transmitted are electrically floating with the first bumps connected to the printed circuit pad groups PPA1 and PPA2 and the printed circuit pad groups PPA1 and PPA2. The second bumps included. Here, the first bump and the second bump may be located in an area that is connected to the external circuit pad group EPA. Here, the reason why the second bump electrically connected to the printed circuit pad group PPA1 is located is that the connection wiring defined to connect the printed circuit pad group PPA1 and the second bump of the connection wiring group L is a printed circuit. This is because it is designed to be disconnected or omitted on the substrate. Meanwhile, the second bump may be connected to the first bump by the dummy wiring DL positioned in the center area of the bump group ICA. That is, the second bumps are not connected by the connection wiring L connecting the printed circuit pad group PPA1 and the second bumps, but are connected by the dummy wiring DL.

Referring to FIG. 8, the second bumps VSS that are not connected to the printed circuit pad group PPA1 among the bump groups ICA are bumps positioned between the bumps VCC and VDD through which a high voltage is transmitted. Although not shown, the first bump VSS connected to the printed circuit pad group PPA1 among the bump groups ICA is a bump that is not positioned between bumps through which a high voltage is transmitted.

The second embodiment of the present invention and the prior art will be described below.

9 is a view for explaining the prior art and the second embodiment.

In the prior art illustrated in FIG. 9A, the widths of the plurality of pad groups VCC, VSS, and VDD formed on the test circuit board 260 and the printed circuit board 240 are the same. In the prior art, the pad groups VCC, VSS and VDD formed on the inspection circuit board 260 and the pad groups VCC, VSS and VDD formed on the printed circuit board 240 may be interconnected in the TAB inspection process. When a miss align occurs, a short ST occurs between adjacent pad groups VSS and VDD. As such, when the short ST is generated between the adjacent pad groups VSS and VDD, an overcurrent is applied to the pad VSS to which the low voltage is transmitted, thereby causing a loss or a defect of a circuit.

In contrast, in the embodiment illustrated in FIG. 9B, the widths of the plurality of pad groups VCC, VSS, and VDD formed on the test circuit board 260 and the printed circuit board 240 are the same. However, in the exemplary embodiment, the connection line L of the pad group VSS positioned between the pad groups VCC and VDD transmitting high voltage is disconnected or omitted so as not to be connected. Therefore, in the exemplary embodiment, the pad groups VCC, VSS and VDD formed on the test circuit board 260 and the pad groups VCC, VSS and VDD formed on the printed circuit board 240 are interconnected in the TAB inspection process. Even if a miss align occurs, the short ST does not occur even under the same conditions as in the prior art because it is electrically floated. Therefore, in the case of the embodiment, it is possible to eliminate the risk of the circuit loss or the defect caused by the short ST.

The embodiment of the present invention has the effect of providing a liquid crystal display device that can minimize the risk of loss or defect of the circuit even if the misalignment between the pads in the TAB inspection process. In addition, the embodiment of the present invention can minimize the risk of causing a loss or defect of the circuit has the effect of improving the production yield.

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, It will be understood that the invention may be practiced. Therefore, the embodiments described above are to be understood as illustrative and not restrictive in all aspects. In addition, the scope of the present invention is shown by the claims below, rather than the above detailed description. Also, it is to be construed that all changes or modifications derived from the meaning and scope of the claims and their equivalent concepts are included in the scope of the present invention.

1 is an exploded perspective view of a liquid crystal display device;

2 is a cross-sectional view of a liquid crystal panel.

3 is a partially exploded perspective view of a liquid crystal panel.

4 is a view for explaining a first embodiment of the present invention.

5 is an enlarged view of a region Y in FIG. 4.

6 is a view for explaining the prior art and the first embodiment.

7 is a view for explaining a second embodiment of the present invention.

8 is an enlarged view of the Z region of FIG. 7.

9 is a view for explaining the prior art and the second embodiment.

<Explanation of symbols on main parts of the drawings>

110, 210: first substrate 120: second substrate

140, 240: printed circuit board 188, 288: external circuit board

160, 260: Test circuit board SPA: Board pad group

PPA1, PPA2: printed circuit pad group EPA: external circuit pad group

ICA: Bump group L: Connection wiring group

Claims (10)

A first substrate on which a transistor is formed; A second substrate facing the first substrate and spaced apart from the first substrate; A liquid crystal layer disposed between the first substrate and the second substrate; A substrate pad group on the first substrate; An external circuit board connected to the first substrate and including an external circuit pad group; A printed circuit board including a printed circuit pad group connected to the substrate pad group and the external circuit pad group, respectively; And at least one of the printed circuit pads included in the printed circuit pad group is narrower than a width of an adjacent printed circuit pad. The method of claim 1, The printed circuit pad having a width narrower than the width of the printed circuit pad located in the periphery of the printed circuit pad group, And an area connected to the external circuit pad group. The method of claim 1, The printed circuit pad connected to the substrate pad group of the printed circuit pad group, And a width narrower than a width of the printed circuit pad connected to the external circuit pad group. The method of claim 2, Among the printed circuit pad groups, a printed circuit pad that transmits a low voltage and a neighboring printed circuit pad include: And a width narrower than that of adjacent printed circuit pads. The method of claim 2, The printed circuit pad having a narrow width of the printed circuit pad group, Liquid crystal display device characterized in that the pad for transmitting a high voltage. A first substrate on which a transistor is formed; A second substrate facing the first substrate and spaced apart from the first substrate; A liquid crystal layer disposed between the first substrate and the second substrate; A substrate pad group on the first substrate; An external circuit board connected to the first substrate and including an external circuit pad group; And A printed circuit board including a printed circuit pad group connected to the substrate pad group and the external circuit pad group, a bump group on which a driving chip is mounted, and a connection wiring group connecting the printed circuit pad group and the bump group. , Among the bump groups, bumps to which a low voltage is transmitted are provided. And a second bump electrically connected to the printed circuit pad group and a second bump electrically floating with the printed circuit pad group. The method of claim 6, The first bump and the second bump of the bump group, And an area connected to the external circuit pad group. The method of claim 6, The second bump, And the first bump is connected to the first bump by a dummy wiring positioned in a center area of the bump group. The method of claim 6, The second bump, The liquid crystal display device, characterized in that located between the bump is a high voltage transmission. The method of claim 6, And a connection wiring defined to connect the printed circuit pad group and the second bump in the connection wiring group is disconnected or omitted on the printed circuit board.
KR1020080116972A 2008-11-24 2008-11-24 Liquid crystal display device KR20100058230A (en)

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