KR20100056213A - Level converting flip-flop - Google Patents

Abstract

PURPOSE: A level conversion flip-flop is provided to minimize the configuration of a circuit by generating a clock pulse through the switching of two transistors. CONSTITUTION: A clock generator(100) is driven with a first power voltage, and generates a clock pulse according to an on/off operation which uses inversed clock signals and delayed inverse clock signals. A data latch(200) uses an on/off operation according to clock pulses, saves data signals whose level is greater than a first power voltage level and less than a second power voltage level, and generates output data.

Description

Level Converting Flip-Flop}

The present invention relates to a level-converting flip-flop, and more particularly, to a level converting flip-flop for converting data of a low power supply voltage level into data of a high power voltage level.

Multiple supply voltage systems are used to minimize power consumption without reducing operating speed. This means that a particular circuit performing one function is not driven by only one type of power supply voltage, but uses two or more power sources. In particular, a flip-flop circuit is required to convert data having a low power supply voltage level into data having a high power voltage level. This level shift flip-flop must have low power consumption and high operating speed.

1 is a circuit diagram illustrating a level converting flip-flop according to the prior art.

Referring to FIG. 1, a conventional level converting flip flop includes a pulse generator 10 and a latch unit 20.

The pulse generator 10 receives the clock signal CK and generates the clock pulse CKP according to the configured logic circuit. The generated clock pulse CKP is input to the latch unit 20.

The latch unit 20 receives the clock pulse CKP and senses the input data D at the rising edge of the received CKP. The sensed input data D is stored in the latch 23 through the switching unit 21. Data stored in the latch 23 is finally represented by the output signal Q.

In the circuit, the clock signal CK, clock pulse CKP, and input data D use a low power supply voltage. That is, the power supply voltage has a relatively low value in the circuit operation in the region between the ground voltage and the power supply voltage. In addition, the latch 23 of the latch unit 20 and a buffer provided thereafter use a relatively high power supply voltage. Therefore, the high level limit of the input data D will be a low power supply voltage, but the high level limit of the output signal Q will be a high power supply voltage.

The above-described flip-flop circuit has a problem that a propagation path of a signal is rather long. That is, in the path where the input data D is received, the low level signal must propagate from the ground voltage through the two NMOS transistors. In addition, to form the clock pulse CKP, it must pass through four inverters and one NAND gate. In a typical CMOS design, two-input NAND gates require two NMOSs in series and two PMOSs in parallel. In this case, two PMOS act as active loads. As a result, when the circuit illustrated in FIG. 1 is implemented on the semiconductor substrate through layout, an excessive number of transistors is a problem. This means an increase in the area occupied by a device performing a specific function, which causes a reduction in the net die, which is the number of chips realized in one wafer, and increases the manufacturing cost.

An object of the present invention for solving the above problems is to provide a level conversion flip-flop that has a simple structure and can occupy a small area at the time of implementation.

The present invention for achieving the above object is a clock generator driven by a first power supply voltage, and generates a clock pulse by the on / off operation using the inverted clock signal and the delayed inverted clock signal; And a data latch using an on / off operation according to the clock pulse and storing and updating a data signal below a second power supply voltage level higher than the first power supply voltage, thereby updating and generating output data. To provide.

According to the present invention described above, a separate logic circuit for generating a clock pulse is not required, and a clock pulse is generated through switching of two transistors. Therefore, the configuration of the circuit can be minimized. In the storage operation of the data signal, the storage operation is controlled only by switching between two transistors. According to the arrangement of the clock generator and the data latch provided, the area occupied on the semiconductor is effectively reduced. That is, a flip-flop circuit may be configured by including a plurality of data latches in one clock generator, thereby improving efficiency of low power consumption and area.

As the inventive concept allows for various changes and numerous embodiments, particular embodiments will be illustrated in the drawings and described in detail in the text. However, this is not intended to limit the present invention to the specific disclosed form, it should be understood to include all modifications, equivalents, and substitutes included in the spirit and scope of the present invention. Like reference numerals are used for like elements in describing each drawing.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art. Terms such as those defined in the commonly used dictionaries should be construed as having meanings consistent with the meanings in the context of the related art and shall not be construed in ideal or excessively formal meanings unless expressly defined in this application. Do not.

Hereinafter, with reference to the accompanying drawings, it will be described in detail a preferred embodiment of the present invention.

Example

2 is a circuit diagram illustrating a level shift flip-flop according to a preferred embodiment of the present invention.

Referring to FIG. 2, the level shift flip-flop of this embodiment has a pulse generator 100 and a data latch 200.

The pulse generator 100 is driven by the first power supply voltage VDDL, and a part of the data latch 200 is driven by the second power supply voltage VDDH. The second power supply voltage VDDH is set to have a higher level than the first power supply voltage VDDL. For example, when the second power supply voltage VDDH is set to 1V, the first power supply voltage VDDL is preferably set to 0.7V.

In addition, the pulse generator 100 shown in FIG. 2 is driven between the first power supply voltage VDDL and the ground level. Therefore, the high level of the signal appearing in the pulse generator 100 does not exceed VDDL, and the low level does not appear lower than the ground level.

Similarly, part of the data latch 200 is driven between the first power supply voltage VDDL and the ground level, and the remainder of the data latch 200 is driven between the second power supply voltage VDDH and the ground level.

First, the pulse generator 100 receives a clock signal CK and generates a clock pulse CKP. In addition, a clock pulse is generated by an on / off operation for the inverted clock signal and the delayed inverted clock signal. To this end, the pulse generator 100 includes a clock input buffer 110, a clock delay unit 120, a switching unit 130, and a clock output buffer 140. In addition, the high level of the signals generated by the pulse generator 100 is less than or equal to the first power supply voltage VDDL. In addition, the level of the clock signal CK input to the pulse generator 100 is preferably set to the first power supply voltage VDDL or less.

The clock input buffer 110 performs the function of an inverter. That is, the clock signal CK input to the clock input buffer 110 is output in an inverted form. The inverted clock signal / CK, which is the output of the clock input buffer 110, is input to the clock delay unit 120 and the switching unit 130.

The clock delay unit 120 is connected between the output terminal of the clock input buffer 110 and the switching unit 130, receives the inverted clock signal / CK, delays the signal by a predetermined time, and outputs the delayed inverted clock signal / CKD. do. The delayed inverted clock signal / CKD, which is an output signal of the clock delay unit 120, is input to the switching unit 130.

The switching unit 130 is connected between the clock delay unit 120 and the clock output buffer 140. The switching unit 130 includes one PMOS transistor Q1 and one NMOS transistor Q2. The gate terminal of the transistor Q1 is commonly connected to the gate terminal of the transistor Q2, and the node connected in common forms an output terminal of the clock delay unit 120. The inverted clock signal / CK, which is the output of the clock input buffer 110, is applied to the source terminal of the transistor Q2.

The clock output buffer 140 is connected between the switching unit 130 and the data latch 200. The clock output buffer 140 inverts the output signal of the switching unit 130 to form a clock pulse CKP. The level of the clock pulse CKP is limited by the first power supply voltage VDDL. Therefore, the high level of the clock pulse CKP does not exceed the first power supply voltage VDDL.

The data latch 200 performs an on / off operation by using a clock pulse that is an output of a clock generator, and stores the data signal in a raised state. That is, the data is stored at an elevated level according to the second power supply voltage VDDH. To this end, the data latch 200 includes a data input buffer 210, a data switching unit 220, a data storage unit 230, and a data output buffer 240.

The data input buffer 210 and the data switching unit 220 are driven by the first power voltage VDDL. In addition, the data storage unit 230 and the data output buffer 240 are driven by the second power supply voltage VDDH. Accordingly, the signal supplied at the first power supply voltage VDDL level is raised to the second power supply voltage VDDH level higher than this through the data storage 230 and the data output buffer 240, and is output. Through this, the low level data signal D may be sensed, stored and updated, and then the high level output data Q may be formed.

First, the data signal D is applied to the data input buffer 210. Preferably, the high level of the data signal D is set below the first power supply voltage VDDL. In addition, since the data input buffer 210 functions as an inverter, the output signal becomes an inverted data signal / D. The inverted data signal / D is input to the data switching unit 220.

The data switching unit 220 is composed of two NMOS transistors N1 and N2. That is, the data signal D is input to the first transistor N1 and performs an on / off operation under the control of the clock pulse CKP received through the gate terminal. One end of the first transistor N1 is connected to an input terminal of the data storage unit 230. The inverted data signal / D is input to the second transistor N2 and performs an on / off operation under the control of the clock pulse CKP received through the gate terminal. One end of the second transistor N2 is connected to the output terminal of the data storage unit 230.

The data storage unit 230 has a latch structure consisting of two inverters, and receives and stores a signal of the data switching unit 220. In addition, the data storage unit 230 is driven by the second power supply voltage VDDH. Accordingly, the output of the data storage unit 230 is output in a state in which the level is raised to a maximum second power supply voltage VDDH relative to the input.

The data output buffer 240 functions as an inverter for inverting an input signal. Since the data output buffer 240 is driven by the second power supply voltage VDDH, the data output buffer 240 may maintain a high output level of the data storage unit. Thus, the output of the data storage unit 240 is inverted to form the output data Q whose level is increased.

3 is a timing diagram illustrating an operation of the flip-flop circuit shown in FIG. 2 according to a preferred embodiment of the present invention.

2 and 3, the pulse generator 100 receiving the clock signal CK having a level lower than or equal to the first power supply voltage VDDL forms the clock pulse CKP and transmits it to the data latch 200. The latch unit senses and stores the data signal D applied under the control of the received clock pulse CKP, and forms the output data Q raised to a level lower than or equal to the second power voltage VDDH.

First, the operation of the pulse generator 100 is as follows.

The clock signal CK input to the clock input buffer 110 is inverted and formed as the inverted clock signal / CK. The clock delay unit 120 delays the inverted clock signal by ΔT and outputs the delayed inverted clock signal / CKP. Accordingly, the inverted clock signal / CK and the delayed inverted clock signal / CKP are input to the switching unit 130.

The switching unit 130 performs a switching operation according to the two input signals and outputs a clock pulse CKP through the clock output buffer 140. For example, in the period T1, the clock signal CK becomes high level, and the inverted clock signal / CK becomes low level. In addition, the delayed inverted clock signal / CKD has a waveform delayed by ΔT relative to the inverted clock signal / CK. Therefore, the inverted clock signal / CKD delayed for a predetermined period DELTA T in the period T1 maintains the high level.

When the inverted clock signal / CK is low level and the delayed inverted clock signal / CKD is high level, the NMOS transistor Q2 of the switching unit 130 is turned on and the switching unit 130 outputs a low level. The output of the switching unit 130 is inverted in the clock output buffer 140 to form a high level clock pulse CKP. The high level of the clock pulse CKP is set below the first power supply voltage VDDL. This is due to the pulse generator 100 being driven by the first power supply voltage VDDL.

In addition, after the delay time DELTA T has elapsed in the period T1, the delayed inverted clock signal / CKD is also changed to the low level. Therefore, the two signals / CK and / CKD applied to the switching unit 130 are at a low level. At this time, the PMOS transistor Q1 of the switching unit 130 is turned on and the NMOS transistor Q2 is turned off. Accordingly, the switching unit 130 outputs a high level signal and forms a low level clock pulse CKP via the clock output buffer 140. The high level signal output from the switching unit 130 is equal to or less than the first power voltage VDDL.

Subsequently, section T2 is started subsequent to section T1.

In the period T2, the clock signal CK is changed to the low level, and the inverted clock signal / CK is changed to the high level. In addition, the inverted clock signal / CKD delayed by the operation of the clock delay unit 120 has a delay delayed by ΔT. Therefore, after the period T2 is started, the inverted clock signal / CKD delayed for the delay time DELTA T maintains a low level. As a result, the clock signal / CK inverted during DELTA T during the period T2 maintains the high level, and the delayed inverted clock signal / CKD maintains the low level.

The PMOS transistor Q1 of the switching unit 130 is turned on by the high level inverted clock signal / CK and the low level delayed inversion clock signal / CKD applied to the switching unit 130, and the switching unit 130 is at a high level. Maintain the state of. This maintains the low level clock pulse CKP via the clock output buffer 140.

Subsequently, after the delay time DELTA T has elapsed in the period T2, the delayed inverted clock signal / CKD is changed to a high level. Therefore, the two signals applied to the switching unit 130 are set to a high level. When the two signals are high level, the transistors Q1 and Q2 of the switching unit 130 are turned off. Thus, the clock pulse CKP maintains its low level, which is the previous state.

That is, the pulse generator 100 according to the present embodiment forms the clock pulse CKP of high level for the time delayed by the clock delay unit 120 by the inverted clock signal / CKD. The high level of the clock pulse CKP is limited by the first power supply voltage VDDL. Therefore, the level of the clock pulse CKP does not exceed the first power supply voltage VDDL.

The data latch 200 according to the present exemplary embodiment senses the data signal D in the rising period of the applied clock pulse CKP and stores it. Therefore, the update of the output data Q occurs in the rising section of the clock pulse CKP. In addition, the level of the data signal D restricted by the first power supply voltage VDDL is limited by the second power supply voltage VDDH through the data latch 200. Therefore, the flip-flop circuit of this embodiment has a structure in which the level is increased from the first power supply voltage VDDL to the second power supply voltage VDDH.

First, when the low level data signal D is input to the data input buffer 210 and the clock pulse CKP rises to the high level for the delay time DELTA T, the first transistor N1 of the data switching unit 220 is Is turned on. The second transistor N2 is also turned on by the high level clock pulse. The high-level inverted data signal / D by the turned-on second transistor N2 is transferred to the other end of the data storage unit 230 and stored.

Accordingly, the first transistor N1 of the data switching unit 210 outputs a low level data signal D, which is input to the data storage unit 230. The data input buffer 210 and the data switching unit 220 are limited by the level of the first power supply voltage VDDL, and the data storage unit 230 is limited in level by the second power supply voltage VDDH. Thus, a level shifting operation in which the level of the signal stored in the data storage 230 rises.

The data storage unit 230 stores the data signal D and at the same time inverts the data signal D to the data output buffer 240. As a result, the data latch 200 senses the low level data signal D in the rising section of the clock pulse CKP, stores it in the data storage 230, and finally updates the output data Q.

Subsequently, after the delay time DELTA T has elapsed in the period T1, the clock pulse CKP is changed to the low level. Therefore, the two transistors N1 and N2 of the data switching unit 220 are turned off. This means that the data previously stored in the data storage unit 220 is maintained as the output data Q. Thus, regardless of the level of the data signal D, the flip-flop retains the existing output data Q.

Subsequently, the clock pulse CKP maintains the low level even in the period T2. Thus, regardless of the level of the data signal D, the flip-flop maintains the state of the existing output data Q.

Even if the data signal D changes to high level, the update of the output data Q does not occur when the clock pulse CKP is not at the rising section or the high level. In addition, when the clock pulse CKP transitions to the high level in the clock period after the period T2, and the data signal D changes to the high level, the update of the data signal is generated in synchronization with the clock pulse CKP. Therefore, the output data Q is updated in synchronization with the transition of the high level of the clock pulse CKP.

In this embodiment, a pulse generator and a data latch are provided separately. Thus, a plurality of data latches may be arranged in one pulse generator. Through this, the area occupied by the flip-flop can be minimized, and the power consumed by the flip-flop can be reduced. That is, when a plurality of data latches have a structure in which one pulse generator is shared, power consumption may be reduced, and the area occupied on the layout of the semiconductor chip may be reduced.

1 is a circuit diagram illustrating a level converting flip-flop according to the prior art.

2 is a circuit diagram illustrating a level shift flip-flop according to a preferred embodiment of the present invention.

3 is a timing diagram illustrating an operation of the flip-flop circuit shown in FIG. 2 according to a preferred embodiment of the present invention.

Claims (6)

A clock generator driven by a first power supply voltage and generating a clock pulse by an on / off operation using an inverted clock signal and a delayed inverted clock signal; And And a data latch using an on / off operation according to the clock pulse and storing and updating a data signal below a second power supply voltage level higher than the first power supply voltage to generate output data. The method of claim 1, wherein the clock generator, A clock input buffer for receiving a clock signal and inverting the clock signal to generate the inverted clock signal; A clock delay unit configured to delay the inverted clock signal to generate the delayed inverted clock signal; The switching unit configured to receive the inverted clock signal and the delayed inverted clock signal and form an inverted clock pulse through switching; And And an output buffer which inverts the inverted clock pulses to form the clock pulses. The method of claim 2, wherein the clock delay unit, A PMOS transistor coupled to the first power supply voltage; And An NMOS transistor connected to the PMOS transistor and the inverted clock signal, And a gate terminal of the PMOS transistor and the NMOS transistor are commonly connected to receive a delayed inverted clock which is an output of the clock delay unit. The method of claim 1, wherein the data latch, A data input buffer for inverting the data signal; A data switching unit configured to transfer the data signal or the inverted data signal by performing an on / off operation according to the clock pulse; A data storage unit having a latch structure to store a signal of the data switching unit, and driven by the first power voltage to increase a level of the data signal or the inverted data signal; And And a data output buffer configured to invert the signal stored in the data storage unit to form the output data and to be driven by the first power voltage. The method of claim 4, wherein the data switching unit, A first transistor receiving the data signal and performing an on / off operation according to the clock pulse; And A second transistor configured to receive the inverted data signal and perform an on / off operation according to the clock pulse; And the output of the first transistor is connected to one end of the data storage, and the output of the second transistor is connected to the other end of the data storage. 6. The level shift flip-flop of claim 5 wherein the first and second transistors are NMOS transistors.

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