KR20100055093A - Reticle manufacturing method for semiconductor device - Google Patents

Abstract

PURPOSE: A method for manufacturing a reticle for a semiconductor is provided to improve pattern fidelity by reducing an off-grid phenomenon by sizing in a pattern generation process. CONSTITUTION: A layer for manufacturing a reticle is formed by a Boolean operation process. A first pattern array box(20) with a square shape is defined on the layer. A second pattern array box(30) is defined by sizing the first pattern array box. The surface of a layer pattern in contact with one side of the first pattern array box is sized to the adjacent surface to the second pattern array box. The sizing completed layer data is converted into the file type to be inputted to an electron beam scan device.

Description

Reticle manufacturing method for semiconductor device

The present invention relates to a method for manufacturing a reticle for semiconductor manufacturing, and more particularly, to a method for manufacturing a reticle for semiconductor manufacturing which can reduce a decrease in uniformity of a pattern due to off-grid.

In general, in order to form a desired pattern in a photolithography process for manufacturing a semiconductor, a reticle is required together with an exposure apparatus and a photoresist film.

The reticle is a disc used to project a repetitive semiconductor circuit pattern onto a silicon wafer, and is made of a quartz plate having a chromium pattern of 4 or 5 times the size of the reticle.

The pattern on this reticle should have the same critical dimension (hereinafter referred to as 'CD') for the same layout pattern. In other words, fidelity of the pattern becomes an important factor in reticle production. Recently, as the line width of semiconductor devices decreases, the demand for fidelity increases.

Meanwhile, a process of manufacturing a reticle for contact photolithography from a semiconductor design circuit diagram (hereinafter referred to as 'DB') will be briefly described as follows. For example, a plurality of contact patterns patterned in a square shape having a length of 0.4 μm on one side of a DB are manufactured to have a reticle larger or smaller than the size on the DB according to a process bias of a semiconductor manufacturing process.

The process bias includes a mask bias, a photo bias and an etch bias. The mask bias refers to the difference between the pattern on the reticle and the pattern on the DB (△ Mask = DB), the photo bias refers to the difference between the pattern on the photosensitive film of the wafer and the pattern on the reticle (△ Photo = Photo-Mask), The etch bias refers to the difference between the pattern on the object to be etched on the wafer and the pattern on the photoresist layer (ΔEtch = Etch-Photo).

For example, if the etch bias is -0.1 μm and the photo bias is 0.05 μm during the contact process bias, the patterned reticle is 0.05 μm larger than the size of the actual DB in the mask (or reticle) fabrication step. The size of the contact on the etchant and the DB is the same.

That is, pattern generation, which converts DB patterns (e.g. gds file format) into the format (e.g. mebes file format) used for reticle production through Boolean operation. In the course of operation, the mask bias is artificially formed through sizing.

On the other hand, when the minimum grid on the DB, which is a design drawing, becomes smaller and smaller, and the address size of the E-beam writer for manufacturing a semiconductor reticle does not match an integer multiple of the grid on the DB, Off grid phenomenon occurs, and the pattern fidelity is lowered due to the mismatch of grid spacing rather than the density of patterns.

For example, although a pattern is drawn on a DB with a grid scale of 1 nm, the electron beam scanning apparatus used for manufacturing a reticle is recognized as a writing address unit that is an integer multiple of 4 nm. In this process, even if the pattern of the same line width is not multiplied according to the position, an off grid with a value of about the middle of the address size is created.

Therefore, even contact holes of the same size have different shapes and sizes depending on the position. That is, since on-grid contact holes and off-grid contact holes exist in the semiconductor reticle, a problem of inferior pattern fidelity occurs.

Accordingly, an object of the present invention is to provide a method for manufacturing a reticle for semiconductor manufacturing which can reduce the off grid phenomenon.

Reticle manufacturing method for a semiconductor manufacturing of the present invention for realizing the above object comprises a first step of forming a layer for reticle manufacturing by a Boolean operation from a database including a semiconductor design circuit diagram; A second step of defining a rectangular-shaped primary pattern array box including a plurality of patterns existing in the layer on the layer; A third step of sizing the primary pattern array box to define a secondary pattern array box; Sizing a surface of a layer pattern in contact with one surface of the primary pattern array box to an adjacent surface of the secondary pattern array box; And converting the layer data on which the sizing operation is completed into a file format that can be input to the electron beam scanning apparatus.

In addition, the primary pattern array box of the second step may be defined such that one surface of a pattern located at an edge of the patterns included in the primary pattern array box coincides with the surface of the primary pattern array box.

In addition, the second pattern array box of the third step is characterized by setting the sizing size in the range of 30 to 50% of the minimum address size of the electron beam scanning apparatus.

According to the method of manufacturing a reticle for manufacturing a semiconductor according to the present invention, there is an effect of improving pattern fidelity by reducing off-grid phenomenon by sizing in a pattern generation process.

Hereinafter, with reference to the accompanying drawings will be described in detail the configuration and operation of the preferred embodiment of the present invention.

1 is a layout diagram in which a primary pattern array box is defined according to an embodiment of the present invention, FIG. 2 is a layout diagram in which a secondary pattern array box is defined according to an embodiment of the present invention, and FIG. A layout diagram showing a result of sizing a layer pattern according to an embodiment of the present invention.

Reticle manufacturing method for manufacturing a semiconductor according to an embodiment of the present invention comprises a first step to a fifth step.

The first step is to form a layer for reticle fabrication by a Boolean operation from a database including a semiconductor design circuit diagram.

Referring to FIG. 1, the second step is to define a rectangular-shaped primary pattern array box 20 including a plurality of patterns 10 present in the layer on the layer.

As shown in FIG. 1, the primary pattern array box 20 may include one surface of a pattern located at an edge of the patterns 10 included in the primary pattern array box 20 and the primary pattern. It is desirable to define the sides of the array box to coincide.

Referring to FIG. 2, the third step is to define the secondary pattern array box 30 by sizing the primary pattern array box 20. Here, the secondary pattern array box 30 preferably sets a sizing size in a range of 30 to 50% of the minimum address size of the electron beam scanning apparatus.

Referring to FIG. 3, the fourth step includes sizing the surface of the layer pattern 10 in contact with one surface of the primary pattern array box 20 to an adjacent surface of the secondary pattern array box 30. to be.

The fifth step is a step of converting the layer data on which the sizing operation is completed into a file format that can be input to the electron beam scanning apparatus.

Example

1 to 3, a method of manufacturing a contact hole mask or a reticle by a method for manufacturing a semiconductor reticle according to an embodiment of the present invention will be described below.

First, the description will be made based on the assumption that the address size for determining the resolution of the electron beam scanning apparatus is 16 nm. Here, 16 nm means that data is processed in area units that are 4 times larger when 4 nm is the size having the minimum resolution.

So instead of speeding up the reticle, we choose a trade-off that reduces accuracy.

If the address size is 16 nm, it means that the edge of the contact hole may be changed within the range of 8 nm, which is half thereof. For example, if the size of the contact hole is designed to be 180 nm, it means that it may be larger or smaller than 180 nm at the point where the off grid is generated depending on the position.

In order to reduce the deterioration of the fidelity of the pattern according to the off-grid, in the reticle manufacturing method for semiconductor manufacturing according to an embodiment of the present invention, as shown in Figure 1 attached to a Boolean calculation from a database containing a semiconductor design circuit diagram The primary pattern array box 20 is defined primarily as a temporary pattern array on the layer formed by the work.

In general, a contact layer is formed by one layer on a semiconductor design circuit diagram, but in the case of an active layer, an active layer is formed by combining an nMOS active region and a pMOS active region on a semiconductor design circuit diagram (OR operation). It is.

In addition, the reference for defining the primary pattern array box 20 is based on the address size of the electron beam scanning apparatus. That is, when the address size is 16 nm, the size of the primary pattern array box 20 is set in consideration of the minimum distance that an off grid of less than 8 nm occurs in the X or Y direction from the layer pattern.

Then, the outlines are sized to a size of 8 nm for all the contact holes which are individual layer patterns, and the secondary pattern array box 30 which is the outermost template box including the sized contact holes is set.

Thereafter, the contact holes existing at the four corners of the secondary pattern array box are selectively rearranged in the on-grid state to expand the size of the contact holes.

Lastly, the address size is changed to an on-grid state so that the second pattern array box 30 can be matched to the other contact holes except for the contact holes existing at the corners of the secondary pattern array box 30.

After the sizing is completed, the layer data is converted into a file format that can be input to the electron beam scanning apparatus, and the pattern data is finally patterned by the electron beam scanning apparatus based on the converted data, thereby eliminating pattern non-uniformity caused by the off-grid. .

It is apparent to those skilled in the art that the present invention is not limited to the above-described embodiments and can be practiced in various ways within the scope not departing from the technical gist of the present invention. It is.

1 is a layout diagram in which a primary pattern array box is defined according to an embodiment of the present invention;

2 is a layout diagram in which a secondary pattern array box is defined according to an embodiment of the present invention;

3 is a layout showing a result of sizing the layer pattern according to an embodiment of the present invention.

* Description of the symbols for the main parts of the drawings *

10: pattern, layer pattern 20: primary pattern array box

30: secondary pattern array box

Claims (3)

A first step of forming a layer for reticle manufacturing by a Boolean operation from a database including a semiconductor design circuit diagram; A second step of defining a rectangular-shaped primary pattern array box including a plurality of patterns existing in the layer on the layer; A third step of sizing the primary pattern array box to define a secondary pattern array box; Sizing a surface of a layer pattern in contact with one surface of the primary pattern array box to an adjacent surface of the secondary pattern array box; And a fifth step of converting the layer data of which the sizing operation is completed into a file format that can be input to an electron beam scanning apparatus. The method of claim 1, wherein the first pattern array box of the second step defines that one surface of a pattern located at an edge of the patterns included in the first pattern array box coincides with a surface of the primary pattern array box. A method for manufacturing a reticle for semiconductor manufacturing, characterized by the above-mentioned. The method of claim 1, wherein the second pattern array box of the third step sets the sizing size in a range of 30 to 50% of the minimum address size of the electron beam scanning apparatus.

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