KR20100051925A - Vertical light emitting diode and manufacturing method of the same - Google Patents

Abstract

PURPOSE: A vertical light emitting diode and a method for manufacturing the same are provided to prevent the lattice defect of a light emitting unit by forming passivation layers on the both end of a substrate before the light emitting unit is formed. CONSTITUTION: A p-type electrode(250) is formed on a silicon substrate(300). Passivation layers(220) are formed on the both end of the p-type electrode. A light emitting unit(240) is formed by successively depositing an n-type semiconductor layer, an active layer and a p-type semiconductor layer on the p-type electrode. An n-type electrode(260) is formed on a part of the n-type semiconductor layer.

Description

Vertical Light Emitting Diode and manufacturing method of the same

The present invention relates to a light emitting diode, and more particularly, by forming a passivation layer at both ends of a substrate before forming the light emitting portion, it is possible to prevent the light emitting portion from being damaged by an etching process and to improve the light emitting efficiency and production yield of the chip. The present invention relates to a vertical light emitting diode and a method of manufacturing the same.

A light emitting diode (LED) is a semiconductor light emitting device that converts electrical energy into light energy, and emits light by flowing current through a compound semiconductor terminal and combining light with electrons and holes in a p-n junction or in an active layer.

The light emitting diode can realize various colors by adjusting the composition ratio of the compound semiconductor. The light conversion efficiency is low, the power consumption is low, and the lifespan reaches 10,000 to 50,000 hours, and the response time when the light is turned on and off is fast. In addition, it can be integrated in various forms as a point light source, and can be made in a small size, so that it is possible to design elaborately and be environmentally friendly. Currently, light emitting diodes are expanding their application range to large outdoor billboards and backlights of liquid crystal displays.

The light emitting diodes are mainly made of III-V compound semiconductors. Since gallium nitride compound semiconductor (GaN) has high thermal stability and wide band gap, it has attracted much attention in the development of high power electronic component devices including LEDs.

1 shows a general structure of a conventional vertical light emitting device.

Referring to FIG. 1, a conventional vertical light emitting device includes a p-type electrode 60, a p-type semiconductor layer 20, an active layer 30, and an n-type semiconductor layer 40 on a metal or silicon support layer 10. ) Are sequentially stacked, and the n-type electrode 70 is in electrical contact with a portion of the surface of the n-type semiconductor layer 40. In addition, a passivation layer 50 made of an insulating material is formed on the sidewall of the light emitting device to prevent leakage of current through the sidewall.

When a voltage is applied between the p-type electrode 60 and the n-type electrode 70, electrons are injected from the n-type electrode 70 to the n-type semiconductor layer 40, and the p-type semiconductor from the p-type electrode 60. Holes are injected into layer 20. Electrons and holes meet and recombine in the active layer 30 to generate light, and the generated light passes through the n-type semiconductor layer 40 and is emitted to the outside through its surface.

In a conventional process, an undoped gallium nitride (GaN) layer is epitaxially grown on a sapphire substrate using a method such as LPE, MBE, MOVPE, and the like to sequentially n-type semiconductor layer 40, active layer 30 and After stacking the p-type semiconductor layer 20, a trench is formed by dry etching or wet etching the grown layers using a photolithography process.

Due to such an etching process, each layer of the etched cutting surface causes serious lattice damage, and is subjected to several photolithography and etching processes, resulting in a high process cost and a reduction in production yield. In addition, in order to solve this problem, a heat treatment process may be performed during the process, but not all of the lattice damages can be recovered by this method.

In addition, in the conventional process, the silicon substrate is bonded after undergoing various processes. At this time, each layer grown on the sapphire substrate forms a structure having a step of several micrometers in thickness. At the level, there were problems in that portions where bonding was not made well. As a result, the chip yield in the wafer is remarkably degraded after the laser lift-off (LLO) process of removing the sapphire substrate with a laser. In addition, the process yield between wafer-wafer (wafer to wafer) is also very irregular, there is a disadvantage that the production is not good.

The present invention devised to solve the problems of the prior art as described above to form a passivation layer on both ends of the substrate before forming the light emitting portion to prevent the lattice defects of the light emitting portion, to increase the external quantum efficiency to obtain a high luminous efficiency The purpose of the present invention is to provide a vertical structure light emitting diode and a method of manufacturing the same.

In addition, the present invention provides a vertical structure light emitting diode and a method of manufacturing the same, which can improve the chip yield of the light emitting diode by a metal film is formed on the entire surface of the light emitting portion so that bonding at the wafer level can occur more smoothly during chip bonding. Has a different purpose.

The object of the present invention is a silicon substrate; A p-type electrode formed on the silicon substrate; A passivation layer formed at both ends of the upper portion of the p-type electrode; A light emitting part formed by sequentially depositing an n-type semiconductor layer, an active layer, and a p-type semiconductor layer on a p-type electrode in a space between the passivation layers; And an n-type electrode formed on a portion of the n-type semiconductor layer.

In addition, the passivation layer of the present invention is preferably made of any one insulating material selected from silicon oxide (SiO _x ), silicon nitride (SiN _x ), titanium dioxide (TiO ₂ ) and tantalum oxide film (Ta _x O _y ). Do.

In addition, the passivation layer of the present invention preferably has a thickness of 4 to 20㎛, 20 to 500㎛ width.

In addition, the p-type electrode of the present invention is formed by depositing any one or more metal materials selected from nickel, platinum, silver, and gold in a plurality of layers, and preferably comprises an ohmic contact layer and a reflective film.

In addition, the light emitting part of the present invention is preferably formed by the organometallic vapor deposition method, molecular beam growth method or hydride vapor deposition method.

In addition, the silicon substrate of the present invention is preferably made of a high doped conductive substrate.

In addition, the n-type semiconductor layer of the present invention is preferably formed with a concave-convex pattern on the surface.

In addition, another object of the present invention is a first step of depositing a passivation layer on the sapphire substrate; A second step of patterning the passivation layer by photolithography to form only at both ends of the sapphire substrate; Forming a light emitting part by sequentially depositing an undoped n-type semiconductor layer, an n-type semiconductor layer, an active layer, and a p-type semiconductor layer in a space between the passivation layers; A fourth step of forming a p-type electrode by depositing a plurality of metal materials on the p-type semiconductor layer; Bonding a silicon substrate to the p-type electrode and removing the sapphire substrate using a laser lift-off process; Removing the undoped n-type semiconductor layer by removing the sapphire substrate; And a seventh step of forming an n-type electrode on the n-type semiconductor layer of the light emitting unit.

In addition, after the third step of the present invention, it is preferable to further include the step of adjusting the step by wet or dry etching the extra passivation layer in accordance with the height of the light emitting portion.

In addition, the p-type electrode of the fourth step of the present invention, after depositing nickel and gold in sequence, heat treatment at a temperature of 400 to 900 ℃ to form an ohmic contact layer; Depositing silver on the ohmic contact layer to a thickness of 1000 to 5000 kV to form a reflective film; Sequentially depositing nickel and platinum on the reflective film; And depositing nickel and gold sequentially on the platinum.

In addition, the nickel, gold, platinum of the present invention is preferably deposited to a thickness of less than 10nm.

In addition, the metal material of the present invention is preferably deposited by any one selected from the e-beam deposition, thermal deposition, electroplating deposition and electroless plating deposition.

In addition, the silicon substrate of the present invention comprises the steps of cleaning the silicon substrate; Depositing nickel on the silicon substrate; And depositing a gold / tin alloy on the nickel.

In addition, the sixth step of the present invention preferably uses an etching process using plasma.

In addition, the sixth step of the present invention preferably comprises the step of forming an uneven pattern on the surface of the n-type semiconductor layer by the etching process using the plasma.

Therefore, the vertical light emitting diode and the manufacturing method of the present invention can form a passivation layer on both ends of the substrate before forming the light emitting portion, thereby preventing lattice defects of the light emitting portion, and increasing the external quantum efficiency to increase the light emitting efficiency of the chip. That has a significant and beneficial effect.

In addition, the vertical structure light emitting diode of the present invention and a manufacturing method thereof have a wide metal film formed on the entire surface of the light emitting part so that bonding at the wafer level can be more smoothly performed during chip bonding, thereby improving chip yield of the light emitting diode. And has an advantageous effect.

In addition, the vertical structure light emitting diode of the present invention and its manufacturing method can reduce the number of photoresist film used in the manufacturing process can reduce the manufacturing cost, and a remarkable and advantageous effect that can increase the production yield of the chip by a simple manufacturing process There is.

The terms or words used in this specification and claims are not to be construed as being limited to their ordinary or dictionary meanings, and the inventors may appropriately define the concept of terms in order to best describe their invention. It should be interpreted as meaning and concept corresponding to the technical idea of the present invention based on the principle that the present invention.

Therefore, the embodiments described in the specification and the drawings shown in the drawings are only the most preferred embodiment of the present invention and do not represent all of the technical idea of the present invention, various modifications that can be replaced at the time of the present application It should be understood that there may be equivalents and variations.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

The vertical light emitting diode according to the present invention includes a silicon substrate 300, a passivation layer 220, a light emitting unit 240, a p-type electrode 250 and an n-type electrode 260.

The silicon substrate 300 uses a high-doped conductive substrate, and a gold / tin alloy containing less than 30% of nickel (Ni) and tin (Sn) having a thickness of 5 to 10 nm is deposited thereon.

In the exemplary embodiment of the present invention, the silicon substrate 300 is used, but the present invention is not limited thereto and other hetero substrates such as GaAs, GaP, AlGaINP, Ge, SiSe, GaN, AlInGaN, InGaN may be used.

The passivation layer 220 is made of an insulating material selected from one of silicon oxide (SiO _x ), silicon nitride (SiN _x ), titanium dioxide (TiO ₂ ), and tantalum oxide film (Ta _x O _y ), and is provided at both ends of the silicon substrate. It is formed in to protect the light emitting portion. The thickness h of the passivation layer 220 is preferably 4 to 20 μm, and the width d is 20 to 500 μm.

In order to smoothly drive the LED, the thickness of the light emitting unit 240 should be 4 μm or more. In the present invention, since the thickness of the light emitting part 240 is determined according to the thickness of the passivation layer 220, when the thickness of the passivation layer is thin, the light emitting part spreads along the passivation layer when the light emitting part 240 is formed. Therefore, in the present invention, the passivation layer 220 is formed to have a thickness of 4 μm or more.

In the light emitting unit 240, an n-type semiconductor layer 242, an active layer 243, and a p-type semiconductor layer 244 are sequentially deposited in a space between both passivation layers 220. It is preferable to make.

The n-type semiconductor layer 242 preferably uses an n-GaN compound semiconductor as a GaN-based nitride compound semiconductor. In addition, the n-type semiconductor layer 242 may have a concave-convex pattern formed on the surface, thereby reflecting the light generated from the active layer 243 at the surface concave-convex patterned interface.

As the p-type semiconductor layer 244, a p-GaN compound semiconductor doped with a p-type conductive impurity is preferably used as the GaN-based nitride compound semiconductor.

The active layer 243 is a material layer in which light is generated by recombination of carriers such as electron-hole pair recombination when an electric field is applied to the light emitting diode device, and is formed of a quantum well (QW) structure of InGaN / GaN. . In addition, materials such as AlGaN and AlInGaN may also be used as the active layer. In addition, the active layer may have a plurality of quantum well structures formed in order to improve luminance, thereby forming a multi quantum well (MQW) structure.

The p-type electrode 250 is formed by depositing a plurality of layers of metal materials such as nickel (Ni), platinum (Pt), silver (Ag), and gold (Au). The p-type electrode 250 includes an ohmic contact layer 253 and a reflective film 254, and nickel (Ni) formed on the reflective film 254 to prevent diffusion of the silicon substrate and tin (Sn). , A platinum (Pt) layer, and a gold (Au) layer deposited on the upper portion with a thickness of about 1 μm.

The ohmic contact layer 253 may be formed by sequentially depositing nickel (Ni) and gold (Au). In addition, it may be formed of any suitable material such as ruthenium / gold (Ru / Au), nickel / gold (Ni / Au), or indium-tin-oxide (ITO). At this time, nickel and gold is preferably deposited to a thickness of less than 10nm. In addition, the ohmic contact layer 253 is heat-treated at a temperature of about 400 to 900 ℃ to improve the ohmic contact characteristics.

The reflective film 254 is formed by depositing silver (Ag) on the ohmic contact layer 253 to a thickness of 1000 to 5000 GPa. The reflective film 254 reflects the light emitted from the light emitter 240 so that the light can be effectively emitted. In addition to silver, the reflective film 254 may use a material having high reflectivity such as aluminum (Al).

The n-type electrode 260 is formed in a portion of the n-type semiconductor layer 242, and a metal material such as Ti / Al is used as the n-type electrode.

2 to 17 are cross-sectional views illustrating a method of manufacturing a vertical light emitting diode device according to an embodiment of the present invention.

First, referring to FIG. 2, the passivation layer 220 is formed by depositing silicon oxide (SiOx) or silicon nitride (SiNx) on the sapphire substrate 210. In this case, when the passivation layer 220 is thin, the light emitting part is spread along the passivation layer when forming the light emitting part 240. Therefore, the passivation layer 220 may be formed to have a thickness of 4 μm or more.

3, the photoresist layer 230 is formed such that a pattern remains only at left and right ends of the passivation layer 220, and as shown in FIG. 4, the passivation layer 220 is photographed using the patterned photoresist layer 230 as a mask. The lithography process and the etching process are performed to pattern only the remaining left and right ends of the sapphire substrate 210.

Then, as shown in FIGS. 5 to 8, the light emitter 240 is formed in the space between the patterned passivation layer 220. First, after the undoped n-type semiconductor layer 241 is grown, the n-type semiconductor layer 242, the active layer 243, and the p-type semiconductor layer 244 are sequentially epitaxially grown.

At this time, methods such as organometallic vapor deposition (MOCVD), molecular beam growth (MBE), hydride vapor deposition (HVPE) and the like can be used.

The undoped n-type semiconductor layer 241 is made of a GaN-based nitride compound, and may be formed to a thickness of about 2 to 3 μm. In addition, the n-type semiconductor layer 242 is made of an n-GaN compound semiconductor, may be formed to a thickness of about 2 to 3㎛, the p-type semiconductor layer 244 is made of a p-GaN compound semiconductor, approximately 0.1 It may be formed to a thickness of about 0.3㎛. In addition, the active layer 243 may be formed to a thickness of about 0.1 to 0.2㎛.

As such, if the passivation layer 220 is formed first, and then the light emitting unit 240 is formed in the space therebetween, the side surface of the light emitting unit 240 may be prevented from being damaged. When the metal material is formed, the metal material is generally formed to be wide, so that the bonding may be performed well when bonding with the silicon substrate.

Then, as shown in FIG. 9, the step of etching the extra passivation layer 220 by wet or dry etching to match the height of the light emitting unit 240 may be further included.

Next, as shown in FIG. 10, a metal material is sequentially deposited on the p-type semiconductor layer 244 to form the p-type electrode 250. First, nickel (Ni, 251) is deposited to a thickness of 10 nm or less for ohmic contact, and gold (Au, 252) is deposited to a thickness of 10 nm or less to form an ohmic contact layer 253. Then, heat treatment is performed at a temperature of 400 to 900 ° C, preferably 400 to 600 ° C to improve ohmic contact.

If the thickness of nickel (Ni, 251) and gold (Au, 252) exceeds 10 nm, the light generated from the light emitting unit is not reflected, and is absorbed by these layers, and thus the thickness of 10 nm or less should be formed.

Next, as illustrated in FIG. 11, silver (Ag) is deposited to a thickness of 1000 to 5000 GPa to form a reflective film 254 layer. Thereafter, nickel (Ni, 255) and platinum (Pt, 256) are sequentially deposited on the reflective layer 254 to a thickness of 10 nm or less, in order to prevent diffusion of the silicon substrate and tin (Sn) to be bonded later. to be. Finally, nickel (Ni, 257) is deposited on platinum (Pt, 256), and gold (Au, 258) is deposited to a thickness of about 1 μm, thereby completing the p-type electrode 250. Here, nickel (Ni, 257) serves as an adhesive to deposit gold (Au, 258) well on the platinum (Pt, 256) layer.

Each metal material constituting the p-type electrode 250 is preferably deposited using an electro-beam deposition or thermal deposition, or electrolytic plating or electroless plating. In addition, processes such as sputtering, chemical vapor deposition, laser deposition, and hydride vapor deposition (HVPE), which are conventional metal layer growth processes, may be used.

Next, as shown in FIG. 12, the silicon substrate 300 is bonded to the upper portion of the p-type electrode 250 by applying heat and pressure.

Since the silicon substrate 300 serves as an electrode, it is preferable to use a high doped conductive substrate.

In addition, the silicon substrate 300 is washed with HF solution to remove the active oxygen layer on the surface, and deposited nickel (Ni, 310) to a thickness of 5 to 10nm, gold / tin containing 30% or less of tin It is desirable to prepare the (Au / Sn) alloy 320 by deposition.

Next, as shown in FIG. 13, the sapphire substrate 210 is removed and removed from the light emitting unit 240, which is preferably separated using a laser lift-off (LLO) process. When the laser light is irradiated onto the sapphire substrate 210, local heat is generated at the interface between the sapphire substrate 210 and the light emitting part 240, and the surface of the light emitting part 240 made of gallium nitride is formed by the heat. The sapphire substrate 210 is easily separated while being decomposed and melted with nitrogen gas.

Next, as shown in FIG. 14, the undoped n-type semiconductor layer 241 is removed by removing the sapphire substrate 210. In this case, since the plasma etching method is used, the undoped n-type semiconductor layer 241 and the passivation layer 220 next to it are also etched together. In addition, a portion of the n-type semiconductor layer 242 exposed as the undoped n-type semiconductor layer 241 is etched is also etched to form a rough pattern on the surface. Such surface irregularities may improve the efficiency of ohmic contact. In addition, the light generated from the active layer can be reflected at the surface-treated patterned interface.

Next, as shown in FIG. 15, an n-type electrode 260 is formed on the n-type semiconductor layer 242 of the light emitting unit 240. As the n-type electrode 260, a metal material such as Ti / Al is used.

Finally, as shown in FIG. 16, unnecessary portions beside the light emitting diodes are diced and removed to complete the light emitting diode device of the present invention as shown in FIG.

Although the present invention has been shown and described with reference to the preferred embodiments as described above, it is not limited to the above embodiments and those skilled in the art without departing from the spirit of the present invention. Various changes and modifications will be possible.

1 is a cross-sectional view of a conventional vertical structure light emitting diode,

2 to 17 is a manufacturing process diagram of a vertical light emitting diode according to an embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

210: sapphire substrate 220: passivation layer

230: photosensitive film 240: light emitting portion

250: p-type electrode 260: n-type electrode

300: silicon substrate

Claims (16)

Silicon substrates; A p-type electrode formed on the silicon substrate; A passivation layer formed at both ends of the upper portion of the p-type electrode; A light emitting part formed by sequentially depositing an n-type semiconductor layer, an active layer, and a p-type semiconductor layer on a p-type electrode in a space between the passivation layers; And An n-type electrode formed on a portion of the n-type semiconductor layer Vertical structure light emitting diode comprising a. The method of claim 1, The passivation layer is a vertical structure light emitting diode made of any one insulating material selected from silicon oxide (SiO _x ), silicon nitride (SiN _x ), titanium dioxide (TiO ₂ ) and tantalum oxide film (Ta _x O _y ). The method of claim 1, The passivation layer has a thickness of 4 to 20㎛, the width of 20 to 500㎛ vertical structure light emitting diode. The method of claim 1, The p-type electrode is formed by depositing at least one metal material selected from nickel, platinum, silver, and gold in a plurality of layers, and comprises an ohmic contact layer and a reflective film. The method of claim 1, The light emitting unit is a vertical structure light emitting diode formed by the organic metal vapor deposition method, molecular beam growth method or hydride vapor deposition method. The method of claim 1, And the silicon substrate is a high doped conductive substrate. The method of claim 1, The n-type semiconductor layer is a vertical structure light emitting diode having a concave-convex pattern is formed on the surface. Depositing a passivation layer on the sapphire substrate; A second step of patterning the passivation layer by photolithography to form only at both ends of the sapphire substrate; Forming a light emitting part by sequentially depositing an undoped n-type semiconductor layer, an n-type semiconductor layer, an active layer, and a p-type semiconductor layer in a space between the passivation layers; A fourth step of forming a p-type electrode by depositing a plurality of metal materials on the p-type semiconductor layer; Bonding a silicon substrate to the p-type electrode and removing the sapphire substrate using a laser lift-off process; Removing the undoped n-type semiconductor layer by removing the sapphire substrate; And A seventh step of forming an n-type electrode on the n-type semiconductor layer of the light emitting part Method of manufacturing a vertical structure light emitting diode comprising a. The method of claim 8, The passivation layer has a thickness of 4 to 20㎛, a width of 20 to 500㎛ manufacturing method of a vertical structure light emitting diode. The method of claim 8, And after the third step, adjusting the level of the passivation layer by wet or dry etching the excess passivation layer according to the height of the light emitting unit. The method of claim 8, The p-type electrode of the fourth step, Depositing nickel and gold sequentially, followed by heat treatment at a temperature of 400 to 900 ° C. to form an ohmic contact layer; Depositing silver on the ohmic contact layer to a thickness of 1000 to 5000 kV to form a reflective film; Sequentially depositing nickel and platinum on the reflective film; And Sequentially depositing nickel and gold on the platinum Method of manufacturing a vertical structure light emitting diode including a. The method of claim 11, The nickel, gold, platinum is a method of manufacturing a vertical light emitting diode is deposited to a thickness of less than 10nm. The method of claim 11, The metal material is a method of manufacturing a vertical structure light emitting diode deposited by any one selected from the e-beam deposition, thermal deposition, electroplating deposition and electroless plating deposition. The method of claim 8, The silicon substrate is Cleaning the silicon substrate; Depositing nickel on the silicon substrate; And Depositing a gold / tin alloy on the nickel Method of manufacturing a vertical structure light emitting diode including a. The method of claim 8, The sixth step is a method of manufacturing a vertical structure light emitting diode using an etching process using a plasma. The method of claim 15, The sixth step is a method of manufacturing a vertical light emitting diode comprising the step of forming an uneven pattern on the surface of the n-type semiconductor layer by the etching process using the plasma.

Images