KR20100047496A - Manufactruing method of semiconductor device - Google Patents

Manufactruing method of semiconductor device Download PDF

Info

Publication number
KR20100047496A
KR20100047496A KR1020080106419A KR20080106419A KR20100047496A KR 20100047496 A KR20100047496 A KR 20100047496A KR 1020080106419 A KR1020080106419 A KR 1020080106419A KR 20080106419 A KR20080106419 A KR 20080106419A KR 20100047496 A KR20100047496 A KR 20100047496A
Authority
KR
South Korea
Prior art keywords
liner
oxide film
sti
film
nitride film
Prior art date
Application number
KR1020080106419A
Other languages
Korean (ko)
Other versions
KR101056244B1 (en
Inventor
김대영
Original Assignee
주식회사 동부하이텍
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주식회사 동부하이텍 filed Critical 주식회사 동부하이텍
Priority to KR1020080106419A priority Critical patent/KR101056244B1/en
Publication of KR20100047496A publication Critical patent/KR20100047496A/en
Application granted granted Critical
Publication of KR101056244B1 publication Critical patent/KR101056244B1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]

Abstract

PURPOSE: A method for manufacturing a semiconductor device is provided to effectively reduce stress on an STI region by preventing damage due to plasma in a gap-fill process by a HDP process. CONSTITUTION: An active region and a trench of an STI are formed by an etching process. A liner nitride film(500) is evaporated inside the trench of the STI and a second pad oxide film with an LP-CVD method. A liner high oxide film(600) is deposited on the liner nitrogen film. A gap-fill insulation material is filled on the liner high temperature oxide layer with an HDP method and is planarized with a CMP process. The STI is formed by successively etching the liner high temperature film, the liner nitride film, a second oxide film, a pad nitride film, and a first pad oxide film on the uppermost layer of the semiconductor substrate with a wet process.

Description

반도체 소자의 제조방법{Manufactruing Method of Semiconductor device}Manufacturing Method of Semiconductor Device

본 발명은 반도체 소자의 제조방법에 관한 것으로서, 더욱 상세하게는 특히 셀로우 트렌치 아이솔레이션(이하 'STI'라 한다) 영역의 소자분리막의 스트레스를 줄이기에 알맞은 반도체소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device suitable for reducing stress of a device isolation film in a shallow trench isolation (hereinafter referred to as STI) region.

주지하는 바와 같이 반도체 소자에는 트랜지스터, 커패시터, 저항 등의 단위 소자가 고밀도로 집적되는데, 이러한 소자들의 전기적으로 독립적인 특성을 위하여 소자 분리기술이 요구된다. As is well known, unit devices, such as transistors, capacitors, and resistors, are integrated at a high density in semiconductor devices, and device isolation techniques are required for the electrically independent characteristics of these devices.

일반적으로 반도체 소자의 제조 공정에 있어서 소자 분리 기술은 크게 LOCOS(LOCal Oxidation of Silicon, 이하 'LOCOS'라 한다) 공정과 STI(Shallow Trench Isolation, 이하 'STI'라 한다) 공정으로 나눌 수 있다. In general, in the semiconductor device manufacturing process, the device isolation technology may be classified into a LOCOS (LOCOS) process and a shallow trench isolation (STI) process.

상기 LOCOS 공정은 반도체 기판에 형성된 패드 산화막과 질화막을 패터닝한 후 선택적 산화 공정에 의하여 소자분리막을 형성하는 공정을 말하며, 상기 STI 공정은 반도체 기판에 일정한 깊이를 갖는 트렌치를 형성하고나서 상기 트렌치에 절연 물질을 매립시킨 후 화학적기계적연마(chemical mechanical polishing, 이하 'CMP'라 한다) 공정에 의해 매립된 부분을 제외한 절연 물질을 제거함으로써 소자 분리막을 형성하는 공정을 말한다. The LOCOS process refers to a process of forming an isolation layer by a selective oxidation process after patterning a pad oxide film and a nitride film formed on a semiconductor substrate, wherein the STI process is to insulate the trench after forming a trench having a predetermined depth in the semiconductor substrate It refers to a process of forming a device isolation film by removing an insulating material except a portion buried by a chemical mechanical polishing (hereinafter referred to as "CMP") process after embedding the material.

상기 LOCOS 공정은 장시간 고온 산화로 인하여 채널 저지 이온의 측면 확산 및 측면 산화에 의해 소자의 전기적인 특성을 저하시키는 원인으로 작용하는 버즈 빅(Bird's Beak)이 발생하여 약 0.25㎛ 이하의 공정에는 적용의 한계가 있다. The LOCOS process is applied to a process of about 0.25 μm or less due to the occurrence of Bird's Beak, which acts as a cause of lowering the electrical characteristics of the device by side diffusion and lateral oxidation of channel blocking ions due to prolonged high temperature oxidation. There is a limit.

이러한 LOCOS 공정의 문제점을 해결하기 위해 현재 0.25㎛ 이하의 미세 공정에서는 소자 분리막 형성 방법으로 STI 공정이 많이 사용되고 있다. 상기 STI 공정 적용시에는 LOCOS 공정의 단점인 버즈 빅은 발생하지 않으므로 반도체 소자의 스케일링(scaling)에 유리하고 절연 특성이 양호하다는 장점이 있다.In order to solve the problem of the LOCOS process, the STI process is widely used as a method of forming a device isolation layer at a minute process of 0.25 μm or less. When the STI process is applied, since the buzz big, which is a disadvantage of the LOCOS process, does not occur, it is advantageous in scaling of semiconductor devices and has good insulation characteristics.

최근 반도체 소자의 스피드 증가에 관한 요구가 커짐에 따라서 트랜지스터(Tr)의 모빌리티(mobility) 증가를 위한 연구가 큰 관심을 일으키고 있다. 특히 캐리어 모빌리티(Carrier mobility)가 트랜지스터의 채널(channel) 주변에 발생하는 스트레스(stress)와 밀접한 관계가 있다는 연구 결과가 발표되면서 채널(Channel)에 인접한 STI영역의 스트레스 감소(stress reduction)에 관한 연구가 크게 관심을 모으고 있다.Recently, as the demand for increasing the speed of semiconductor devices increases, research for increasing the mobility of the transistor Tr has been of great interest. In particular, as a result of research showing that carrier mobility is closely related to stress occurring around a channel of a transistor, a study on stress reduction of an STI region adjacent to a channel is presented. Is greatly attracting attention.

예를 들어, 종래에는 셀로우 트렌치 아이솔레이션(STI) 형성 후, STI의 갭을 채우기 위해 TEOS(Tetra Ethyl Ortho Silicate)를 사용하는데, 이때 일반적으로 STI 영역 주위로 압축 스트레스(compressive stress)가 형성된다.For example, conventionally, after forming trench trench isolation (STI), TEOS (Tetra Ethyl Ortho Silicate) is used to fill the gap of STI, in which compressive stress is generally formed around the STI region.

이때 발생되는 압축 스트레스(Compressive stress)는 STI와 트랜지스터(Tr)간의 거리 차에 따라서 트랜지스터의 모빌리티 뿐만 아니라, 트랜지스터의 누설 전류(leakage current)에도 악영향을 끼친다.The compressive stress generated at this time adversely affects not only the mobility of the transistor but also the leakage current of the transistor according to the distance difference between the STI and the transistor Tr.

이에, 상기와 같은 스트레스(stress)를 감소시키기 위해서 종래에는 플라즈마 질화 처리를 하는 방법을 많이 사용하고 있다. 그러나 STI영역 주변에 플라즈마 질화처리공정으로 질소를 주입하여도 그 깊이가 10 ~ 15Å정도로 매우 낮아서 후속의 고밀도 플라즈마(High Density Plasma:이하 'HDP'라 한다)방법으로 갭필(gap fill)시 발생하는 플라즈마 손상(plasma damage)에 의해서 STI의 코너부위와 바닥부위의 질소층이 쉽게 손실 될 뿐만 아니라 형성된 질화막의 두께가 낮아서 STI에서의 스트레스를 감소시키기에는 영향성이 작다는 문제점이 있다.Thus, in order to reduce the stress (stress) as described above, a conventional method of plasma-nitriding is used a lot. However, even when nitrogen is injected around the STI area by the plasma nitridation process, the depth is very low, about 10 to 15Å, which is generated during gap fill by the subsequent high density plasma (HDP) method. Plasma damage is not only easy to lose the nitrogen layer at the corners and the bottom of the STI, but also has a problem that the impact of reducing the stress in the STI due to the low thickness of the formed nitride film.

본 발명은 상기와 같은 문제점을 해결하기 위하여 안출된 것으로서, STI영역에서의 스트레스 효과를 높이기 위해 라이너 질화막(SiN)을 증착하고, HDP공정에 의한 갭필시 플라즈마에 의한 손상방지를 위해 라이너 질화막 증착공정 이후(plasma nitridation) 라이너 고온산화막(high temp. oxide: 이하 'HTO'라한다)을 증착하여 STI 내부의 라이너 질화막의 손실을 방지하는 반도체 소자의 제조방법을 제공함에 그 목적이 있다.The present invention has been made to solve the above problems, the liner nitride film (SiN) is deposited to increase the stress effect in the STI region, and the liner nitride film deposition process to prevent damage by plasma during gap fill by the HDP process It is an object of the present invention to provide a method for manufacturing a semiconductor device which prevents the loss of a liner nitride film inside an STI by depositing a plasma nitridation high temp. Oxide (hereinafter referred to as HTO).

상술한 바와 같은 목적을 구현하기 위한 본 발명의 반도체 소자의 제조방법은 반도체 기판상에 순차적으로 제1패드산화막, 패드질화막 및 제2패드산화막 증착하고 사진공정 및 반응성이온에칭공정을 이용한 식각공정을 진행하여 활성영역 및 STI의 트렌치를 형성하는 단계, 상기 제2패드산화막 및 상기 STI의 트렌치 내부에 LP-CVD 방식으로 라이너 질화막을 증착하는 단계, 상기 라이너 질화막 위에 라이너 고온산화막을 증착하는 단계, 상기 라이너 고온산화막 위에 HDP 방식으로 갭필절연물질 충진 및 CMP공정으로 평탄화 하는 단계 및 습식공정을 진행하여 반도체 기판상의 최상층에 증착된 라이너 고온산화막, 라이너질화막, 제2산화막, 패드질화막 및 제1패드산화막을 순차적으로 식각하여 STI를 형성하는 단계를 포함하는 것을 특징으로 한다.The method of manufacturing a semiconductor device of the present invention for realizing the above object is to sequentially deposit a first pad oxide film, a pad nitride film and a second pad oxide film on a semiconductor substrate, and perform an etching process using a photo process and a reactive ion etching process. Forming a trench of an active region and an STI, depositing a liner nitride film in the second pad oxide film and the trench of the STI by LP-CVD, depositing a liner high temperature oxide film on the liner nitride film, Filling the gap fill insulating material and planarizing the gap fill insulating material by the HDP method and the CMP process on the liner high temperature oxide film, and the wet process is carried out to deposit the liner high temperature oxide film, liner nitride film, second oxide film, pad nitride film and first pad oxide film deposited on the top layer of the semiconductor substrate. Sequentially etching to form an STI.

본 발명에 따른 반도체 소자의 제조방법에 의하면 라이너 질화막 및 라이너 고온산화막을 증착함으로써 HDP공정에 의한 갭필시 플라즈마에 의한 손상을 방지함으로써 STI 영역에서의 스트레스를 효과적으로 감소시키는 장점이 있다.According to the method of manufacturing the semiconductor device according to the present invention, by depositing a liner nitride film and a liner high temperature oxide film, there is an advantage of effectively reducing stress in the STI region by preventing plasma damage during gap fill by the HDP process.

이하 첨부한 도면을 참조하여 본 발명의 바람직한 실시예에 대한 구성 및 작용을 상세히 설명하면 다음과 같다. 도 1 부터 도 6은 본 발명에 따른 STI내 라이너 질화막 및 라이너 고온산화막을 증착하여 HDP공정에 의한 갭필시 플라즈마에 의한 손상을 방지함으로써 STI 영역에서의 스트레스를 효과적으로 감소시키는 반도체 소자의 제조방법을 나타내는 반도체 소자의 단면도이다. Hereinafter, the configuration and operation of the preferred embodiment of the present invention will be described in detail with reference to the accompanying drawings. 1 to 6 illustrate a method of fabricating a semiconductor device which effectively reduces stress in an STI region by depositing a liner nitride film and a liner high temperature oxide film in an STI according to the present invention to prevent damage by plasma during gap fill by an HDP process. It is sectional drawing of a semiconductor element.

먼저 도 1에서는 반도체 기판(100)상에 제1패드산화막(200), 패드질화막(300) 및 제2패드산화막(400)을 순차적으로 증착한다. 이후 활성영역과 STI영역을 정의하기 위하여 사진공정에 의하여 포토레지스트를 패터닝한 다음 이온성반응에칭(RIE)공정을 진행하여 트렌치를 형성한다. First, in FIG. 1, the first pad oxide film 200, the pad nitride film 300, and the second pad oxide film 400 are sequentially deposited on the semiconductor substrate 100. After that, the photoresist is patterned by a photolithography process to define the active region and the STI region, followed by an ionic reaction etching (RIE) process to form a trench.

이후 상기 포토레지스트를 제거하여 도 1에 도시한 것처럼 반도체 소자 단면을 형성하거나 다른 실시예로서는 상기 반도체 기판(100)상에 순차적으로 적층된 제1패드산화막(200), 패드질화막(300) 및 제2패드산화막(400)을 하드마스크로 사용하여 트렌치를 형성할 수도 있다.Thereafter, the photoresist is removed to form a cross-section of the semiconductor device as shown in FIG. 1, or in another embodiment, the first pad oxide film 200, the pad nitride film 300, and the second film sequentially stacked on the semiconductor substrate 100. A trench may be formed using the pad oxide film 400 as a hard mask.

다음으로 도 2에서는 저압화학기상증착(LP-CVD)방법으로 상기 STI의 내부에 라이너 질화막(500)을 형성한다. 라이너 질화막(500)은 트렌치에 매립되는 산화물(700)로 인한 압축 응력(Compressive Stress)을 보상하기 위한 것이다. 즉 트렌치 매립 산화물(700)로 인해 반도체 기판(100)에 가해지는 압축 응력(Compressive Stress)이 라이너 질화막(500)의 인장응력(Tensile Stress)에 의해 상쇄되기 때문에 STI에 의한 소자의 전기적 특성이 저하되는 것을 효과적으로 방지할 수있다. 상기 라이너 질화막(500)의 두께는 LP-CVD방법을 이용하여 40~120Å로 증착함이 바람직하다.Next, in FIG. 2, a liner nitride film 500 is formed inside the STI by low pressure chemical vapor deposition (LP-CVD). The liner nitride film 500 is intended to compensate for the compressive stress due to the oxide 700 embedded in the trench. That is, since the compressive stress applied to the semiconductor substrate 100 due to the trench buried oxide 700 is canceled by the tensile stress of the liner nitride film 500, the electrical characteristics of the device due to the STI are deteriorated. Can effectively prevent being. The thickness of the liner nitride film 500 is preferably deposited at 40-120 kPa using the LP-CVD method.

다음으로 도 3에서는 HDP공정에 의한 트렌치 매립 산화물(700)로 갭필시 플라즈마에 의한 라이너 질화막(500)의 손상방지를 위해 라이너 질화막(500) 증착공정 이후 라이너 고온산화막(600)을 증착한다. 상기 라이너 고온산화막(600)의 두께는 40~120Å로 증착함이 바람직하다. Next, in FIG. 3, the liner high temperature oxide film 600 is deposited after the deposition process of the liner nitride film 500 in order to prevent damage of the liner nitride film 500 by plasma during gap fill with the trench buried oxide 700 by the HDP process. The thickness of the liner high temperature oxide film 600 is preferably deposited to 40 ~ 120Å.

다음으로 도 4 및 도 5에서는 HDP 방법을 이용하여 셀로우 트렌치 아이솔레이션(STI)영역에 트렌치 매립 산화물(700)로 갭필한 후, 라이너 질화막(500)을 연마 정지막으로 하여 화학 기계적 연마(Chemical Mechanical Polishing:CMP) 공정을 진행하여 평탄화한다.Next, in FIGS. 4 and 5, after gap filling with trench buried oxide 700 in the shallow trench isolation (STI) region using the HDP method, chemical mechanical polishing is performed using the liner nitride film 500 as a polishing stop film. Polishing: CMP) process to planarize.

다음으로 도 6에서는 순차적으로 라이너 고온산화막(600), 라이너 질화막(500), 제2패드산화막(400), 패드 질화막(300) 및 제1패드산화막(200)을 순차적으로 제거하여 STI 영역을 형성한다. 여기서 뜨거운 인산(hot phosphoric acid) 용액으로 질화막을 제거하고, 세정 공정으로 산화막을 제거하는 것이 바람직하다.Next, in FIG. 6, the STI region is formed by sequentially removing the liner high temperature oxide film 600, the liner nitride film 500, the second pad oxide film 400, the pad nitride film 300, and the first pad oxide film 200. do. Here, it is preferable to remove the nitride film with a hot phosphoric acid solution and to remove the oxide film by a cleaning process.

따라서 STI 영역의 트렌치 내부에 두개의 라이너 질화막(500) 및 라이너 고온산화막(600)을 증착함으로써 HDP방법에 의하여 트렌치 매립 산화물(700)로 갭필시 라이너 질화막(600)의 손실을 보호함으로써 STI영역에서의 스트레스를 감소시키는 효과가 있다.Therefore, by depositing the two liner nitride film 500 and the liner high temperature oxide film 600 inside the trench of the STI region, the loss of the liner nitride film 600 in the gapfill with the trench buried oxide 700 by the HDP method is prevented. It is effective in reducing stress.

본 발명은 상기 실시예에 한정되지 않고 본 발명의 기술적 요지를 벗어나지 아니하는 범위 내에서 다양하게 수정·변형되어 실시될 수 있음은 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에 있어서 자명한 것이다.It is apparent to those skilled in the art that the present invention is not limited to the above embodiments and can be practiced in various ways without departing from the technical spirit of the present invention. will be.

도 1 부터 도 6은 본 발명에 따른 STI내 라이너 질화막 및 라이너 고온산화막을 증착함으로써 HDP공정에 의한 갭필시 플라즈마에 의한 손상을 방지함으로써 STI 영역에서의 스트레스를 효과적으로 감소시키는 반도체 소자의 제조방법을 나타내는 반도체 소자의 단면도이다. 1 to 6 illustrate a method of manufacturing a semiconductor device which effectively reduces stress in an STI region by preventing plasma damage during gap fill by an HDP process by depositing a liner nitride film and a liner high temperature oxide film in an STI according to the present invention. It is sectional drawing of a semiconductor element.

<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>

100:반도체기판 200:제1패드산화막100: semiconductor substrate 200: first pad oxide film

300:패드질화막 400:제2패드산화막300: pad nitride film 400: second pad oxide film

500:라이너 질화막 600:라이너 고온산화막500: liner nitride film 600: liner high temperature oxide film

700:트렌치 매립 산화물700: trench buried oxide

Claims (4)

반도체 기판상에 순차적으로 제1패드산화막, 패드질화막 및 제2패드산화막 증착하고 사진공정 및 반응성이온에칭공정을 이용한 식각공정을 진행하여 활성영역 및 STI의 트렌치를 형성하는 단계; Sequentially depositing a first pad oxide film, a pad nitride film, and a second pad oxide film on a semiconductor substrate, and performing an etching process using a photo process and a reactive ion etching process to form trenches of an active region and an STI; 상기 제2패드산화막 및 상기 STI의 트렌치 내부에 LP-CVD 방식으로 라이너 질화막을 증착하는 단계;Depositing a liner nitride layer in the second pad oxide layer and the trench of the STI by LP-CVD; 상기 라이너 질화막 위에 라이너 고온산화막을 증착하는 단계;Depositing a liner high temperature oxide film on the liner nitride film; 상기 라이너 고온산화막 위에 HDP 방식으로 갭필절연물질 충진 및 CMP공정으로 평탄화 하는 단계 및 Filling the gap fill insulating material with the HDP method and planarizing the CMP process on the liner high temperature oxide film; and 습식공정을 진행하여 반도체 기판상의 최상층에 증착된 라이너 고온산화막, 라이너질화막, 제2산화막, 패드질화막 및 제1패드산화막을 순차적으로 식각하여 STI를 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 제조방법.Performing a wet process to sequentially etch the liner high temperature oxide film, the liner nitride film, the second oxide film, the pad nitride film, and the first pad oxide film deposited on the uppermost layer on the semiconductor substrate to form an STI. Manufacturing method. 제 1항에 있어서,      The method of claim 1, 상기 라이너 질화막 및 상기 라이너 고온산화막의 두께가 동일하게 형성되는 것을 특징으로 하는 반도체 소자의 제조방법.      And the liner nitride film and the liner high temperature oxide film have the same thickness. 제 1항에 있어서, The method of claim 1, 상기 라이너 질화막의 두께는 40~120Å인 것을 특징으로 하는 반도체 소자의 제조방법. The thickness of the liner nitride film is a manufacturing method of a semiconductor device, characterized in that 40 ~ 120Å. 제 1항에 있어서, The method of claim 1, 상기 라이너 고온산화막의 두께는 40~120Å인 것을 특징으로 하는 반도체 소자의 제조방법.The thickness of the liner high temperature oxide film is a manufacturing method of a semiconductor device, characterized in that 40 ~ 120Å.
KR1020080106419A 2008-10-29 2008-10-29 Method of manufacturing semiconductor device KR101056244B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020080106419A KR101056244B1 (en) 2008-10-29 2008-10-29 Method of manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020080106419A KR101056244B1 (en) 2008-10-29 2008-10-29 Method of manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
KR20100047496A true KR20100047496A (en) 2010-05-10
KR101056244B1 KR101056244B1 (en) 2011-08-11

Family

ID=42274457

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020080106419A KR101056244B1 (en) 2008-10-29 2008-10-29 Method of manufacturing semiconductor device

Country Status (1)

Country Link
KR (1) KR101056244B1 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8697579B2 (en) 2011-02-09 2014-04-15 Samsung Electronics Co., Ltd. Method of forming an isolation structure and method of forming a semiconductor device
WO2024019440A1 (en) * 2022-07-22 2024-01-25 주식회사 에이치피에스피 Method for manufacturing semiconductor device

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100527595B1 (en) * 2004-02-16 2005-11-09 주식회사 하이닉스반도체 Method of Forming Isolated Oxide in the Semiconductor Device
KR20050118490A (en) * 2004-06-14 2005-12-19 주식회사 하이닉스반도체 Method for isolation in semiconductor device
KR20060011612A (en) * 2004-07-30 2006-02-03 주식회사 하이닉스반도체 Method for isolation in semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8697579B2 (en) 2011-02-09 2014-04-15 Samsung Electronics Co., Ltd. Method of forming an isolation structure and method of forming a semiconductor device
WO2024019440A1 (en) * 2022-07-22 2024-01-25 주식회사 에이치피에스피 Method for manufacturing semiconductor device

Also Published As

Publication number Publication date
KR101056244B1 (en) 2011-08-11

Similar Documents

Publication Publication Date Title
US8384188B2 (en) Semiconductor device and fabrication method thereof
US20020127818A1 (en) Recess-free trench isolation structure and method of forming the same
CN101656226A (en) Method for forming shallow trench isolation structure
US7670926B2 (en) Method for forming shallow trench isolation utilizing two filling oxide layers
KR20110052206A (en) Semiconductor device having a device isolation structure
US6544861B2 (en) Method for forming isolation trench
US20110012226A1 (en) Semiconductor device and method for manufacturing the same
US20020053715A1 (en) Trench isolation structure having a curvilinear interface at upper corners of the trench isolation region, and method of manufacturing the same
KR101056244B1 (en) Method of manufacturing semiconductor device
US6180492B1 (en) Method of forming a liner for shallow trench isolation
KR100546855B1 (en) Method For Manufacturing Semiconductor Devices
KR100703836B1 (en) Method for forming trench type isolation layer in semiconductor device
KR100875346B1 (en) Manufacturing method of shallow trench isolation
KR20040059445A (en) Method for forming trench type isolation layer in semiconductor device
KR20100074668A (en) Manufacturing method for isolation structure of semiconductor device
US8043932B2 (en) Method of fabricating semiconductor device
KR20090053036A (en) Method of manufacturing a flash memory device
KR100519648B1 (en) Method For Manufacturing Semiconductor Devices
KR100653704B1 (en) Methods of forming trench isolation in semiconductor device and trench isolation structure fabricated thereby
KR20070001421A (en) Method for forming trench type isolation layer in semiconductor device
KR100579962B1 (en) Method For Manufacturing Semiconductor Devices
KR100822620B1 (en) Method of manufacturing a semiconductor device
KR100539005B1 (en) Method For Manufacturing Semiconductor Devices
KR100924544B1 (en) Method for forming isolation layer of semiconductor device
KR20100076377A (en) Method for fabricating method semiconductor device

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E90F Notification of reason for final refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
LAPS Lapse due to unpaid annual fee