KR20100036004A - Method of manufacturing semiconductor device - Google Patents

Method of manufacturing semiconductor device Download PDF

Info

Publication number
KR20100036004A
KR20100036004A KR1020080095428A KR20080095428A KR20100036004A KR 20100036004 A KR20100036004 A KR 20100036004A KR 1020080095428 A KR1020080095428 A KR 1020080095428A KR 20080095428 A KR20080095428 A KR 20080095428A KR 20100036004 A KR20100036004 A KR 20100036004A
Authority
KR
South Korea
Prior art keywords
semiconductor device
manufacturing
solution
semiconductor substrate
cmp
Prior art date
Application number
KR1020080095428A
Other languages
Korean (ko)
Inventor
정종구
김형환
박성은
Original Assignee
주식회사 하이닉스반도체
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR1020080095428A priority Critical patent/KR20100036004A/en
Publication of KR20100036004A publication Critical patent/KR20100036004A/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819—Smoothing of the dielectric

Abstract

The present invention discloses a method of retrofitting a semiconductor device capable of improving the manufacturing yield by simplifying the process of manufacturing a semiconductor device to which copper wiring is applied. A method of manufacturing a semiconductor device according to the present invention disclosed herein is a method of manufacturing a semiconductor device capable of simplifying a process, wherein during the CMP process of an insulating film formed on a semiconductor substrate, a conductive film on a rear surface of the semiconductor substrate is cleaned using a cleaner of a CMP device. It is characterized by removing together.

Description

Method of manufacturing semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device capable of improving the production yield by simplifying a device formation process using copper wiring.

In general, a capacitor including a storage node, a dielectric layer, and a plate node is formed in a semiconductor device, and a metal wiring is formed to contact the capacitor. On the other hand, according to the trend of high integration of semiconductor devices, aluminum and tungsten having excellent electrical conductivity have been mainly used as a material for metal wiring. Recently, research has been conducted to use copper as a next-generation metallization material that can solve the RC signal delay problem in highly integrated high-speed operation devices because the electrical conductivity is much better and the resistance is lower than that of aluminum and tungsten.

However, when copper is used as the metallization material, a copper film is formed on the rear surface of the semiconductor substrate. In this case, the copper component diffuses outward into the semiconductor substrate from the copper film on the rear surface of the semiconductor substrate, and acts as an impurity, whereby a leakage current is generated to cause a defect of the semiconductor element. Accordingly, in order to prevent outward diffusion of the copper component, a diffusion barrier layer, for example, a nitride layer, must be formed on the rear surface of the semiconductor substrate.

In addition, in order to reduce the resistance of the plate node of the capacitor, a polysilicon film, which is a conductive film for the plate node, is formed by using a furnace equipment. In this case, the polysilicon film is formed on the diffusion barrier layer on the back surface of the semiconductor substrate. . Accordingly, a process for removing the polysilicon film portion formed on the diffusion barrier on the back surface of the semiconductor substrate is essentially accompanied.

However, in the above-described prior art, after the insulating film is formed on the semiconductor substrate on which the capacitor is formed and the insulating film is CMP, the polysilicon film portion is removed. For this reason, in the case of the conventional technology described above, a wet equipment is additionally required to remove the polysilicon film, and thus, a lot of time and cost are required in manufacturing a semiconductor device. Degrades. In addition, in the above-described prior art, the concentration of the etching solution used in the wet equipment is changed, so that the polysilicon film portion cannot be removed properly, or the particles in the etching solution are redeposited on the semiconductor substrate, thereby deteriorating the semiconductor device. Is generated.

The present invention provides a method for manufacturing a semiconductor device that can improve the manufacturing yield by simplifying the process of manufacturing a semiconductor device to which copper wiring is applied.

In addition, the present invention provides a semiconductor device and a method of manufacturing the same that can suppress the failure of the semiconductor device to improve the characteristics and reliability of the device.

In one aspect, a method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device that can simplify the process, during the CMP process of the insulating film formed on the semiconductor substrate, using a cleaner of the CMP equipment back surface of the semiconductor substrate It includes removing together the conductive film.

The conductive film is a polysilicon film.

The cleaner of the CMP equipment includes a bath clean and three modules, Brush 1 and Brush 2.

The bath clean module is performed using SC-1 solution.

The bath clean module is performed by using an SC-1 solution and an oxidant together.

The oxidant includes any one of a tetramethyl ammonium hydroxide (TMAH) solution and a H 2 O 2 solution.

The oxidant is supplied in the same bath as the SC-1 solution.

The oxidant is mixed and supplied to the slurry used in the CMP process.

The Brush1 module is performed using NH 4 OH solution.

The Brush 2 module is performed using HF solution and HNO 3 solution.

In another aspect, the method of manufacturing a semiconductor device according to the present invention includes the steps of forming a conductive film on a semiconductor substrate, forming an insulating film on the conductive film and CMP the insulating film, and forming the conductive film. Removing a portion of the conductive film formed on the back surface of the semiconductor substrate.

The conductive film formed on the semiconductor substrate is a conductive film for plate nodes.

The conductive film formed on the semiconductor substrate is a laminated film of a TiN film and a polysilicon film.

Removal of the conductive film portion formed on the back surface of the semiconductor substrate is performed using a cleaner of the CMP equipment used in the CMP of the insulating film.

The cleaner of the CMP equipment includes a bath clean and three modules, Brush 1 and Brush 2.

The bath clean module is performed using SC-1 solution.

The bath clean module is performed by using an SC-1 solution and an oxidant together.

The oxidant includes any one of a tetramethyl ammonium hydroxide (TMAH) solution and a H 2 O 2 solution.

The oxidant is supplied in the same bath as the SC-1 solution.

The oxidant is mixed and supplied to the slurry used in the CMP process.

The Brush1 module is performed using NH 4 OH solution.

The Brush 2 module is performed using HF solution and HNO 3 solution.

The present invention forms an insulating film on a polysilicon film, which is a conductive film for a plate node, and then removes the polysilicon film on the back of the semiconductor substrate using a cleaner of the CMP equipment during the CMP process of the insulating film.

This eliminates the need for additional equipment and process steps to remove the polysilicon film on the back of the semiconductor substrate, thereby simplifying the process and reducing the cost and process time.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1A to 1C are cross-sectional views of processes for describing a method of manufacturing a semiconductor device according to an embodiment of the present invention.

Referring to FIG. 1A, a capacitor C is formed on a semiconductor substrate 100 having an underlayer including an interlayer insulating layer 102 and a contact plug 104 for a storage node. The capacitor C includes the storage node 106, the dielectric layer 108, and the plate node 113, and is electrically connected to the contact plug 104 for the storage node. The plate node 113 includes a stacked structure of a TiN film 110 and a polysilicon film 112a as a conductive film.

Here, the polysilicon film 112a, which is a conductive film for the plate node, is formed by using a furnace equipment to reduce the resistance of the plate node of the capacitor C. At this time, the polysilicon film 112a is formed on the rear surface of the semiconductor substrate 100. The polysilicon film 112b is formed.

Meanwhile, in order to form copper with a subsequent metallization material, since the diffusion barrier layer 111 formed of a nitride film is formed on the rear surface of the semiconductor substrate 100 to prevent outward diffusion of the copper component, the semiconductor substrate 100 The polysilicon film 112b on the back surface is formed on the diffusion barrier film 111.

When the polysilicon film 112b is formed on the diffusion barrier film 111, since the outward diffusion of the copper component may not be properly prevented, the polysilicon film 112b formed on the diffusion barrier film 111 should be removed.

Referring to FIG. 1B, a first insulating layer 114 is formed on the semiconductor substrate 100 to cover the capacitor C. Referring to FIG. The first insulating film 114 includes, for example, an oxide film. In this case, the first insulating layer 114 has a very large step in, for example, a cell region in which data storage elements are formed and a peripheral circuit region formed at a position adjacent to the cell region.

Referring to FIG. 1C, a CMP process is performed to planarize and remove a step of the first insulating layer 114. Here, in the exemplary embodiment of the present invention, the polysilicon film 112b, which is a conductive film on the rear surface of the semiconductor substrate 100, is oxidized and removed together using a cleaner of the CMP equipment used in the CMP process.

First, the cleaner of the CMP equipment includes a bath clean and three modules of Brush 1 and Brush 2, wherein the Bath Clean module is performed using, for example, a Standard clean-1 (SC-1) solution. The SC-1 solution serves to remove the defect. In addition, the bath clean module according to an embodiment of the present invention can be performed using the SC-1 solution and the oxidant. In this case, the surface of the polysilicon film 112b on the back surface of the semiconductor substrate 100 is oxidized.

Here, the oxidizing agent includes any one of a TMAH (Tetramethyl ammonium hydroxide) solution and H 2 O 2 solution. The TMAH solution is used to improve the wet etch rate for removing the polysilicon layer 112b on the back surface of the semiconductor substrate 100. The oxidant is preferably mixed and supplied to the slurry used in the CMP process, may be supplied in the same bath as the SC-1 solution, or may be supplied through a separate line.

Then, the Brush1 module is performed using NH 4 OH solution. The NH 4 OH solution serves to remove metal ions or particles generated during the CMP process.

Subsequently, the Brush 2 module is performed using HF solution and HNO 3 solution. At this time, the surface of the polysilicon film 112b on the back surface of the semiconductor substrate 100 oxidized in the bath clean module is removed, and the polysilicon film 112b formed on the diffusion barrier film 111 is completely removed.

Here, in the embodiment of the present invention, since the polysilicon film 112b on the back side of the semiconductor substrate 100 may be removed together using the cleaner of the CMP device during the CMP process, the polysilicon on the back surface of the semiconductor substrate 100 may be removed. No additional equipment and process steps are needed to remove the silicon film 112b. Through this, the present invention can simplify the process and reduce the cost and processing time.

Referring to FIG. 1D, a contact plug 116 is formed in the CMP first insulating layer 114 to be electrically connected to the capacitor C. Referring to FIG. After the second insulating layer 118 is formed on the CMP first insulating layer 114 including the contact plug 116, the second insulating layer 118 is etched to expose the contact plug 116. Form the formation region. Then, the wiring formation region is filled with a copper film to form a copper wiring 120.

In this case, since the polysilicon film is removed from the back surface of the semiconductor substrate 100 to form only the diffusion barrier 111, it is possible to prevent the outward diffusion of the copper component caused when the copper wiring 120 is formed.

Thereafter, a series of subsequent processes are performed in sequence to complete the semiconductor device according to the embodiment of the present invention.

According to the above-described embodiment of the present invention, the polysilicon film on the back of the semiconductor substrate is removed together with the cleaner of the CMP equipment during the CMP process of the insulating film, and thus, the polysilicon film on the back of the semiconductor substrate is further removed after the CMP process. The process can be simplified compared to the conventional process case performed.

In addition, the present invention does not require additional equipment and process time for removing the polysilicon film on the back of the semiconductor substrate can improve the manufacturing yield.

In addition, the present invention can completely remove the polysilicon film formed on the diffusion barrier on the back of the semiconductor substrate during the CMP process, thereby effectively preventing the outward diffusion of the copper component.

On the other hand, the CMP equipment presented in the present invention is applicable to all CMP equipment, including CMP equipment such as Applied Materials in the United States and Ebara in Japan.

As mentioned above, although the present invention has been illustrated and described with reference to specific embodiments, the present invention is not limited thereto, and the following claims are not limited to the scope of the present invention without departing from the spirit and scope of the present invention. It can be easily understood by those skilled in the art that can be modified and modified.

1A to 1D are cross-sectional views of processes for describing a method of manufacturing a semiconductor device according to an embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

100 semiconductor substrate 102 interlayer insulating film

104: contact plug for storage node 106: storage node

108: dielectric film 110: TiN film

111: diffusion barrier 112a: polysilicon film

112b: polysilicon film on backside of semiconductor substrate 113: plate node

C: Capacitor 114: First Insulation Film

116: contact plug 118: second insulating film

120: copper wiring

Claims (22)

As a method of manufacturing a semiconductor device capable of simplifying the process, In the CMP process of the insulating film formed on the semiconductor substrate, A method of manufacturing a semiconductor device comprising removing the conductive film on the back surface of the semiconductor substrate using a cleaner of a CMP device. The method of claim 1, The conductive film is a method for manufacturing a semiconductor device, characterized in that the polysilicon film. The method of claim 1, The cleaner of the CMP device comprises a bath clean and three modules of brush1 and brush2. The method of claim 3, wherein The bath clean module is a method of manufacturing a semiconductor device, characterized in that performed using the SC-1 solution. The method of claim 3, wherein The bath clean module is a method of manufacturing a semiconductor device, characterized in that performed using a SC-1 solution and an oxidant. The method of claim 5, The oxidant is a method for manufacturing a semiconductor device, characterized in that it comprises any one of TMAH (Tetramethyl ammonium hydroxide) solution and H 2 O 2 solution. The method of claim 5, Wherein the oxidant is supplied in the same bath as the SC-1 solution. The method of claim 5, The oxidizing agent is a method of manufacturing a semiconductor device, characterized in that the mixture supplied to the slurry used in the CMP process. The method of claim 3, wherein The brush 1 module is a method of manufacturing a semiconductor device, characterized in that performed using NH 4 OH solution. The method of claim 3, wherein The brush 2 module is a method of manufacturing a semiconductor device, characterized in that performed using HF solution and HNO 3 solution. Forming a conductive film on the semiconductor substrate; Forming an insulating film on the conductive film; And Removing the conductive film portion formed on the rear surface of the semiconductor substrate when the conductive film is formed while the CMP of the insulating film is formed; Method of manufacturing a semiconductor device comprising a. The method of claim 11, The conductive film formed on the semiconductor substrate is a manufacturing method of a semiconductor device, characterized in that the conductive film for the plate node. The method of claim 11, And the conductive film formed on the semiconductor substrate is a laminated film of a TiN film and a polysilicon film. The method of claim 11, The removal of the conductive film portion formed on the back surface of the semiconductor substrate is performed using a cleaner of the CMP equipment used for CMP of the insulating film. The method of claim 14, The cleaner of the CMP device comprises a bath clean and three modules of brush1 and brush2. The method of claim 15, The bath clean module is a method of manufacturing a semiconductor device, characterized in that performed using the SC-1 solution. The method of claim 15, The bath clean module is a method of manufacturing a semiconductor device, characterized in that performed using a SC-1 solution and an oxidant. The method of claim 17, The oxidant is a method for manufacturing a semiconductor device, characterized in that it comprises any one of TMAH (Tetramethyl ammonium hydroxide) solution and H 2 O 2 solution. The method of claim 17, Wherein the oxidant is supplied in the same bath as the SC-1 solution. The method of claim 17, The oxidizing agent is a method of manufacturing a semiconductor device, characterized in that the mixture supplied to the slurry used in the CMP process. The method of claim 15, The brush 1 module is a method of manufacturing a semiconductor device, characterized in that performed using NH 4 OH solution. The method of claim 15, The brush 2 module is a method of manufacturing a semiconductor device, characterized in that performed using HF solution and HNO 3 solution.
KR1020080095428A 2008-09-29 2008-09-29 Method of manufacturing semiconductor device KR20100036004A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020080095428A KR20100036004A (en) 2008-09-29 2008-09-29 Method of manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020080095428A KR20100036004A (en) 2008-09-29 2008-09-29 Method of manufacturing semiconductor device

Publications (1)

Publication Number Publication Date
KR20100036004A true KR20100036004A (en) 2010-04-07

Family

ID=42213730

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020080095428A KR20100036004A (en) 2008-09-29 2008-09-29 Method of manufacturing semiconductor device

Country Status (1)

Country Link
KR (1) KR20100036004A (en)

Similar Documents

Publication Publication Date Title
JP2004532519A (en) Manufacturing method of electronic structure
KR20100122701A (en) Method of manufacturing semiconductor device
JP2007109894A (en) Semiconductor device and its manufacturing method
US20070190797A1 (en) Cleaning method for use in semiconductor device fabrication
JP4963815B2 (en) Cleaning method and semiconductor device manufacturing method
CN108573911B (en) Semiconductor structure and forming method thereof
CN111106158A (en) Semiconductor structure and forming method thereof
US6136694A (en) Method for forming via hole
KR20100036004A (en) Method of manufacturing semiconductor device
CN114078752A (en) Semiconductor structure and forming method thereof
US20230377894A1 (en) Method of forming semiconductor device and substrate processing system for forming semiconductor device
US11545552B2 (en) Semiconductor structure and method for forming the same
CN111446204B (en) Semiconductor structure and forming method thereof
CN111081630B (en) Semiconductor structure and forming method thereof
KR100367403B1 (en) Method for forming contact of a semiconductor device
KR100702802B1 (en) Method for forming metal wiring layer of semiconductor device
KR100955838B1 (en) Semiconductor device and method for forming metal line in the same
KR100835779B1 (en) Method of manufacturing a semiconductor device
CN115602608A (en) Method for forming semiconductor structure
KR100639205B1 (en) Method of manufacturing semiconductor device
JP2007188911A (en) Semiconductor device, and method of manufacturing same
KR100447325B1 (en) Method of forming a metal wiring in a semiconductor device
KR100874432B1 (en) Method for cleaning a wafer and method for forming a metal line in semiconductor device using the same
CN116936532A (en) Semiconductor structure and forming method thereof
CN112349651A (en) Semiconductor structure and forming method thereof

Legal Events

Date Code Title Description
WITN Withdrawal due to no request for examination