KR20100025843A - Termination circuit for semiconductor device - Google Patents

Abstract

PURPOSE: The termination circuit of a semiconductor device is provided to improve the yield of the semiconductor device by trimming a termination resistance value based on a plurality of load control signals. CONSTITUTION: A fuse part(410) includes a plurality of fuses in which termination trimming information is programmed. The fuse part outputs a plurality of fuse state signals corresponding to the electrical state of each fuse. A termination trimming control part(420) generates a plurality of load control signals in response to a termination test signal and the fuse state signals. A termination part(430) trims a termination resistance value in response to the load control signals. The termination trimming control part includes a plurality of pull-up load control parts(421) and a plurality of full-down load control parts(422).

Description

Termination Circuit for Semiconductor Devices {TERMINATION CIRCUIT FOR SEMICONDUCTOR DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor design technique, and to a technique for configuring a termination circuit of a semiconductor element.

The semiconductor device includes a termination circuit for terminating an input signal applied through an input / output pad. As described above, the termination circuit provided in the semiconductor device may be referred to as an on die termination (ODT) circuit.

1 is a circuit diagram of a termination circuit of a semiconductor device of the prior art.

Referring to FIG. 1, a termination circuit of a semiconductor device is activated in response to a pull-up termination unit 110 and a pull-down termination code NCODE <0: 1> that are activated in response to a pull-up termination code PCODE <0: 1>. A pull-down termination part 120 is provided.

Looking at the detailed configuration and operation of the termination circuit of the semiconductor device configured as described above are as follows.

First, the pull-up termination unit 110 is connected between the power supply voltage terminal VDDQ and the first node N0 to receive the first pull-up active load MP1 controlled by the first pull-up termination code PCODE <0>, A second pull-up active load MP2 is connected between the power supply voltage terminal VDDQ and the first node N0 and is controlled by the second pull-up termination code PCODE <1>. In addition, a first pull-up termination resistor PU_R1 is inserted between the first pull-up active load MP1 and the first node N0, and a first pull-up active load MP2 and the first node N0 are inserted between the first pull-up active load MP1 and the first node N0. 2 Pull-up termination resistor PU_R2 is inserted.

Next, the pull-down termination unit 120 is connected between the ground voltage terminal VSSQ and the first node N0 to receive the first pull-down active load MN1 under the control of the first pull-down termination code NCODE <0>. And a second pull-down active load MN2 connected between the ground voltage terminal VSSQ and the first node N0 and controlled by the second pull-down termination code NCODE <1>. Also, a first pull-down termination resistor PD_R1 is inserted between the first pull-down active load MN1 and the first node N0, and a first pull-down termination resistor PD_R1 is inserted between the second pull-down active load MN2 and the first node N0. 2 Pull-down termination resistor PD_R2 is inserted.

The first pull-up active load MP1 and the second pull-up active load MP2, which are activated under the control of the pull-up termination code PCODE <0: 1>, are configured as PMOS transistors. The switch acts as a switch for activating the pull-up termination resistor PU_R1 and the second pull-up termination resistor PU_R2, and also serves as a load itself to determine the overall pull-up termination resistance value. That is, the pull-up termination resistance value is determined under the control of the pull-up termination code PCODE <0: 1>.

In addition, the first pull-down active load MN1 and the second pull-down active load MN2, which are activated under the control of the pull-down termination code NCODE <0: 1>, are composed of NMOS transistors, which are turned on. The switch acts as a switch for activating the first pull-down termination resistor PD_R1 and the second pull-down termination resistor PD_R2, and serves as a load itself to determine the overall pull-down termination resistance value. That is, the pull-down termination resistance value is determined under the control of the pull-down termination code NCODE <0: 1>.

As described above, since the pull-up and pull-down termination resistance values are determined by the control of the pull-up termination code PCODE <0: 1> and the pull-down termination code NCODE <0: 1>, termination can be controlled. The actual termination resistance Rtt effective viewed from the input / output pad DQ connected to the first node N0 becomes a parallel resistance value of the pull-up termination resistance value and the pull-down termination resistance value. The pull-up termination resistance and the pull-down termination resistance are designed to be equal to each other. The resistance value changes as the PVT changes. If the difference between the resistance value generated at the same voltage (VOLTAGE) and temperature (TEMPERATURE) can be seen as the effect of the process (PROCESS). The difference between the pull-up termination and pull-down termination resistance is defined as the termination mismatch, and when the semiconductor device is tested, the pull-up and pull-down termination resistance values are adjusted to adjust the pull-up and pull-down termination resistance values within the design target tolerance. You will work to correct and trim the termination mismatch.

When termination mismatch occurs in the termination circuit of the semiconductor device, the first pull-up termination resistor PU_R1, the second pull-up termination resistor PU_R2, the first pull-down termination resistor PD_R1, and the second pull-down termination resistor PD_R2 Assuming that the resistance values of the passive elements such as) are the same, the first pull-up active load MP1, the second pull-up active load MP2, the first pull-down active load MN1 and the second pull-down active load MN2 Differences in the current-voltage characteristics of active devices, such as, may cause termination mismatch. That is, termination mismatch occurs due to the difference in characteristics of each PMOS transistor and NMOS transistor.

Meanwhile, the general formula used to measure the termination resistance value (Rtt effective) and the termination mismatch (Rtt mismatch) is as follows.

2 is a formula used for measuring termination resistance and termination mismatch.

Referring to FIG. 2, the termination resistance value 210 may be calculated using the amount of current according to the input voltage level. As described above, when measuring the resistance values according to the current and voltage characteristics, the termination resistance value (Rtt effective) is calculated from the slope of two points of the high level and the low level of the input voltage instead of any one point.

In addition, the termination mismatch 220 may be calculated using the termination measurement voltage Vm measured by the input / output pad DQ when the termination circuit is operated. Termination mismatch is expressed as a percentage based on half of the supply voltage (VDDQ). This formula can only calculate the difference between the pull-up termination resistance and the pull-down termination resistance, and it is not known whether the pull-up or pull-down termination resistance is larger or smaller than the design target.

3 is a diagram for a pull-up termination resistance value and a pull-down termination resistance value.

Referring to FIG. 3, current-voltage characteristics of a pull-up active load of a pull-up termination part and a pull-down active load of a pull-down termination part are shown. That is, the current-voltage characteristics of the PMOS transistor and the NMOS transistor can be referred to as the slope of the resistance value.

Conventionally, the termination mismatch (Rtt mismatch) was checked by using the termination measurement voltage (Vm), and the pull-up termination resistance value and the pull-down termination resistance value had to be confirmed by measuring the current-voltage characteristics of each active element for trimming. . Therefore, a problem that the test time of the semiconductor device takes too long occurred.

SUMMARY OF THE INVENTION The present invention has been proposed to solve the above conventional problems, and provides a termination circuit of a semiconductor device capable of quickly trimming a termination mismatch between a pull-up termination resistance value and a pull-down termination resistance value due to process differences. The purpose.

According to an aspect of the present invention for achieving the above technical problem, a fuse unit having a plurality of fuses, the termination trimming information is programmed, for outputting a plurality of fuse status signals corresponding to the electrical state of each fuse; A termination trimming controller configured to generate a plurality of load control signals in response to a termination test signal and the plurality of fuse state signals; And a termination part in which a termination resistance value is trimmed in response to the plurality of load control signals.

The present invention uses a method of cutting the fuse to check the termination mismatch through the termination measurement voltage when the termination circuit is operating, and to adjust the predetermined pull-up termination resistance value and the pull-down termination resistance value through the lookup table. It was.

According to the present invention, since the termination mismatch can be trimmed by cutting the fuse through a lookup table, the pull-up termination resistance value and the pull-down termination resistance value do not need to be individually measured again as in the prior art. Therefore, the test time of the semiconductor device is shortened and the yield of the semiconductor device can be improved by trimming the termination mismatch.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .

In general, the logic signal of the circuit is divided into a high level (HIGH LEVEL, H) or a low level (LOW LEVEL, L) corresponding to the voltage level, and may be expressed as '1' and '0', respectively. In addition, it is defined and described that it may additionally have a high impedance (HI-Z) state and the like. In addition, PMOS (P-channel Metal Oxide Semiconductor) and N-channel Metal Oxide Semiconductor (NMOS), which are terms used in the present embodiment, are known to be a type of MOSFET (Metal Oxide Semiconductor Field-Effect Transistor).

4 is a termination circuit of a semiconductor device according to an embodiment of the present invention.

Referring to FIG. 4, a termination circuit of a semiconductor device includes a plurality of fuses in which termination trimming information is programmed, and outputs a plurality of fuse state signals TM_PUP1, TM_PUP2, TM_PDN1, and TM_PDN2 corresponding to electrical states of each fuse. A plurality of load control signals P_EN <0: 2>, N_EN <0: 2> in response to the fuse unit 410, the termination test signal TM_ODT_EN, and the plurality of fuse status signals TM_PUP1, TM_PUP2, TM_PDN1, TM_PDN2. Termination trimming control unit 420 for generating a) and a termination unit 430 is trimmed in response to a plurality of load control signals (P_EN <0: 2>, N_EN <0: 2>).

Looking at the detailed configuration and operation of the termination circuit of the semiconductor device configured as described above are as follows.

The termination trimming controller 420 is configured to generate a plurality of pull-up load control signals P_EN <0: 2> corresponding to each fuse state signal in response to the termination test signal / TM_ODT_EN. The plurality of pull-down load controllers 422 are configured to generate a plurality of pull-down load control signals N_EN <0: 2> corresponding to each fuse state signal in response to the termination test signal TM_ODT_EN.

Here, the plurality of pull-up load controllers 421 include a plurality of logical sum means for inputting the termination test signal / TM_ODT_EN and the corresponding fuse state signals / TM_PUP1 and TM_PUP2. In addition, it may further comprise a logic sum means for inputting the termination test signal / TM_ODT_EN and the ground voltage (VSS). In the embodiment, the logical sum means is implemented by using a NOR GATE and an inverter. Accordingly, the plurality of pull-up load controllers 421 may invert the signals output from the first NOR0 and the NOR0 that receive the termination test signal / TM_ODT_EN and the ground voltage VSS. Inverts the signals output from the second NOR1 and the second NOR1 to which the first inverter INV0, the termination test signal / TM_ODT_EN, and the first fuse state signal / TM_PUP1 are input. Inverts the signals output from the third NOR2 and the third NORgate NOR2 that input the second inverter INV1, the termination test signal / TM_ODT_EN, and the second fuse state signal TM_PUP2. It consists of a third inverter (INV2) to make.

In addition, the plurality of pull-down load controllers 422 are configured by logical multiplication means for inputting the termination test signal TM_ODT_EN and the corresponding fuse state signals TM_PDN1 and / TM_PDN2. In addition, it may further comprise a logical multiplication means for inputting the termination termination test signal (TM_ODT_EN) and the power supply voltage (VDD). In the embodiment, the logical multiplication means is implemented using a NAND gate and an inverter (INVERTER). Therefore, the plurality of pull-down load controllers 422 may be configured to invert signals output from the first NAND gate NAND0 and the first NAND gate NAND0, which input the termination test signal TM_ODT_EN and the power supply voltage VDD. Fourth for inverting the signals output from the second and second NAND gates NAND1 and NAND1 inputting the inverter INV3, the termination test signal TM_ODT_EN and the third fuse state signal TM_PDN1. Sixth for inverting the signals output from the third and third NAND gates NAND2 and NAND2 that input the inverter INV4, the termination test signal TM_ODT_EN, and the fourth fuse state signal / TM_PDN2. It consists of an inverter INV5.

The termination unit 430 is connected between the power supply voltage terminal VDDQ and the first node N0 to be connected in parallel with each other, which is activated under the control of a plurality of pull-up load control signals P_EN <0: 2>. The pull-up termination unit 431 including the active loads MP0 to MP5 is connected between the ground voltage terminal VSSQ and the first node N0 to control the plurality of pull-down load control signals N_EN <0: 2>. It is composed of a pull-down termination unit 432 having a plurality of pull-down active loads (MN0 ~ MN5) connected in parallel to each other activated by receiving. In addition, the pull-up termination unit 431 may further include pull-up termination resistors PU_R1 and PU_R2 connected in series with the plurality of pull-up active loads MP0 to MP5. In addition, the pull-down termination unit 120 may further include pull-down termination resistors PD_R1 and PD_R2 connected in series with the plurality of pull-down active loads MN0 to MN5. The plurality of pull-up active loads MP0 to MP5 are PMOS transistors, and the plurality of pull-down active loads MN0 to MN5 are NMOS transistors.

It is assumed that the resistance values of the passive devices such as the first pull-up termination resistor PU_R1, the second pull-up termination resistor PU_R2, the first pull-down termination resistor PD_R1, and the second pull-down termination resistor PD_R2 are all the same. If the termination circuit is composed of only such passive elements, the termination resistance of the termination unit 430 will have a constant value at the same voltage and temperature. However, since the switch for selectively activating the termination resistors PU_R1, PU_R2, PD_R1, and PD_R2 of the passive element is composed of transistors, the switch itself serves as an active load, forming a termination resistance value. Active loads, such as transistors, may have different current-voltage characteristics for each semiconductor device due to process differences.

In the exemplary embodiment of the present invention, the pull-up termination unit 431 includes a plurality of pull-up active rods connected in parallel to each other which are activated under the control of a plurality of pull-up load control signals P_EN <0: 2> to adjust the pull-up termination resistance value. (MP0 to MP5). In addition, the pull-down termination unit 432 includes a plurality of pull-down active loads MN0 to MN5 connected in parallel to each other, which are activated under the control of a plurality of pull-down load control signals N_EN <0: 2> to adjust the pull-down termination resistance value. ) Will be provided.

Since the plurality of pull-up active loads MP0 to MP5 are connected in parallel with each other, the resistance value can be adjusted by adjusting the number of turns on by the pull-up load control signal P_EN <0: 2>. Will be. In addition, since the plurality of pull-down active loads MN0 to MN5 are connected in parallel with each other, the resistance value can be adjusted by adjusting the number of turns on by the pull-down load control signal N_EN <0: 2>. Will be.

The pull-up load control signals P_EN <0: 2> and the pull-down load control signals N_EN <0: 2> use the fuse state signals TM_PUP1, TM_PUP2, TM_PDN1, and TM_PDN2 of the fuse unit 410 as described above. Since the termination trimming control unit 420 is generated, the termination mismatch is calculated using the termination measurement voltage Vm measured at the input / output pad DQ connected to the first node N0 when the termination circuit operates. The cut adjusts the pull-up termination and pull-down termination resistor values and trims the termination mismatch. The change in the resistance value due to the fuse cutting is made in a LOOKUP TABLE and used for testing a semiconductor device. This eliminates the need to measure current-voltage characteristics to calculate pull-up termination and pull-down termination resistances while trimming termination mismatches.

5 is a diagram illustrating an example of trimming a termination mismatch using FIG. 4.

A description with reference to FIGS. 4 and 5 is as follows. If the termination measurement voltage Vm measured by the input / output pad DQ is lower than the reference value based on half of the power supply voltage VDDQ (0.750V), it means that the pull-up termination resistance value is larger than the pull-down termination resistance value. Also, higher than the reference means that the pull-down termination resistance value is greater than the pull-up termination resistance value. Therefore, if you only look at the mismatch between the pull-up and pull-down termination resistance value, it is possible to trim the termination mismatch by increasing or decreasing the pull-up or pull-down termination resistance value according to the result of comparing the termination measurement voltage (Vm) with the reference. However, the termination mismatch calculated using the termination measurement voltage (Vm) represents a relative ratio, so in practice the pull-up termination and pull-down termination resistances are adjusted within the allowable range of the targets specified in the design. Should be.

The plurality of fuse state signals TM_PUP1, TM_PUP2, TM_PDN1, and TM_PDN2 output from the fuse unit 410 are all initially output at a high level, and the termination trimming control unit 420 is at the high level when the termination test signal TM_ODT_EN is high. The pull-up load control signals P_EN <0: 2> and the pull-down load control signals N_EN <0: 2> are output using the plurality of fuse state signals TM_PUP1, TM_PUP2, TM_PDN1, and TM_PDN2. Initially, the pull-up control signals P_EN <0: 2> are output at high level, low level, and low level, respectively, in that order. In addition, the pull-down load control signals N_EN <0: 2> are output at low level, high level, and high level, respectively, in order. Therefore, as shown in FIG. 5, the pull-up and pull-down load control signals P_EN <0: 2> and N_EN <0: 2> are generated through the fuse cutting, and the termination mismatch is trimmed. In the exemplary embodiment, when the first fuse state signal / TM_PUP1 is output to the high level through the fuse cutting in the initial state, the pull-up termination resistance value is increased, and when the second fuse state signal TM_PUP2 is output to the low level, the pull-up termination is performed. The resistance value becomes small. In addition, when the third fuse state signal TM_PDN1 is output at a low level, the pull-down termination resistance value is increased, and when the fourth fuse state signal / TM_PDN2 is output at a high level, the pull-down termination resistance value is reduced.

6 is a diagram illustrating a result of trimming termination mismatch by applying the present invention.

Referring to FIG. 6, the graph 610 before trimming the termination mismatch shows that the mismatch was between -6% and + 6%. The graph 620 after trimming shows that the mismatch is -2% to +2. You can see that it decreases between%.

In the above, the termination circuit of the semiconductor device according to the embodiment of the present invention has been described in detail. Although the technical spirit of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above embodiment is for the purpose of description and not of limitation. In addition, it will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

For example, the configuration of Active High or Active Low to indicate the activation of the signal may vary depending on the embodiment. In addition, the configuration of the transistor may be changed as necessary to implement the same function. That is, the configurations of the PMOS transistor and the NMOS transistor may be replaced with each other, and may be implemented using various transistors as necessary. In addition, the number of passive devices and active devices included in the pull-up termination unit and the pull-down termination unit may be configured to be changed as necessary. Such a change in the circuit is too many cases, and the change can be easily inferred by a person skilled in the art, so the enumeration thereof will be omitted.

1 is a circuit diagram of a termination circuit of a semiconductor device of the prior art.

2 is a formula used for measuring termination resistance and termination mismatch.

3 is a diagram for a pull-up termination resistance value and a pull-down termination resistance value.

4 is a termination circuit of a semiconductor device according to an embodiment of the present invention.

5 is a diagram illustrating an example of trimming a termination mismatch using FIG. 4.

6 is a diagram illustrating a result of trimming termination mismatch by applying the present invention.

* Explanation of symbols for the main parts of the drawings

421: pull-up load control unit 422: pull-down load control unit

431: pull-up termination 432: pull-down termination

In the figure, PMOS transistors and NMOS transistors are denoted by MPi and MNi (i = 0, 1, 2, ...), respectively.

Claims (11)

A fuse unit including a plurality of fuses in which termination trimming information is programmed, and outputting a plurality of fuse state signals corresponding to electrical states of each fuse; A termination trimming controller configured to generate a plurality of load control signals in response to a termination test signal and the plurality of fuse state signals; And Termination unit trimming the termination resistance value in response to the plurality of load control signals Termination circuit of a semiconductor device comprising a. The method of claim 1, The termination trimming control unit, A plurality of pull-up load controllers for generating a plurality of pull-up load control signals corresponding to each fuse state signal in response to the termination test signal; And a plurality of pull-down load controllers for generating a plurality of pull-down load control signals corresponding to each fuse state signal in response to the termination test signal. The method of claim 2, Each of the plurality of pull-up load controllers, And a logic sum means for inputting the termination test signal and the corresponding fuse state signal. The method of claim 3, The plurality of pull-up load control unit, And a logic sum means for inputting the termination test signal and a ground voltage. The method of claim 2, The plurality of pull-down load control unit, respectively, And a logical multiplication means for inputting the termination test signal and the corresponding fuse state signal. The method of claim 5, The plurality of pull-down load control unit, And a logical multiplication means for inputting the termination test signal and a power supply voltage. The method of claim 2, The termination part, A pull-up termination part having a plurality of pull-up active rods connected in parallel with each other and activated under the control of the plurality of pull-up load control signals; And a pull-down termination unit having a plurality of pull-down active rods connected in parallel to each other activated under the control of the plurality of pull-down load control signals. The method of claim 7, wherein And the pull-up termination unit further comprises a pull-up termination resistor connected in series with the plurality of pull-up active loads. The method of claim 8, And the pull-down termination unit further comprises a pull-down termination resistor connected in series with the plurality of pull-down active loads. The method of claim 7, wherein And the plurality of pull-up active loads are transistors. The method of claim 10, And the plurality of pull-down active loads are transistors.

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