KR20100018124A - Clock generator and display driver circuit using the same - Google Patents

Abstract

PURPOSE: A clock generator and a display driver circuit using the same are provided to process the held data by generating a clock edge as an output clock after a preset time. CONSTITUTION: A clock detection unit(301) is inputted with the reference clock. The clock detection unit reverses the output signal for a preset time in a state an edge of the reference clock is not generated. An inverter(303) is inputted with the reference clock. The inverter reverses the reference clock. A multiplexer(305) is inputted with the reference clock and the output signal of the inverter. The multiplexer selectively outputs the reference clock or the output signal of the inverter according to the output signal of the clock detection unit.

Description

Clock generator and display driver circuit using the same

The present invention relates to a clock generator and a display driving circuit having the same, and more particularly, to a clock generator for a pipeline technique and a display driving circuit using the same.

In general, if the data throughput on the data path is large and the propagation delay time is long and the write cycle or bandwidth cannot be increased, the pipeline technique can solve the problem.

The pipeline technique is an operation method that starts the execution of another instruction before the execution of one instruction, and divides the operation process into several stages so that each stage overlaps and is executed at the same time. One of the methods of increasing the throughput without increasing the processing speed of the display driving circuit is a special case of parallel processing or simultaneous processing in which several tasks are performed at the same time.

1 illustrates a circuit to which a conventional pipeline technique is applied. Referring to FIG. 1, the entire logic circuit is divided into a first logic circuit 101 and a second logic circuit 105, and an output of each logic circuit is input to the first register 103 or the second register 107. do. The reference clock I_CLK is input to the first register 103 and the second register 107 to control the data output timing of each register. As described above, the circuit to which the pipeline technique is applied can perform operations simultaneously in the first logic circuit and the second logic circuit, so that the data throughput of the circuit is higher than before the pipeline technique is applied.

On the other hand, the host interface of the display driver circuit does not guarantee continuous clock input. Therefore, when a pipeline technique is used in the data path in a system receiving such a clock, there is a problem in that a subsequent clock is not inputted so that data may be held and remain unprocessed.

FIG. 2 is a time series illustrating an example in which data is held and remains unprocessed in a circuit to which a conventional pipeline technique is applied. Referring to FIG. 2, when the reference clock I_CLK is the nth cycle (Cycle n), D (n) is input to the input data DATA, and the n + 1th cycle (Cycle n), which is the next cycle of the nth cycle, is input. D (n + 1) is input as the input data DATA when +1), and D as the input data DATA when the n + 2th cycle (Cycle n + 2) which is the next period of the n + 1th cycle. (n + 2) is input.

Referring to FIG. 2, the data transfer process in each cycle is performed. After D (n) input as the input data DATA in the nth cycle Cycle n, the data processing process of the first logic circuit 101 is performed. When the n + 1 th cycle (Cycle n + 1), which is the next period, is stored in the first register 103 as D1 (n). D1 (n) means data output after D (n) has undergone a data processing of the first logic circuit 101. In a similar manner, D (n + 1) and D (n + 2) input as input data DATA are also transferred to the first register 103. In a similar manner, D1 (n) and D1 (n + 1) of the first register 103 are also transferred to the second register 107 after the data processing of the second logic circuit 105 is performed.

However, as shown in FIG. 2, since no subsequent clock is input after the n + 2th cycle n + 2, D1 (n + 2) stored in the first register 103 is the second register 107. ) Is held in the first register and remains unprocessed.

As described above, when the pipeline technique is applied to the data path in a system in which continuous clock input is not guaranteed, there is a problem in that the subsequent clock is not input and the data may be held and remain unprocessed.

An object of the present invention is to provide a clock generator and a display driving circuit using the same which can prevent a problem of data being held between pipeline stages.

In order to achieve the above object, the clock generator according to an embodiment of the present invention, the clock for inverting the output signal when the edge of the reference clock does not occur for a predetermined time to receive the reference clock A detection unit, an inverter that receives the reference clock and inverts the reference clock, and outputs the output signal of the reference clock and the inverter, and receives the reference clock and an output signal of the inverter according to the output signal of the clock detector. It characterized in that it comprises a multiplexer for selectively outputting the.

Preferably, the clock detector may invert the output signal when the edge of the reference clock does not occur for a period longer than the period of the reference clock.

In addition, when the edge of the reference clock occurs within the preset time, the clock detector generates an output signal having a first level, and when the edge of the reference clock does not occur during the preset time. Generates an output signal having a second level, and the multiplexer outputs the reference clock when the output signal of the clock detector is the first level, and outputs the reference clock when the output signal of the clock detector is the second level. It is preferable to output the output signal of.

The clock generator according to another embodiment of the present invention receives a first input signal, detects whether the first input signal maintains a logic high for a predetermined first time or more, and generates a first control signal according to the detection result. A first clock detector for generating a second input signal and a second input signal, detecting whether the second input signal maintains a logic low for a preset second time, and generating a second control signal according to the detection result; A second clock detector, a first multiplexer configured to receive the first input signal and the logic low signal and selectively output the first input signal or the logic low signal in response to the first control signal, and the second input A second multiplexer configured to receive a signal and a logic high signal and selectively output the second input signal or the logic high signal in response to the second control signal; It is characterized by.

Preferably, when the first input signal is a reference clock, the second clock detector and the second multiplexer receive the output of the first multiplexer as the second input signal, and the second input signal is the second input signal. In the case of a reference clock, the first clock detector and the first multiplexer may receive an output of the second multiplexer as the first input signal.

The output signal of the first multiplexer or the output signal of the second multiplexer may be output to the outside.

In addition, the first clock detector and the second clock detector receive a third control signal, and the first clock detector outputs a first input signal by the first multiplexer in response to the activation of the third control signal. The second clock detector may control the second multiplexer to output the second input signal in response to the activation of the third control signal.

Preferably, the first clock detector includes M delay parts (M is a natural number), and each of the M delay parts includes a buffer for delaying and outputting a signal input to each of the delay parts, and an output of the buffer. And an AND gate configured to receive and output a signal and the first input signal, wherein a buffer of the first delay unit receives the first input signal, and an Nth delay unit (N is a natural number smaller than or equal to M and larger than 1). The input terminal of the buffer may be connected to the output terminal of the AND gate of the N−1th delay unit, and the AND gate of the Mth delay unit may output the first control signal.

The buffer of each of the delay units preferably has a delay time smaller than the pulse width of the first input signal.

Preferably, the second clock detector includes M delay parts (M is a natural number), and each of the M delay parts includes a buffer for delaying and outputting a signal input to each of the delay parts, and an output of the buffer. And an OR gate for receiving and outputting a signal and the second input signal, wherein a buffer of the first delay unit receives the second input signal, and an Nth delay unit (N is a natural number smaller than or equal to M and larger than 1). The input terminal of the buffer may be connected to the output terminal of the OR gate of the N-th delay unit, and the OR gate of the M-th delay unit may output the second control signal.

The buffer of each of the delay units preferably has a delay time smaller than the pulse width of the second input signal.

Meanwhile, the display driving circuit according to an embodiment of the present invention receives predetermined data and a reference clock, receives a first register controlled by the reference clock, and the reference clock, and controls the reference clock for a predetermined time. If no edge occurs, a clock detector for inverting an output signal, an inverter for receiving the reference clock and inverting the reference clock for output, and a clock detector for receiving the reference clock and an output signal of the inverter A clock generator having a multiplexer for selectively outputting the reference clock or the output signal of the inverter according to an output signal of the input signal, and receiving data from the first register, an output clock of the clock generator, and receiving the output clock. And a second register controlled by the control unit.

Preferably, the clock detector may invert the output signal of the clock detector when the edge of the reference clock does not occur for a period longer than the period of the reference clock.

The clock generator and the display driving circuit using the same according to the present invention as described above have an effect of stably processing data by preventing data from being held between pipeline stages.

DETAILED DESCRIPTION In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings that illustrate preferred embodiments of the present invention.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals in the drawings denote like elements.

3 is a block diagram illustrating a clock generator according to an exemplary embodiment of the present invention. As illustrated, the clock generator 300 includes a clock detector 301, a multiplexer 305, and an inverter 303, and a reference clock I_CLK input from an external source is the clock detector 301 and the multiplexer 305. And an inverter 303. The clock detector 301 detects whether an edge of the reference clock I_CLK occurs for a predetermined time, and generates an output signal Con accordingly. Preferably, the level of the output signal when the edge of the reference clock I_CLK occurs and the output signal when the edge of the reference clock I_CLK does not occur within a predetermined time period are reversed. For example, when an edge of the reference clock I_CLK occurs for a predetermined time, the clock detector 301 outputs the output signal Con to have a first level, and outputs the reference clock I_CLK for a predetermined time. If no edge is generated, the output signal Con may be inverted to have the second level. The first level signal and the second level signal may be any one of a logic low signal and a logic high signal and are different signals.

The predetermined time of the clock detector 301 may be set to be longer than a period of the reference clock I_CLK. In this case, the clock detector 301 may detect whether an edge of the reference clock I_CLK occurs for a time longer than a period of the reference clock I_CLK. In addition, the edge detected by the clock detector 301 may be at least one of a rising edge or a falling edge.

The inverter 303 receives the reference clock I_CLK and inverts and outputs the reference clock I_CLK. The multiplexer 305 receives the reference clock I_CLK and the output signal of the inverter 303, and selectively selects the output signal of the reference clock I_CLK or the inverter 303 according to the output signal Con of the clock detector 301. Will output For example, the multiplexer 305 outputs the reference clock I_CLK when the output signal Con of the clock detector 301 is at the first level, and outputs the reference signal I_CLK when the output signal Con of the clock detector 301 is at the second level. The output signal of the inverter 303 can be output.

A detailed operation of the clock generator illustrated in FIG. 3 will now be described with reference to FIG. 4.

4 illustrates a timing diagram of the reference clock I_CLK, the output signal Con of the clock detector, and the output clock O_CLK. 4 illustrates that the clock detector 301 detects a rising edge, the first level corresponds to a logic low, the second level corresponds to a logic high, and the multiplexer 305 outputs the output signal Con of the clock detector 301. Is a logic low signal, the reference clock I_CLK is output, and when the output signal Con of the clock detector 301 is a logic high signal, the embodiment outputs the output signal of the inverter 303. Ts represents a preset time of the clock detector 301.

Referring to FIG. 4, since the rising edge of the reference clock I_CLK occurs within a preset time of the clock detector 301, the output signal Con of the clock detector 301 remains logic low before t1. do. When the output signal Con of the clock detector 301 is a logic low signal, the multiplexer 305 outputs the reference clock I_CLK, so the output clock O_CLK has the same waveform as the reference clock I_CLK.

If the preset time Ts of the clock detector 301 is equal to t2-t1, since the rising edge of the reference clock I_CLK has not occurred from t1 to t2 since t1 has passed, the clock detector 301 when t2 is reached. The output signal Con is inverted from the logic low signal to the logic high signal. When the output signal Con of the clock detector 301 changes to a logic high signal, the multiplexer 305 outputs the output signal of the inverter 303 inverting the reference clock I_CLK, so the output clock O_CLK is at t2. This is a logic high signal.

When a time elapses to t3 and a rising edge of the reference clock I_CLK occurs, the clock detector 301 outputs a logic low signal. When the output signal Con of the clock detector 301, which is a logic low signal, is input to the multiplexer 305, the multiplexer 305 outputs the reference clock I_CLK, so after t3, the reference clock I_CLK and the output clock ( O_CLK) shows the same waveform.

When the waveforms of the reference clock I_CLK and the output clock O_CLK are compared with reference to FIG. 4, the output clock O_CLK corresponds to t1 and t2 when the rising edge occurs at the t1 and t3 of the reference clock I_CLK. Rising edge occurs at. That is, the output clock O_CLK is generated by advancing the rising edge of the input clock I_CLK generated at t3 to t2.

2 and 4, even after the clock of t1 occurs, data held in the register exists. When the reference clock I_CLK is input to the register, the held data cannot be processed until t3. However, when the output clock O_CLK is input to the register, the held data can be processed at the time t2 before t3.

5 is a block diagram illustrating a clock generator according to another exemplary embodiment of the present invention. As illustrated, the clock generator 500 includes a first clock detector 501, a second clock detector 505, a first multiplexer 503, and a second multiplexer 507. The first clock detector 501 receives a first input signal IN_1, detects whether the first input signal IN_1 maintains a logic high for a preset first time, and controls the first control signal according to the detection result. Generate the signal Con_1. Preferably, the first input signal IN_1 may be a reference clock I_CLK. The second clock detector 505 receives the second input signal IN_2, detects whether the second input signal IN_2 maintains a logic low for a preset second time, and controls the second control signal according to the detection result. Generate the signal Con_2. Preferably, the second input signal IN_2 may be an output signal of the first multiplexer 503.

The first time and the second time may be set to a time longer than a period of the reference clock I_CLK. In this case, the first clock detector 501 detects whether the first input signal IN_1 maintains a logic high for a time longer than a period of the reference clock I_CLK, and the second clock detector 505 determines the reference clock. It may be detected whether the second input signal IN_2 maintains a logic low for a time longer than the period of I_CLK.

According to one embodiment of the first clock detector 501 and the second clock detector 505 applied to the present invention, the first clock detector 501 maintains the first input signal IN_1 at a logic high for a first time or more. Output the first control signal Con_1 that is logic high, and outputs the first control signal Con_1 that is logic low if the first input signal IN_1 becomes logic low or does not remain logic high for more than a first time. Can be. In addition, when the second input signal IN_2 is maintained at a logic low for a second time or more, the second clock detector 505 outputs a second control signal Con_2 that is a logic low, and the second input signal IN_2 is logic. If it is high or is not maintained at a logic low for more than a second time, the second control signal Con_2 that is a logic high can be output.

Meanwhile, the first multiplexer 503 receives the first input signal IN_1 and a logic low signal (eg, logic “0”) in response to the first control signal Con_1 in response to the first input signal ( IN_1) or selectively outputs the logic low signal. In addition, the second multiplexer 507 receives the second input signal IN_2 and a logic high signal (eg, logic “1”) in response to the second control signal Con_2 in response to the second input signal ( IN_2) or the logic high signal is selectively output.

According to one embodiment of the first multiplexer 503 and the second multiplexer 507 applied to the present invention, the first multiplexer 503 is the first input signal IN_1 when the first control signal Con_1 is logic low. And a logic low signal when the first control signal Con_1 is logic high. In addition, the second multiplexer 507 may output a second input signal IN_2 when the second control signal Con_2 is logic high, and output a logic high signal when the second control signal Con_2 is logic low. .

The clock generator 500 may output at least one of an output signal of the first multiplexer 503 or an output signal of the second multiplexer 507 to the outside. As an example, when the output of the first multiplexer 503 is provided as an input of the second multiplexer 507, the output of the second multiplexer 507 may be provided to the outside as an output clock O_CLK.

The third control signal Con_3 is a signal for controlling the reference clock I_CLK and the output clock O_CLK to have the same waveform. The third control signal Con_3 is input to the first clock detector 501 and the second clock detector 505 from the outside. Can be. In response to the activation of the third control signal Con_3, the first clock detector 501 controls the first multiplexer 503 to output the first input signal IN_1 regardless of a clock detection result. The second clock detector 505 controls the second multiplexer 507 to output the second input signal IN_2 regardless of the clock detection result. Therefore, when the third control signal Con_3 is activated, the reference clock I_CLK is output to the output clock O_CLK as it is through the first multiplexer 503 and the second multiplexer 507.

Meanwhile, as shown in FIG. 5, in the clock generator according to the exemplary embodiment, the first input signal IN_1 is the reference clock I_CLK, and the second input signal IN_2 is the first multiplexer 503. It may be an output signal. Although not shown, the clock generator may be implemented such that the second input signal IN_2 is the reference clock I_CLK, and the first input signal IN_1 is an output signal of the second multiplexer 507.

Meanwhile, although only two clock detectors and two multiplexers are shown in FIG. 5, the clock generator may be implemented by two or more clock detectors and two or more multiplexers.

A detailed operation of the clock generator 500 illustrated in FIG. 5 will now be described with reference to FIG. 6.

FIG. 6 is a timing diagram of the reference clock I_CLK, the first control signal Con_1, the second input signal IN_2, the second control signal Con_2, and the output clock O_CLK shown in FIG. It is shown.

The timing diagram shown in FIG. 6 relates to an embodiment of the clock generator 500 shown in FIG. 5, and the operation of the clock generator 500 is as follows. The first clock detector 501 outputs a first control signal Con_1 that is a logic high when the first input signal IN_1 maintains a logic high for a first time Ts1 or more, and the first input signal IN_1 When the logic low level or the logic high level is not maintained for more than the first time Ts1, the first control signal Con_1 that is a logic low is output. In addition, when the second input signal IN_2 maintains a logic low for more than a second time Ts2, the second clock detector 505 outputs a second control signal Con_2 that is a logic low, and the second input signal IN_2. ) Becomes logic high or does not remain logic low for more than the second time Ts2, outputting the second control signal Con_2 that is logic high. The first multiplexer 503 outputs a first input signal IN_1 when the first control signal Con_1 is logic low, and outputs a logic low signal when the first control signal Con_1 is logic high. The second multiplexer 507 outputs a second input signal IN_2 when the second control signal Con_2 is logic high, and outputs a logic high signal when the second control signal Con_2 is logic low.

Referring to FIG. 6, Ts1 represents a preset first time of the first clock detector 501 and Ts2 represents a preset second time of the second clock detector 505. Since the reference clock I_CLK is not held at logic high for more than the first time Ts1 before t1 and the edge of the reference clock I_CLK occurs continuously within the first time Ts1, the first clock detector 501 outputs a first control signal Con_1 that is a logic low. Accordingly, since the first multiplexer 503 that receives the first control signal Con_1 that is a logic low outputs the reference clock I_CLK, the second input signal IN_2 is connected to the reference clock I_CLK in the period before t1. The same waveform is displayed. The second clock detector 505 receives the second input signal IN_2, and before t1, the second input signal IN_2 is not maintained at a logic low for more than the second time Ts2, and the second time Ts2 is not applied. Since the edge of the second input signal IN_2 continues within the second clock detector 505, the second clock signal 505 outputs the second control signal Con_2 that is logic high in the period before t1. Accordingly, since the second multiplexer 507, which receives the second control signal Con_2 that is logic high, outputs the second input signal IN_2, the output clock O_CLK is the second input signal IN_2 in the period before t1. Will show a waveform like).

When the preset first time Ts1 of the first clock detector 501 is equal to t2-t1, since the reference clock I_CLK is kept at a logic high from t1 to t2 after t1 passes, the first clock when t2 is reached. The first control signal Con_1, which is an output signal of the detector 501, becomes a logic high state. When the first control signal Con_1 is in the logic high state at t2, the first multiplexer 503 outputs the logic low signal, and thus the second input signal IN_2 is in the logic low state.

The second clock detector 505 detects whether the second input signal IN_2 is held at a logic low for more than the second time Ts2, and before t2, the second input signal IN_2 is equal to or longer than the second time Ts2. The second control signal Con_2, which is an output signal of the second clock detector 505, maintains a logic high state because it is not maintained at the phase logic low. Therefore, since the second multiplexer 507 receiving the second control signal Con_2 that is logic high outputs the second input signal IN_2, the waveforms of the second input signal IN_2 and the output clock O_CLK are not generated until t2. Become equal to each other.

When the preset second time Ts2 of the second clock detector 505 is equal to t3-t2, since the second input signal IN_2 is maintained at a logic low from t2 to t3 after t2 passes, The second control signal Con_2, which is an output signal of the two clock detector 505, is in a logic low state. When the second control signal Con_2 is in the logic low state at t3, the second multiplexer 507 outputs the logic high signal, so the output clock O_CLK is in the logic high state.

When the reference clock I_CLK becomes a logic low at t4, the first clock detector 501 outputs a first control signal Con_1 that is a logic low. Accordingly, when the first control signal Con_1 that is a logic low is input to the first multiplexer 503, the first multiplexer 503 outputs the reference clock I_CLK. Therefore, after t4, the second input signal IN_2 is It has the same waveform as the reference clock I_CLK.

When the second input signal IN_2 becomes logic high at t5, the second clock detector 505 outputs the second control signal Con_2 that is logic high. Accordingly, when the second control signal Con_2 that is logic high is input to the second multiplexer 507, the second multiplexer 507 outputs the second input signal IN_2. Therefore, after t5, the output clock O_CLK is It has the same waveform as the second input signal IN_2.

When the waveforms of the reference clock I_CLK and the output clock O_CLK are compared with reference to FIG. 6, the output clock O_CLK corresponds to t1 and t3 when the rising edge occurs at the t1 and t5 of the reference clock I_CLK. Rising edge occurs at. That is, the output clock O_CLK is generated by advancing the rising edge of the input clock I_CLK generated at t5 to t3.

2 and 6, data held in a register exists even after the clock of t1 occurs. When the reference clock I_CLK is input to the register, the held data cannot be processed until t5. However, when the output clock O_CLK is input to the register, the held data can be processed at the time t3 before t5.

FIG. 7 is a block diagram illustrating an embodiment of the first clock detector 501 of FIG. 5. An embodiment of the first clock detector 501 shown in FIG. 7 may include a plurality of delay units (for example, three delay units 701, 711, and 721), and each delay unit may include a buffer 703 and 713. , 723, and AND gates 705, 715, and 725. The buffer 703 of the first delay unit 701 receives the first input signal IN_1 and delays it and outputs the delay. The AND gate 705 of the first delay unit 701 outputs the output signal of the buffer 703. And an AND operation after receiving the first input signal IN_1 and outputting the same.

The three delay units 701, 711, and 721 are connected in series with each other, and the output of the AND gate 705 of the first delay unit 701 is input to the buffer 713 of the second delay unit 711. The output of the AND gate 615 of the second delay unit 711 is input to the buffer 723 of the third delay unit 721. The output of the AND gate 725 of the third delay unit 721 is output as the first control signal Con_1.

The sum of the delay times of the respective buffers 703, 713, and 723 may be the first time Ts1 of the first clock detector 501. The buffers 703, 713, and 723 of each of the three delay units 701, 711, and 721 may have a delay time smaller than the pulse width of the first input signal IN_1. This is to ensure that pulses having a pulse width shorter than the delay time of each buffer do not remain as alternating current (AC) components inside the delay unit.

FIG. 8 is a block diagram illustrating an exemplary embodiment of the second clock detector 505 of FIG. 5. An embodiment of the second clock detector 505 shown in FIG. 8 may include a plurality of delay units (for example, three delay units; 801, 811, and 821), and each delay unit may include buffers 803 and 813. 823 and OR gates 805, 815, and 825. The buffer 803 of the first delay unit 801 receives the second input signal IN_2 and delays it and outputs the delay. The OR gate 805 of the first delay unit 801 outputs the output signal of the buffer 803. And OR operation after receiving the second input signal IN_2 and outputting the OR operation.

The three delay units 801, 811, 821 are connected in series with each other, and the output of the OR gate 805 of the first delay unit 801 is input to the buffer 813 of the second delay unit 811. The output of the OR gate 815 of the second delay unit 811 is input to the buffer 823 of the third delay unit 821. The output of the OR gate 825 of the third delay unit 821 is output as the second control signal Con_2.

The sum of the delay times of the respective buffers 803, 813, and 823 may be the second time Ts2 of the second clock detector 505. The buffers 803, 813, 823 of each of the three delay units 801, 811, and 821 may have a delay time smaller than the pulse width of the second input signal IN_2. This is to ensure that pulses having a pulse width shorter than the delay time of each buffer do not remain as alternating current (AC) components inside the delay unit.

9 is a block diagram illustrating an embodiment of a display driving circuit including a clock generator according to an embodiment of the present invention. The display driving circuit 900 includes a first register 920, a second register 940, and a clock generator 950. The first register 920 receives the input data DATA and the reference clock I_CLK, and the second register 940 receives the data from the first register 920 and outputs the clock of the clock generator 950. O_CLK) is input. The clock generator 950 receives the reference clock I_CLK and generates an output clock O_CLK. The display driving circuit 900 receives the input data DATA, processes the same, and then outputs the result to the first register 920, and the first register 920. After receiving the data from the process and processing it, it may further include a second logic circuit 930 for outputting the result to the second register (940). In addition, the clock generator 950 of FIG. 9 may be implemented as one embodiment of the clock generator 300 shown in FIG. 3 or one embodiment of the clock generator 500 shown in FIG. 5.

FIG. 10 is a time-series diagram of an embodiment of a specific operation of the display driving circuit shown in FIG. 9. Referring to FIG. 10, since the edge of the reference clock I_CLK occurs from the nth cycle (Cycle n) to the n + 2th cycle (Cycle n + 2), the clock generator as shown in FIGS. 4 and 6. The output clock O_CLK of 950 becomes equal to the reference clock I_CLK.

Referring to the data transfer process in each cycle in FIG. 10, the input data DATA is stored in the first register 920 after the data processing process of the first logic circuit 910 is performed. When the reference clock I_CLK is the nth cycle (Cycle n), D (n) is stored in the first register 920, and when the n + 1th cycle (Cycle n + 1) is the next period of the nth cycle. D (n + 1) is stored in the first register 920, and D (n +) is stored in the first register 920 when the n + 2 th cycle (Cycle n + 2) is the next period of the n + 1 th cycle. 2) is stored.

D (n) stored in the first register 920 in the nth cycle (Cycle n) is D1 (n) in the second register 940 in the n + 1th cycle (Cycle n + 1), the next period. Stored as. D1 (n) means data output after D (n) has undergone data processing of the second logic circuit 930. In a similar manner, D (n + 1) and D (n + 2) stored in the first register 920 are also passed to the second register 940.

However, as shown in FIG. 10, since no subsequent clock is input after the n + 2th cycle n + 2, D1 (n + 2) stored in the second register 940 is not transferred to the next register. And it is held in the second register 940 and is not processed. When the input of the reference clock I_CLK is stopped and there is no change in the signal level of the reference clock I_CLK, the clock generator 950 generates a clock edge when a predetermined time elapses as described above, thereby outputting the output clock O_CLK. ) Therefore, D1 (n + 2) held in the second register 940 receives the output clock O_CLK and transfers it to the next register. That is, as described above, the clock generator 950 generates a clock edge with the output clock O_CLK after the input of the reference clock I_CLK stops to process the held data. .

As described above, optimal embodiments have been disclosed in the drawings and the specification. Although specific terms have been used herein, they are used only for the purpose of describing the present invention and are not intended to limit the scope of the invention as defined in the claims or the claims. Therefore, those skilled in the art will understand that various modifications and equivalent other embodiments are possible. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

1 illustrates a circuit to which a conventional pipeline technique is applied.

FIG. 2 illustrates a case where data is held and remains unprocessed in a circuit to which the conventional pipeline technique is applied.

3 is a block diagram illustrating a clock generator according to an exemplary embodiment of the present invention.

4 shows a timing diagram of a reference clock, an output signal of a clock detector, and an output clock.

5 is a block diagram illustrating a clock generator according to another exemplary embodiment of the present invention.

FIG. 6 illustrates a timing diagram of the reference clock, the first control signal, the second input signal, the second control signal, and the output clock shown in FIG. 5.

FIG. 7 is a block diagram illustrating an exemplary embodiment of the first clock detector illustrated in FIG. 5.

FIG. 8 is a block diagram illustrating an exemplary embodiment of the second clock detector illustrated in FIG. 5.

9 is a block diagram illustrating an embodiment of a display driving circuit including a clock generator according to an embodiment of the present invention.

FIG. 10 is a time-series diagram of an embodiment of a specific operation of the display driving circuit shown in FIG. 9.

Explanation of symbols on the main parts of the drawings

301: clock detector 303: inverter

305: multiplexer 501: first clock detector

503: First multiplexer 505: Second clock detector

507: second multiplexer

Claims (13)

A clock detector that receives a reference clock and inverts an output signal when an edge of the reference clock does not occur for a preset time; An inverter receiving the reference clock and inverting the reference clock to output the reference clock; And And a multiplexer configured to receive the reference clock and the output signal of the inverter and selectively output the reference clock or the output signal of the inverter according to the output signal of the clock detector. The method of claim 1, wherein the clock detector, And inverting the output signal when the edge of the reference clock has not occurred for a period longer than the period of the reference clock. The method of claim 1, The clock detector generates an output signal having a first level when an edge of the reference clock occurs within the preset time, and generates an output signal having an edge of the reference clock during the preset time. Generates an output signal with two levels, The multiplexer outputs the reference clock when the output signal of the clock detector is the first level, and outputs the output signal of the inverter when the output signal of the clock detector is the second level. generator. A first clock detector configured to receive a first input signal, detect whether the first input signal maintains a logic high for a preset first time, and generate a first control signal according to the detection result; A second clock detector configured to receive a second input signal, detect whether the second input signal maintains a logic low for a preset second time, and generate a second control signal according to the detection result; A first multiplexer which receives the first input signal and the logic low signal and selectively outputs the first input signal or the logic low signal in response to the first control signal; And And a second multiplexer configured to receive the second input signal and the logic high signal and selectively output the second input signal or the logic high signal in response to the second control signal. ). The method of claim 4, wherein When the first input signal is a reference clock, the second clock detector and the second multiplexer receive the output of the first multiplexer as the second input signal. And when the second input signal is the reference clock, the first clock detector and the first multiplexer receive the output of the second multiplexer as the first input signal. The method of claim 4, wherein And an output signal of the first multiplexer or an output signal of the second multiplexer to the outside. The method of claim 4, wherein The first clock detector and the second clock detector receive a third control signal; The first clock detector controls the first multiplexer to output a first input signal in response to activation of the third control signal. And the second clock detector controls the second multiplexer to output a second input signal in response to activation of the third control signal. The method of claim 4, wherein The first clock detector includes M delay parts (M is a natural number), Each of the M delay units includes a buffer for delaying and outputting a signal input to each of the delay units, and an AND gate for receiving and outputting an output signal of the buffer and the first input signal, The buffer of the first delay unit receives the first input signal, and the input terminal of the buffer of the Nth delay unit (N is a natural number smaller than or equal to M and larger than 1) is connected to the output terminal of the AND gate of the N-1 delay unit. And the AND gate of the Mth delay unit outputs the first control signal. The method of claim 8, Each buffer of the delay unit has a delay time less than the pulse width of the first input signal. The method of claim 4, wherein The second clock detector includes M delay parts (M is a natural number), Each of the M delay units includes a buffer for delaying and outputting a signal input to each of the delay units, and an OR gate for receiving and outputting an output signal of the buffer and the second input signal, The buffer of the first delay unit receives the second input signal, and the input terminal of the buffer of the Nth delay unit (N is a natural number smaller than or equal to M and larger than 1) is connected to the output terminal of the OR gate of the N-1 delay unit. And the OR gate of the Mth delay unit outputs the second control signal. The method of claim 10, Each buffer of the delay unit has a delay time smaller than the pulse width of the second input signal. A first register receiving a predetermined data and a reference clock and controlled by the reference clock; A clock detector for inverting an output signal when an edge of the reference clock is not generated for a predetermined time after receiving the reference clock, an inverter for receiving the reference clock and inverting the reference clock and outputting the reference clock; A clock generator having a reference clock and an output signal of the inverter and a multiplexer configured to selectively output the reference clock or the output signal of the inverter according to the output signal of the clock detector; And And a second register receiving data from the first register, an output clock of the clock generator, and a second register controlled by the output clock. The method of claim 12, wherein the clock detector, And inverting the output signal when the edge of the reference clock does not occur for a period longer than the period of the reference clock.

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