KR100674921B1 - A sampling block and sampling method for digital data - Google Patents

Abstract

Disclosed are a digital data sampling block and sampling method in which data latency is significantly reduced when sampling externally input digital data. The digital data sampling block includes a data capture block, an external clock capture block, and a multiplexer. The data capture block samples the external digital data by using the inverted second clock signal in which the phase of the second clock signal and the second clock signal are inverted. The external clock capture block outputs a control signal using information on the phase difference between the first clock signal and the second clock signal. The multiplexer selects and outputs output data of the data capture block according to the control signal. The digital sampling method includes an external digital data capture step, an external clock capture step, and a multiplexing step.

Digital data sampling, data capture, clock capture

Description

A sampling block and sampling method for digital data}

BRIEF DESCRIPTION OF THE DRAWINGS In order to better understand the drawings cited in the detailed description of the invention, a brief description of each drawing is provided.

FIG. 1 illustrates a case where a sampling problem does not occur among the relationship between digital data input from the outside, an internal clock signal sampling the same, and detected data.

2 illustrates a case where a problem occurs in sampling among the relationship between digital data input from the outside, an internal clock signal sampling the same, and detected data.

3 is a block diagram of a digital data sampling block according to an embodiment of the present invention.

4 shows a relationship between an external clock, input data, and an internal clock.

FIG. 5 is a clock pulse diagram when a trigger edge of a plurality of delay clocks having a predetermined time delay of an internal clock Internal_CLK exists in a first section of an external clock External_CLK.

FIG. 6 is a clock pulse diagram when a trigger edge of a plurality of delay clocks having a predetermined time delay of an internal clock Internal_CLK exists in a second section of an external clock External_CLK.

The present invention relates to a digital signal processing system, and more particularly, to a digital signal processing system having a digital data sampling block capable of changing the phase of a clock signal used to sample input data.

The digital signal processing system recognizes digital data input from the outside by using an internal sampling clock signal and stores or uses the same.

The digital signal processing system transmits and receives the digital data from other external function blocks. The digital signal processing system and the function blocks may operate using the same master clock, but generally the master Divide the clock to the required frequency and use it. Therefore, the frequency of the clock used by the digital signal processing system and the functional blocks is often different. Although the frequency of the clock used by the digital signal processing system and the functional blocks is the same, the phases are usually different.

Therefore, the digital data generated corresponding to the clock signal having a predetermined frequency in one functional block is sampled by the clock signal of the same frequency when used in another functional block or the digital signal processing system. Even if there is a disadvantage that the wrong data can be sampled by the phase difference.

In order to prevent this, conventionally, the digital data is converted and used with a predetermined reference by using the concept of FIFO (First Input First Output). In this case, there is a disadvantage that the latency becomes long.

FIG. 1 illustrates a case where a sampling problem does not occur among the relationship between digital data input from the outside, an internal clock signal sampling the same, and detected data.

Referring to FIG. 1, externally input data (IN) streams are 2FA and 105, respectively, and the data are sampled at a trigger edge of an internal clock signal. Therefore, it can be seen that the output data OUT is accurately sampled after a predetermined delay time has elapsed.

2 illustrates a case where a problem occurs in sampling among the relationship between digital data input from the outside, an internal clock signal sampling the same, and detected data.

Referring to FIG. 2, since the trigger edge of the internal clock signal is located between two consecutive data, a problem occurs in sampling, and the output data OUT cannot be predicted.

Since the digital data input from the outside cannot be known in phase, it is impossible to sample using a clock signal that is exactly matched internally. Therefore, in order to use external data in an internal circuit, some data modification must be applied. In order to modify external data, it is common to use a first input first output (FIFO) method and apply this concept to a register. However, the method of using the registers requires a large area to implement the registers, and the registers are not low in power consumption and cause the system to increase the latency.

A new method for overcoming this has been proposed as a patent in Korea. (Application No. 2002-0052107) However, the present invention does not completely overcome the drawback of the long delay time due to the use of a memory, a write-only data counter, a register, and the like. I couldn't.

An object of the present invention is to provide a digital data sampling block in which data latency is significantly reduced when sampling digital data input from the outside.

Another object of the present invention is to provide a digital data sampling method in which a data delay time is significantly reduced when sampling externally input digital data.

The digital data sampling block according to the present invention for achieving the above technical problem, samples the external digital data loaded according to the first clock signal using the second clock signal.

The digital data sampling block includes a data capture block, an external clock capture block, and a multiplexer.

The data capture block samples the external digital data by using the inverted second clock signal in which the phase of the second clock signal and the second clock signal are inverted. The external clock capture block outputs a control signal using information on the phase difference between the first clock signal and the second clock signal. The multiplexer selects and outputs output data of the data capture block according to the control signal.

According to another aspect of the present invention, there is provided a digital data sampling method, wherein external digital data loaded according to a first clock signal is sampled using a second clock signal.

The digital data sampling method includes an external digital data capture step, an external clock capture step, and a multiplexing step.

In the external digital data capturing step, the external digital data is sampled by using the inverted second clock signal in which the phase of the second clock signal and the second clock signal are inverted. In the external clock capture step, a control signal is output using information on the phase difference between the first clock signal and the second clock signal. The multiplexing step selects and outputs output data of the data capturing step according to the control signal.

DETAILED DESCRIPTION In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings that illustrate preferred embodiments of the present invention.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals in the drawings denote like elements.

3 is a block diagram of a digital data sampling block according to an embodiment of the present invention.

Referring to FIG. 3, the digital data sampling block includes a data capture block 310, an external clock capture block 320, and a multiplexer 360.

The data capture block 310 samples the external digital data using the second clock signal CLK2 and the inverted second clock signal CLK2B in which the phases of the second clock signal are inverted. The external clock capture block 320 outputs the control signal CNTL using information on the phase difference between the first clock signal CLK1 and the second clock signal CLK2. The multiplexer 360 selects and outputs output data DS1 and DS1B of the data capture block 310 in accordance with the control signal CNTL.

The data capture block 310 includes a clock signal reversing apparatus 311, a first sampling block 313, and a second sampling block 315.

The clock signal reversing apparatus 311 outputs the inverted second clock signal CLK2B in which the phase of the second clock signal CLK2 is reversed by 180 degrees. The clock signal reversing apparatus 311 is preferably an inverter that is supplied with the second clock signal CLK2 to the input terminal and outputs the second clock signal CLK2B inverted by the output terminal. The first sampling block 313 samples the external digital data D using the second clock signal CLK2 and outputs the output DS1. The second sampling block 315 samples the external digital data D using the inverted second clock signal CLK2B and outputs the result DS1B.

The external clock capture block 320 includes a delay clock generator 330, an external clock sampling block 340, and a comparator 350.

The delay clock generator 330 generates delayed second clock signals by delaying the second clock signal CLK2 and the second clock signal by at least two different delay times, and for this purpose, the first delay device 331. ), A second delay unit 333 and an N-th delay unit 335.

The first delay device 331 outputs the first delay clock DLY1 having the smallest delay time with respect to the second clock signal CLK2. The second delay device 333 outputs a second delay clock DLY2 having a delay time with respect to the second clock signal CLK2 greater than the first delay clock. The Nth delay device 335 outputs an Nth delay clock whose delay time for the second clock signal DLYN is greater than the (N-1) th delay clock. Where N is an integer.

The external clock sampling block 340 samples the first clock signal CLK1 using the plurality of delay clocks DLY1, DLY2, and DLYN, and for this purpose, the third sampling block 341 and the fourth sampling block. 433 and a (N + 2) th sampling block 345.

The third sampling block 341 samples the first clock signal CLK1 using the first delay clock DLY1. The fourth sampling block 433 samples the first clock signal CLK1 using the second delay clock DLY2. The (N + 2) sampling block 345 samples the first clock signal CLK1 using the Nth delay clock DLYN. Herein, the third sampling block to the (N + 2) s sampling block is operated in response to the first clock signal CLK1 to the input terminal and responds to the first delay clocks DLY1 to N-th delay signal DLYN. It is preferably a D flip-flop.

The comparison analyzer 350 compares and analyzes output data of the external clock sampling block 340 and outputs a control signal CNTL. The control signal CNTL has a first logic value when all the values of the output data of the external clock sampling block 340 are the same, and a second logic value when all the values are not the same. Here, the first logic value and the second logic value have different voltage levels.

The multiplexer 360 outputs the data DS1 sampled corresponding to the second clock signal CLK2 when the control signal CNTL is the first logical value, and when the control signal CNTL is the second logical value. The sampled data DS1B is output in response to the inverted second clock signal CLK2B.

Hereinafter, an operation principle of a digital data sampling block according to an embodiment of the present invention shown in FIG. 3 will be described.

4 shows a relationship between an external clock, input data, and an internal clock.

Referring to FIG. 4, the logic high state and the logic low state of the external clock External_CLK are divided into two sections ① and ②, and one data IN is available in one cycle of the external clock. Can be. The time of each section is, for example, 0.5 ns (nano seconds) for the first section ① and 1.5 ns for the second section ②.

According to the basic idea of the present invention, if the trigger edge (arrow) of the internal clock (Internal_CLK) exists in the first section (1), the internal clock (Internal_CLK) is used as it is or a predetermined time delay is used to sample the data (IN). If the trigger edge (arrow) of the internal clock (Internal_CLK) is present in the second section (2), the internal clock (Internal_CLK) is inverted to sample the data (IN).

First, an internal clock (Internal_CLK) is used to distinguish the first section (①) and the second section (②).

FIG. 5 is a clock pulse diagram when a trigger edge of a plurality of delay clocks having a predetermined time delay of an internal clock Internal_CLK exists in a first section of an external clock External_CLK.

Referring to FIG. 5, there are three delay clocks (Internal_CLK0 to Internal_CLK2) in which the internal clock (Internal_CLK) is delayed a predetermined time in the logic high period of the external clock (External_CLK), and the rising edges (arrows) of the three delay clocks. Are all within the logic high section of the external clock External_CLK, it can be seen that the control signal CNTL has a logic low of " 0 ". The first delay clock Internal_CLK0 and the third delay clock Internal_CLK2 have a phase difference of 1.5 ns.

The fact that the rising edges (arrows) of the three delay clocks (Internal_CLK0 to Internal_CLK2) are all within the logic high interval of the external clock (External_CLK) means that when the values of the external clock (External_CLK) are sampled at the rising edges of the three delay clocks, It has the same value. The value of the control signal CNTL may be arbitrarily selected from among logic low "0" and logic high "1".

FIG. 6 is a clock pulse diagram when a trigger edge of a plurality of delay clocks having a predetermined time delay of an internal clock Internal_CLK exists in a second section of an external clock External_CLK.

Referring to FIG. 6, in the case where any one of the trigger edges (rising edges) of the plurality of delay clocks is in the second section, the second clock signal CLK2 is inverted to sample the data IN. Able to know.

As described above, the optimum embodiment has been disclosed in the drawings and the specification. Although specific terms have been used herein, they are used only for the purpose of describing the present invention and are not intended to limit the scope of the invention as defined in the claims or the claims. Therefore, those skilled in the art will understand that various modifications and equivalent other embodiments are possible. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

As described above, the digital data sampling block and the sampling method according to the present invention can reduce the power consumption of the system because the external data is used in the internal circuit but the delay time is minimized and the register is not used. There is an advantage.

Claims (17)

The digital data sampling block for sampling external digital data loaded according to the first clock signal using the second clock signal may include: A data capture block configured to sample and output the external digital data by using the second clock signal and an inverted second clock signal inverted in phase of the second clock signal; An external clock capture block configured to output a control signal using information on a phase difference between the first clock signal and the second clock signal; And a multiplexer for selecting and outputting output data of the data capture block according to the control signal. The method of claim 1, wherein the data capture block, A clock signal inversion device for outputting the inverted second clock signal in which the phase of the second clock signal is inverted by 180 degrees; A first sampling block for sampling the external digital data using the second clock signal; And And a second sampling block for sampling the external digital data using the inverted second clock signal.  The clock signal reversing apparatus of claim 2, And an inverter for applying the second clock signal to an input terminal and outputting the inverted second clock signal to an output terminal.  The method of claim 2, wherein the first sampling block, A D type flip-flop is input to the external terminal and operates in response to the second clock signal; The second sampling block, And a D-type flip-flop input to the external terminal and operating in response to the inverted second clock signal. The method of claim 1, wherein the external clock capture block, A delay clock generation device generating delayed second clock signals delaying the second clock signal and the second clock signal by at least two different delay times; An external clock sampling block configured to sample the first clock signal using the at least two delayed second clock signals; And a comparator for comparing the output data of the external clock sampling block and outputting the control signal. The apparatus of claim 5, wherein the delay clock generator is A first delay device outputting a first delay clock having the smallest delay time with respect to the second clock signal; A second delay device outputting a second delay clock having a delay time with respect to the second clock signal greater than the first delay clock; And And an Nth delay device for outputting an Nth delay clock having a delay time for the second clock signal greater than the (N-1) th delay clock, wherein N is an integer. The method of claim 6, wherein the external clock sampling block, A third sampling block for sampling the first clock signal using the first delay clock; A fourth sampling block for sampling the first clock signal using the second delay clock; And And a (N + 2) sampling block for sampling the first clock signal using the Nth delay clock. The method of claim 7, wherein the third sampling block, The first clock signal is applied to an input terminal and is a D flip-flop that operates in response to the first delay clock, The fourth sampling block, The first clock signal is applied to an input terminal and is a D-type flip-flop that operates in response to the second delay clock, The (N + 2) sampling block is, And a D-type flip-flop applied with the first clock signal to an input terminal and operating in response to the Nth delay clock. The method of claim 6, wherein the comparative analyzer, And if all values of the output data of the external clock sampling block are the same, output the first logic value as a control signal, and if all values are not the same, output the second logic value as a control signal. Sampling block. The method of claim 9, wherein the multiplexer, Output sampled data corresponding to the second clock signal in response to the first logic value, and output sampled data corresponding to the inverted second clock signal in response to the second logic value. Digital data sampling block. A digital data sampling method for sampling external digital data loaded according to a first clock signal using a second clock signal may include: An external digital data capture step of sampling and outputting the external digital data by using the second clock signal and an inverted second clock signal inverted in phase of the second clock signal; An external clock capture step of outputting a control signal using information on the phase difference between the first clock signal and the second clock signal; And And a multiplexing step of selecting and outputting the output data of the data capturing step according to the control signal. The method of claim 11, wherein the data capture step, A clock signal inversion step of outputting the inverted second clock signal in which the phase of the second clock signal is inverted by 180 degrees; A first sampling step of sampling the external digital data using the second clock signal; And And a second sampling step of sampling the external digital data by using the inverted second clock signal. The method of claim 11, wherein the external clock capture step, A delay clock generation step of generating delayed second clock signals delaying the second clock signal and the second clock signal by at least two different delay times; An external clock sampling step of sampling the first clock signal using the at least two delayed second clock signals; And And comparing and analyzing output data of the external clock sampling block to output the control signal. The method of claim 13, wherein the delay clock generating step, A first delay step of outputting a first delay clock having the smallest delay time with respect to the second clock signal; A second delay step of outputting a second delay clock having a delay time with respect to the second clock signal greater than the first delay clock; And And an Nth delay step of outputting an Nth delay clock having a delay time for the second clock signal greater than the (N-1) th delay clock, wherein N is an integer. The method of claim 14, wherein the external clock sampling step, A third sampling step of sampling the first clock signal using the first delay clock; A fourth sampling step of sampling the first clock signal using the second delay clock; And And a (N + 2) sampling step of sampling the first clock signal using the Nth delay clock. The method of claim 13, wherein the comparative analysis step, And if all values of the output data of the external clock sampling block are the same, output the first logic value as a control signal, and if all values are not the same, output the second logic value as a control signal. Sampling Method. The method of claim 13, wherein the multiplexing step, Output sampled data corresponding to the second clock signal in response to the first logic value, and output sampled data corresponding to the inverted second clock signal in response to the second logic value. Digital data sampling method.

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