CN112164371A - Drive circuit and display panel - Google Patents
Drive circuit and display panel Download PDFInfo
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- CN112164371A CN112164371A CN202011095672.7A CN202011095672A CN112164371A CN 112164371 A CN112164371 A CN 112164371A CN 202011095672 A CN202011095672 A CN 202011095672A CN 112164371 A CN112164371 A CN 112164371A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
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Abstract
The embodiment of the application provides a drive circuit and display panel, drive circuit are applied to display panel, drive circuit includes: a gate driving sub-circuit for outputting a driving signal; the gating sub-circuit comprises a gating input end, a first gating output end and a second gating output end, the gating sub-circuit is used for selecting one of the first gating output end and the second gating output end to be conducted with the gating input end, and the gating input end is connected with the output end of the grid driving sub-circuit; and the phase reversal sub-circuit is connected with the second gating output end and is used for reversing the phase of the signal input into the phase reversal sub-circuit, and the output end of the phase reversal sub-circuit is connected with the first gating output end. The gate sub-circuit can select whether the output end of the gate driving sub-circuit is communicated with the inverting sub-circuit, so that the signal input to the rear end is the signal originally output by the gate driving sub-circuit or the inverted signal, and two different signals are provided to realize different functions.
Description
Technical Field
The application relates to the technical field of display, in particular to a driving circuit and a display panel.
Background
An OLED (Organic Light Emitting Diode) display panel has the advantages of high brightness, wide viewing angle, fast response speed, low power consumption, and the like, and is widely applied to the field of high-performance display. In the OLED display panel, pixels are arranged in a matrix shape comprising a plurality of rows and a plurality of columns, and a grid drive circuit of the OLED display panel outputs fixed signals to control the on of each row of pixels.
Disclosure of Invention
An object of the embodiments of the present invention is to provide a driving circuit and a display panel, which can change the output signal of a gate driving sub-circuit to achieve multiple functions.
The embodiment of the application provides a driving circuit, it is applied to display panel, driving circuit includes:
a gate driving sub-circuit for outputting a driving signal;
the gate sub-circuit comprises a gate input end, a first gate output end and a second gate output end, the gate sub-circuit is used for selecting one of the first gate output end and the second gate output end to be conducted with the gate input end, and the gate input end is connected with the output end of the gate drive sub-circuit; and
and the phase reversal sub-circuit is connected with the second gating output end, is used for reversing the phase of the signal input into the phase reversal sub-circuit, and has an output end connected with the first gating output end.
The embodiment of the application also provides a display panel which comprises the driving circuit.
In the embodiment of the application, the output end of the gate driving sub-circuit is connected with the gating sub-circuit and the inverting sub-circuit, and the gating sub-circuit can select whether the output end of the gate driving sub-circuit is communicated with the inverting sub-circuit or not, so that a signal input to the rear end is a signal originally output by the gate driving sub-circuit or is a signal after inverting, and two different signals are provided to realize different functions.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic diagram of a driving circuit according to an embodiment of the present disclosure.
Fig. 2 is a schematic diagram of a gate sub-circuit and an inverting sub-circuit in the driving circuit shown in fig. 1.
Fig. 3 is a timing diagram of the gate sub-circuit and the inverting sub-circuit shown in fig. 2.
Fig. 4 is another schematic diagram of the gate sub-circuit and the inverter sub-circuit in the driving circuit shown in fig. 1.
Fig. 5 is a timing diagram of the gating sub-circuit and the inverting sub-circuit shown in fig. 4.
Fig. 6 is a schematic diagram of a gate driver sub-circuit in the driving circuit shown in fig. 1.
Fig. 7 is a timing diagram of the gate driver sub-circuit shown in fig. 6.
Fig. 8 is a schematic structural diagram of a pixel driving sub-circuit of a driving circuit according to an embodiment of the present disclosure.
Fig. 9 is a schematic view of a display panel according to an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
The transistors used in all embodiments of the present application may be thin film transistors or field effect transistors or other devices with the same characteristics, and since the source and drain of the transistors used herein are symmetrical, the source and drain may be interchanged as required. In the embodiment of the present application, to distinguish two poles of a transistor except for a gate, one of the two poles is referred to as a source, and the other pole is referred to as a drain. The form in the drawing provides that the middle end of the switching transistor is a grid, the signal input end is a source, and the output end is a drain. In addition, the transistors used in the embodiments of the present application may include a P-type transistor and/or an N-type transistor, where the P-type transistor is turned on when the gate is at a low level and turned off when the gate is at a high level, and the N-type transistor is turned on when the gate is at a high level and turned off when the gate is at a low level.
Referring to fig. 1, fig. 1 is a schematic diagram of a driving circuit according to an embodiment of the present disclosure. The embodiment of the application provides a driving circuit 100, the driving circuit 100 is applied to a display panel, and the driving circuit 100 includes a gate driving sub-circuit 110, a gate sub-circuit 120 and an inverting sub-circuit 130.
The gate driving sub-circuit 110 is used to output a driving signal.
The gate sub-circuit 120 includes a gate input terminal 122, a first gate output terminal 124, and a second gate output terminal 126, the gate sub-circuit 120 is configured to select one of the first gate output terminal 124 and the second gate output terminal 126 to be turned on with the gate input terminal 122, and the gate input terminal 122 is connected to an output terminal of the gate driving sub-circuit 110.
The inverting sub-circuit 130 is coupled to the second gated output 126, the inverting sub-circuit 130 is configured to invert the signal input to the inverting sub-circuit 130, and the output of the inverting sub-circuit 130 is coupled to the first gated output 124.
In the related art, the gate driving sub-circuit is used to output a low voltage pulse, but when a constant low voltage is required in a test stage, the gate driving sub-circuit cannot be realized. The reason is that when the low voltage pulse width of the start signal STV is increased, the pulse width of the start signal STV cannot be supplied to the PD point because the pulse width of the second clock signal XCK is fixed, and the pulse width of the first clock signal CK is also fixed and cannot be adjusted accordingly, so that the gate driver sub-circuit cannot adjust the output pulse width, and the test cannot be completed normally.
In this embodiment, the output terminal of the gate driving sub-circuit 110 is connected to the gate sub-circuit 120 and the inverting sub-circuit 130, and the gate sub-circuit 120 can select whether the output terminal of the gate driving sub-circuit 110 is connected to the inverting sub-circuit 130, so that the signal input to the back end is the signal originally output by the gate driving sub-circuit 110, or the signal after the inversion provides two different signals to implement different functions. For example, the signal originally output by the gate driving sub-circuit 110 can control the turn-on of each row of pixels, and the inverted signal can be used for testing.
Referring to fig. 2 and 3, fig. 2 is a schematic diagram of a gate sub-circuit and an inverter sub-circuit in the driving circuit shown in fig. 1, and fig. 3 is a timing diagram of the gate sub-circuit and the inverter sub-circuit shown in fig. 2.
The gate sub-circuit 120 includes a first gate transistor Q1 and a second gate transistor Q2. The gate of the first gating transistor Q1 is connected with the gate of the second gating transistor Q2 and is connected with a gating control line EN; the drain of the first gating transistor Q1 is connected to the drain of the second gating transistor Q2 and to the output XA of the gate drive sub-circuit 110; the source of the first gating transistor Q1 is connected to the input terminal of the inverting sub-circuit 130, and the source of the second gating transistor Q2 is connected to the output terminal OUT of the inverting sub-circuit 130.
The first gating transistor Q1 is a PMOS transistor, and the second gating transistor Q2 is an NMOS transistor; when the gate control line EN outputs a low level, the first gate transistor Q1 is turned on to connect the output terminal XA of the gate driving sub-circuit 110 with the input terminal of the inverting sub-circuit 130; when the gate control line EN outputs a high level, the second gate transistor Q2 is turned on to connect the output terminal XA of the gate drive sub-circuit 110 with the output terminal OUT of the inverter sub-circuit 130.
Whether the original signal or the inverted signal of the gate driving sub-circuit 110 is input to the rear end can be controlled by the gate control line EN.
Referring to fig. 4 and 5, fig. 4 is another schematic diagram of the gate sub-circuit and the inverter sub-circuit in the driving circuit shown in fig. 1, and fig. 5 is a timing diagram of the gate sub-circuit and the inverter sub-circuit shown in fig. 4.
The first gating transistor Q1 is an NMOS transistor, and the second gating transistor Q2 is a PMOS transistor; when the gate control line EN outputs a high level, the first gate transistor Q1 is turned on to connect the output terminal XA of the gate driving sub-circuit 110 with the input terminal of the inverting sub-circuit 130; when the gate control line EN outputs a low level, the second gate transistor Q2 is turned on to connect the output terminal of the gate drive sub-circuit 110 with the output terminal OUT of the inverting sub-circuit 130.
Through the gate control line EN, it is possible to select different signals as needed to control whether the original signal or the inverted signal of the gate driving sub-circuit 110 is input to the rear end.
With continued reference to fig. 2 to 5, the inverter sub-circuit 130 includes a first inverter transistor Q3 and a second inverter transistor Q4, the first inverter transistor Q3 is an NMOS transistor, and the second inverter transistor Q4 is a PMOS transistor; the gate of the first inverting transistor Q3 is connected to the gate of the second inverting transistor Q4 and to the second gating output 126 of the gating circuit; the source of the first inverting transistor Q3 is connected to the source of the second inverting transistor Q4 and to the first gate output 124 of the gate circuit; the drain of the first inverter transistor Q3 is connected to the first voltage terminal VGL, the drain of the second inverter transistor Q4 is connected to the second voltage terminal VGH, and the voltage of the second voltage terminal VGH is greater than the voltage of the first voltage terminal VGL. The first voltage terminal VGL may be a negative voltage, and the second voltage terminal VGH may be a positive voltage.
When the gate drive sub-circuit 110 outputs a high level signal, the first inverter transistor Q3 is turned on, the second inverter transistor Q4 is turned off, and the first inverter transistor Q3 outputs the first voltage terminal VGL, i.e., outputs a low level signal, thereby inverting the high level signal output by the gate drive sub-circuit 110 to a low level signal. When the gate drive sub-circuit 110 outputs a low level signal, the second inverter transistor Q4 is turned on, the first inverter transistor Q3 is turned off, and the second inverter transistor Q4 outputs the second voltage terminal VGH, i.e., outputs a high level signal, thereby inverting the low level signal output by the gate drive sub-circuit 110 to a high level signal.
Referring to fig. 6 and 7, fig. 6 is a schematic diagram of a gate driving sub-circuit in the driving circuit shown in fig. 1, and fig. 7 is a timing diagram of the gate driving sub-circuit shown in fig. 6. The gate driving sub-circuit 110 includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a first capacitor C1, and a second capacitor C2.
The drain of the first transistor T1 is connected to the first voltage terminal VGL, the source of the first transistor T1 is connected to the first node PU, and the gate of the first transistor T1 is connected to the second clock signal XCK.
The drain of the second transistor T2 is connected to the start signal STV, the source of the second transistor T2 is connected to the second node a, and the gate of the second transistor T2 is connected to the second clock signal XCK.
The drain of the third transistor T3 is connected to the second clock signal XCK, the source of the third transistor T3 is connected to the first node PU, and the gate of the third transistor T3 is connected to the second node a.
The drain of the fourth transistor T4 is connected to the second node a, and the gate of the fourth transistor T4 is connected to the first clock signal CK.
The drain of the fifth transistor T5 is connected to the source of the fourth transistor T4, the source of the fifth transistor T5 is connected to the second voltage terminal VGH, and the gate of the fifth transistor T5 is connected to the first node PU.
The drain of the sixth transistor T6 is connected to the first clock signal CK, the source of the sixth transistor T6 is connected to the output terminal XA of the gate driving sub-circuit 110, and the gate of the sixth transistor T6 is connected to the third node PD.
The drain of the seventh transistor T7 is connected to the output terminal XA of the gate driving sub circuit 110, the source of the seventh transistor T7 is connected to the second voltage terminal VGH, and the gate of the seventh transistor T7 is connected to the first node PU.
The drain of the eighth transistor T8 is connected to the second node a, the source of the eighth transistor T8 is connected to the third node PD, and the gate of the eighth transistor T8 is connected to the first voltage terminal VGL.
A first terminal of the first capacitor C1 is connected to the third node PD, and a second terminal of the first capacitor C1 is connected to the output terminal XA of the gate driving sub-circuit 110.
A first terminal of the second capacitor C2 is connected to the first node PU, and a second terminal of the second capacitor C2 is connected to the second voltage terminal VGH.
The first voltage terminal VGL may be a negative voltage, and the second voltage terminal VGH may be a positive voltage. At Step1, the second clock signal XCK outputs low, the first clock signal CK outputs high, the start signal STV outputs low, and the output terminal XA of the gate driver sub-circuit 110 outputs high. At Step2, the second clock signal XCK outputs high, the first clock signal CK outputs low, the start signal STV outputs high, and the output terminal XA of the gate driver sub-circuit 110 outputs low. At Step3, the second clock signal XCK outputs low, the first clock signal CK outputs high, the start signal STV outputs high, and the output terminal XA of the gate driver sub-circuit 110 outputs high. At Step4, the second clock signal XCK outputs high, the first clock signal CK outputs low, the start signal STV outputs high, and the output terminal XA of the gate driver sub-circuit 110 outputs low. The output terminal XA of the gate driving sub-circuit 110 can output a low voltage pulse signal, and the gate sub-circuit 120 and the inverting sub-circuit 130 can convert the low voltage pulse signal into a high voltage pulse signal.
Referring to fig. 8, fig. 8 is a schematic structural diagram of a pixel driving sub-circuit of a driving circuit according to an embodiment of the present disclosure. The driving circuit 100 further includes a pixel driving sub-circuit 140 and a pixel 150, the pixel driving sub-circuit 140 including a first pixel transistor T1 ', a second pixel transistor T2', a third pixel transistor T3 ', a fourth pixel transistor T4', a fifth pixel transistor T5 ', a sixth pixel transistor T6', a seventh pixel transistor T7 'and a first pixel capacitance C1'.
The drain of the first pixel transistor T1 ' is connected to the fourth node D, the source of the first pixel transistor T1 ' is connected to the fifth node E, and the gate of the first pixel transistor T1 ' is connected to the sixth node F.
The drain of the second pixel transistor T2 'is connected to the digital signal line DATA, the source of the second pixel transistor T2' is connected to the fourth node D, and the gate of the pixel second transistor T2 is connected to the first control line scan (n). A first control line scan (n) connects the output of the inverting sub-circuit and the first gating output of the gating sub-circuit.
The drain of the third pixel transistor T3 'is connected to the sixth node F, the source of the third pixel transistor T3 is connected to the fifth node E, and the gate of the third pixel transistor T3' is connected to the first control line scan (n).
The drain of the fourth pixel transistor T4 ' is connected to the sixth node F, the source of the fourth pixel transistor T4 ' is connected to the reference signal line VI, and the Gate of the fourth pixel transistor T4 ' is connected to the first Reset signal line Reset Gate.
The drain of the fifth pixel transistor T5 ' is connected to the power source terminal VDD, the source of the fifth pixel transistor T5 ' is connected to the fourth node D, and the gate of the fifth pixel transistor T5 ' is connected to the second control signal line EM.
The drain of the sixth pixel transistor T6 ' is connected to the fifth node E, the source of the sixth pixel transistor T6 ' is connected to the pixel 150, and the gate of the sixth pixel transistor T6 ' is connected to the second control signal line EM.
The drain of the seventh pixel transistor T7 ' is connected to the reference signal line VI, the source of the seventh pixel transistor T7 ' is connected to the pixel 150, and the gate of the seventh pixel transistor T7 ' is connected to the second Reset signal line Reset anode.
A first terminal of the first pixel capacitor C1 'is connected to the power source terminal VDD, and a second terminal of the first pixel capacitor C1' is connected to the sixth node F.
The first pixel transistor T1 ', the second pixel transistor T2 ', the third pixel transistor T3 ', the fourth pixel transistor T4 ', the fifth pixel transistor T5 ', the sixth pixel transistor T6 ' and the seventh pixel transistor T7 ' are all PMOS transistors.
One end of the pixel 150 is connected to the source of the seventh pixel transistor T7', and the other end is grounded.
It should be noted that the gate driving sub-circuit may be arranged in other circuit structures as required, and the pixel driving sub-circuit may be arranged in other circuit structures as required, such as 6T2C, 5T2C, 3T1C or 2T 1C. The gating subcircuits may be arranged in other circuit configurations as desired. The inverting sub-circuit may be configured in other circuit configurations as desired.
An embodiment of the present application further provides a display panel, where the display panel includes the driving circuit in any one of the above embodiments, and a detailed structure of the driving circuit is not described herein again. It can be understood that please refer to fig. 9, fig. 9 is a schematic view of a display panel provided in the embodiment of the present application. The driving circuit of the display panel 10 may include a plurality of gate driving sub-circuits 110, a plurality of gate sub-circuits 120, and a plurality of inverter sub-circuits 130. The specific structures of the gate driving sub-circuit 110, the gating sub-circuit 120 and the inverting sub-circuit 130 can refer to the above embodiments, and are not described herein again.
The above description is only an embodiment of the present invention, and not intended to limit the scope of the present invention, and all modifications of equivalent structures and equivalent processes, which are made by using the contents of the present specification and the accompanying drawings, or directly or indirectly applied to other related technical fields, are included in the scope of the present invention.
Claims (10)
1. A driving circuit applied to a display panel, the driving circuit comprising:
a gate driving sub-circuit for outputting a driving signal;
the gate sub-circuit comprises a gate input end, a first gate output end and a second gate output end, the gate sub-circuit is used for selecting one of the first gate output end and the second gate output end to be conducted with the gate input end, and the gate input end is connected with the output end of the gate drive sub-circuit; and
and the phase reversal sub-circuit is connected with the second gating output end, is used for reversing the phase of the signal input into the phase reversal sub-circuit, and has an output end connected with the first gating output end.
2. The driving circuit of claim 1, wherein the gating sub-circuit comprises a first gating transistor and a second gating transistor;
the grid electrode of the first gating transistor is connected with the grid electrode of the second gating transistor and is connected with a gating control line;
the drain electrode of the first gating transistor is connected with the drain electrode of the second gating transistor and is connected with the output end of the grid electrode driving sub-circuit;
the source electrode of the first gating transistor is connected with the input end of the inverting sub-circuit, and the source electrode of the second gating transistor is connected with the output end of the inverting sub-circuit.
3. The driving circuit according to claim 2, wherein the first gating transistor is a PMOS transistor, and the second gating transistor is an NMOS transistor;
when the gating control line outputs a low level, the first gating transistor is conducted so that the output end of the gate driving sub-circuit is connected with the input end of the inverting sub-circuit;
when the gating control line outputs a high level, the second gating transistor is turned on to connect the output terminal of the gate driving sub-circuit with the output terminal of the inverting sub-circuit.
4. The driving circuit according to claim 2, wherein the first gating transistor is an NMOS transistor, and the second gating transistor is a PMOS transistor;
when the gating control line outputs a high level, the first gating transistor is conducted so that the output end of the gate driving sub-circuit is connected with the input end of the inverting sub-circuit;
when the gating control line outputs a low level, the second gating transistor is turned on to connect the output terminal of the gate driving sub-circuit with the output terminal of the inverting sub-circuit.
5. The driving circuit according to claim 1, wherein the inverting sub-circuit comprises a first inverting transistor and a second inverting transistor, the first inverting transistor is an NMOS transistor, and the second inverting transistor is a PMOS transistor;
the grid electrode of the first inverting transistor is connected with the grid electrode of the second inverting transistor and is connected with the second gating output end of the gating circuit;
the source electrode of the first inverting transistor is connected with the source electrode of the second inverting transistor and is connected with the first gating output end of the gating circuit;
the drain electrode of the first inverting transistor is connected with a first voltage end, the drain electrode of the second inverting transistor is connected with a second voltage end, and the voltage of the second voltage end is greater than that of the first voltage end.
6. The driving circuit according to claim 1, wherein the gate driving sub-circuit comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a first capacitor, and a second capacitor;
the drain electrode of the first transistor is connected to a first voltage end, the source electrode of the first transistor is connected to a first node, and the grid electrode of the first transistor is connected to a second clock signal;
the drain electrode of the second transistor is connected to a starting signal, the source electrode of the second transistor is connected to a second node, and the grid electrode of the second transistor is connected to a second clock signal;
the drain electrode of the third transistor is connected to a second clock signal, the source electrode of the third transistor is connected to a first node, and the grid electrode of the third transistor is connected to a second node;
the drain electrode of the fourth transistor is connected to a second node, and the grid electrode of the fourth transistor is connected to the first clock signal;
the drain electrode of the fifth transistor is connected to the source electrode of the fourth transistor, the source electrode of the fifth transistor is connected to the second voltage end, and the grid electrode of the fifth transistor is connected to the first node;
the drain of the sixth transistor is connected to the first clock signal, the source of the sixth transistor is connected to the output end of the gate driving sub-circuit, and the gate of the sixth transistor is connected to the third node;
the drain electrode of the seventh transistor is connected to the output end of the gate drive sub-circuit, the source electrode of the seventh transistor is connected to the second voltage end, and the gate electrode of the seventh transistor is connected to the first node;
the drain of the eighth transistor is connected to the second node, the source of the eighth transistor is connected to the third node, and the gate of the eighth transistor is connected to the first voltage end;
the first end of the first capacitor is connected to a third node, and the second end of the first capacitor is connected to the output end of the grid driving sub-circuit;
a first end of the second capacitor is connected to the first node, and a second end of the second capacitor is connected to the second voltage terminal.
7. The driving circuit of claim 6, wherein the output of the gate driving sub-circuit is capable of outputting a low voltage pulse signal, and the gating sub-circuit and the inverting sub-circuit are capable of converting the low voltage pulse signal into a high voltage pulse signal.
8. The driving circuit according to claim 1, further comprising a pixel driving sub-circuit and a pixel, wherein the pixel driving sub-circuit comprises a first pixel transistor, a second pixel transistor, a third pixel transistor, a fourth pixel transistor, a fifth pixel transistor, a sixth pixel transistor, a seventh pixel transistor, and a first pixel capacitor;
the drain electrode of the first pixel transistor is connected to a fourth node, the source electrode of the first pixel transistor is connected to a fifth node, and the grid electrode of the first pixel transistor is connected to a sixth node;
the drain electrode of the second pixel transistor is connected to the digital signal line, the source electrode of the second pixel transistor is connected to the fourth node, and the grid electrode of the second pixel transistor is connected to the first control line;
the drain electrode of the third pixel transistor is connected to a sixth node, the source electrode of the third pixel transistor is connected to a fifth node, and the grid electrode of the third pixel transistor is connected to a first control line;
the drain of the fourth pixel transistor is connected to a sixth node, the source of the fourth pixel transistor is connected to a reference signal line, and the gate of the fourth pixel transistor is connected to a first reset signal line;
the drain electrode of the fifth pixel transistor is connected to a power supply end, the source electrode of the fifth pixel transistor is connected to a fourth node, and the grid electrode of the fifth pixel transistor is connected to a second control signal line;
the drain electrode of the sixth pixel transistor is connected to a fifth node, the source electrode of the sixth pixel transistor is connected to the pixel, and the grid electrode of the sixth pixel transistor is connected to a second control signal line;
the drain electrode of the seventh pixel transistor is connected to a reference signal line, the source electrode of the seventh pixel transistor is connected to the pixel, and the grid electrode of the seventh pixel transistor is connected to a second reset signal line;
a first end of the first pixel capacitor is connected to a power supply end, and a second end of the first pixel capacitor is connected to the sixth node.
9. The driving circuit according to claim 8, wherein the first pixel transistor, the second pixel transistor, the third pixel transistor, the fourth pixel transistor, the fifth pixel transistor, the sixth pixel transistor, and the seventh pixel transistor are all PMOS transistors.
10. A display panel comprising the driver circuit according to any one of claims 1 to 9.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US11361713B1 (en) * | 2021-05-17 | 2022-06-14 | Shanghai Tianma Micro-electronics Co., Ltd. | Display panel and display device |
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| US11361713B1 (en) * | 2021-05-17 | 2022-06-14 | Shanghai Tianma Micro-electronics Co., Ltd. | Display panel and display device |
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