KR20100011215A - Method of manufacturing multi-layer circuit board using selective plating by forming middle-layer - Google Patents
Method of manufacturing multi-layer circuit board using selective plating by forming middle-layer Download PDFInfo
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- KR20100011215A KR20100011215A KR1020080072338A KR20080072338A KR20100011215A KR 20100011215 A KR20100011215 A KR 20100011215A KR 1020080072338 A KR1020080072338 A KR 1020080072338A KR 20080072338 A KR20080072338 A KR 20080072338A KR 20100011215 A KR20100011215 A KR 20100011215A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 32
- 238000007747 plating Methods 0.000 title claims abstract description 27
- 238000000034 method Methods 0.000 claims abstract description 34
- 229910052751 metal Inorganic materials 0.000 claims abstract description 32
- 239000002184 metal Substances 0.000 claims abstract description 32
- 230000001681 protective effect Effects 0.000 claims abstract description 29
- 239000000758 substrate Substances 0.000 claims description 31
- 229910052782 aluminium Inorganic materials 0.000 claims description 16
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical group [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 16
- 229920002120 photoresistant polymer Polymers 0.000 claims description 12
- 238000005530 etching Methods 0.000 claims description 6
- 238000002048 anodisation reaction Methods 0.000 claims description 5
- 230000015572 biosynthetic process Effects 0.000 claims description 5
- 238000007743 anodising Methods 0.000 claims description 4
- 238000000469 dry deposition Methods 0.000 claims description 4
- 238000000206 photolithography Methods 0.000 claims description 4
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 4
- 238000004544 sputter deposition Methods 0.000 claims description 4
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 2
- 238000000151 deposition Methods 0.000 claims description 2
- 239000007769 metal material Substances 0.000 claims description 2
- 239000010936 titanium Substances 0.000 claims description 2
- 229910052719 titanium Inorganic materials 0.000 claims description 2
- 239000010410 layer Substances 0.000 abstract description 90
- 239000000463 material Substances 0.000 abstract description 6
- 239000011229 interlayer Substances 0.000 abstract description 5
- 230000003647 oxidation Effects 0.000 abstract 1
- 238000007254 oxidation reaction Methods 0.000 abstract 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 6
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- MUBZPKHOEPUJKR-UHFFFAOYSA-N Oxalic acid Chemical compound OC(=O)C(O)=O MUBZPKHOEPUJKR-UHFFFAOYSA-N 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 229910020177 SiOF Inorganic materials 0.000 description 1
- 239000005380 borophosphosilicate glass Substances 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 235000006408 oxalic acid Nutrition 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76832—Multiple layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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Abstract
Description
본 발명은 멀티레이어 기판을 제조하는 방법에 관한 것으로, 더욱 자세하게는 재료의 제한 없이 멀티레이어 기판을 제조하는 방법에 관한 것이다.The present invention relates to a method of manufacturing a multilayer substrate, and more particularly, to a method of manufacturing a multilayer substrate without material limitation.
반도체 패키징, 멤스(MEMS) 또는 COG(칩온글라스)기판 등과 같은 디스플레이 분야에서 고성능화 내지 고집적화가 요구됨에 따라, 멀티레이어 기술이 필수적으로 사용되고 있다.BACKGROUND ART As the high performance and high integration are required in display fields such as semiconductor packaging, MEMS or COG (chip on glass) substrates, multilayer technologies are inevitably used.
이러한 멀티레이어 기술은 다층의 금속배선구조로 이루어지고, 상부 및 하부 금속배선들 사이에 층간절연층이 개재되어 있는 것이다. 종래의 멀티레이어 기판 제조방법에서는 층간절연층을 SiO2, DSG(SiOF), TFOS, BPSG 등의 재질로 형성하고 있으며, 이러한 층간절연층위에 도금을 실시하기 어렵다는 점이 멀티레이어 기판을 제조함에 있어서 큰 문제이다.This multilayer technology consists of a multi-layered metal interconnection structure, and an interlayer insulating layer is interposed between upper and lower metal interconnections. In the conventional multilayer substrate manufacturing method, the interlayer insulating layer is formed of SiO 2 , DSG (SiOF), TFOS, BPSG, or the like, and it is difficult to plate the interlayer insulating layer on the multilayer insulating layer. It is a problem.
또한, 종래의 멀티레이어 기판 제조방법은, 전체적인 제조비용이 높고 제조공정이 복잡한 단점이 있다. 이러한 단점을 해결하기 위하여 최근에는 알루미늄을 양극산화 방법으로 산화시킨 AOO(anodic aluminum oxide)를 절연층으로 사용하는 등의 다양한 방법이 개발되고 있다.In addition, the conventional multilayer substrate manufacturing method has a disadvantage in that the overall manufacturing cost is high and the manufacturing process is complicated. In order to solve this drawback, various methods such as using AOO (anodic aluminum oxide) in which aluminum is oxidized by anodizing has been developed.
하지만, 새로운 멀티레이어 기판 제조방법에서 사용되는 알루미늄 등은 그 위에 도금을 실시하기 어려운 금속이라는 문제점이 있어 실용화되지 못하고 있는 실정이다.However, aluminum and the like used in the new multilayer substrate manufacturing method has a problem that it is difficult to perform plating on it, and thus it is not practical.
본 발명은 상기 문제점을 해결하기 위하여 발명된 것으로, 중간층을 형성하여 도금을 실시함으로써 재료의 제한 없이 멀티레이어 기판을 제조할 수 있는 방법을 제공하는 것을 목적으로 한다. The present invention has been invented to solve the above problems, and an object of the present invention is to provide a method of manufacturing a multilayer substrate without limiting the material by forming an intermediate layer and performing plating.
상기의 목적을 달성하기 위하여 본 발명에 의한 중간층 형성을 통한 선택적 도금을 이용한 멀티레이어 기판 제조방법은, 기재의 표면에 금속층을 형성하는 1단계; 상기 금속층의 표면에 제1보호피막 패턴을 형성하는 2단계; 상기 금속층을 상기 제1보호피막 패턴에 의해 선택적으로 양극산화시킨 뒤에 상기 제1보호피막을 제거하는 3단계; 상기 3단계에서 제1보호피막을 제거한 표면에 중간층을 형성하는 4단계; 상기 중간층의 표면에 제2보호피막 패턴을 형성하는 5단계; 상기 중간층을 상기 제2보호피막 패턴에 의해 선택적으로 에칭하는 6단계; 및 상기 제2보호피막을 제거하고 에칭 뒤에 남은 중간층에 도금을 실시하는 7단계를 포함하는 것을 특징으로 한다. In order to achieve the above object, a multilayer substrate manufacturing method using selective plating by forming an intermediate layer according to the present invention includes a step of forming a metal layer on a surface of a substrate; Forming a first protective film pattern on the surface of the metal layer; Removing the first protective film after selectively anodizing the metal layer by the first protective film pattern; Forming an intermediate layer on the surface from which the first protective film is removed in step 3; Forming a second protective film pattern on the surface of the intermediate layer; Selectively etching the intermediate layer by the second protective film pattern; And removing the second protective film and performing plating on the intermediate layer remaining after the etching.
이때, 4단계에서는 중간층을 형성하기에 앞서 1단계부터 3단계까지의 공정을 1번 이상 반복 수행하여 다층의 금속 회로 패턴을 형성시킨 뒤에 중간층을 형성하거나, 중간층을 형성하기에 앞서 제1보호피막이 제거된 표면 전체에 금속층을 증착한 뒤에 중간층을 형성하는 것도 가능하다.At this time, in step 4, the steps 1 to 3 are repeated one or more times before the intermediate layer is formed to form a multi-layer metal circuit pattern, and then an intermediate layer is formed, or the first protective film is formed before the intermediate layer is formed. It is also possible to form an intermediate layer after depositing a metal layer over the removed surface.
이때, 4단계에서 제1보호피막을 제거한 뒤에 제1금속층 표면을 전면적으로 양극산화시켜 절연층을 형성하고, 상기 절연층에 관통홀을 형성한 뒤에, 중간층을 형성하는 것도 가능하다.In this case, after removing the first protective film in step 4, the entire surface of the first metal layer is anodized to form an insulating layer, and after forming a through hole in the insulating layer, an intermediate layer may be formed.
또한, 7단계의 제2보호피막을 제거하기 전에, 상기 6단계에서 중간층을 에칭하여 드러난 금속층 또는 금속층의 양극산화층에 추가공정을 실시할 수 있다.In addition, before removing the second protective film in step 7, an additional process may be performed on the metal layer or the anodization layer of the metal layer exposed by etching the intermediate layer in step 6.
상기 금속층은 알루미늄층 또는 티타늄층 등 도금이 어려운 금속층이고, 상기 중간층은 도금이 쉬운 금속재질이며, 도금이 쉬운 금속은 Cu와 Au 등이 대표적이다.The metal layer is a metal layer that is difficult to plate, such as an aluminum layer or a titanium layer, the intermediate layer is a metal material that is easy to plate, and the metals that are easy to plate are typical of Cu and Au.
그리고 상기 보호피막 패턴을 형성하는 방법은 감광성 포토레지스트를 이용한 포토 리소그래피 방법을 사용하며, 상기 중간층을 형성하는 방법은 스퍼터링, PECVD 등의 건식증착법이다.The protective film pattern is formed by a photolithography method using a photosensitive photoresist, and the intermediate layer is formed by a dry deposition method such as sputtering or PECVD.
본 발명에 따르면, 도금이 쉬운 중간층을 형성하여 선택적 도금방법으로 도금층을 형성함으로써, 간단한 공정으로 멀티레이어 기판을 제조할 수 있고, 이에 따라 도금이 어려운 재료를 이용하여 멀티레이어 기판을 제조할 수 있는 효과가 있다.According to the present invention, by forming an intermediate layer easy to plate and forming a plating layer by a selective plating method, it is possible to manufacture a multilayer substrate in a simple process, thereby manufacturing a multilayer substrate using a material difficult to plate It works.
본 발명을 첨부된 도면을 참조하여 상세히 설명하면 다음과 같다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 1은 본 발명의 중간층 형성을 통한 선택적 도금을 이용한 멀티레이어 기판 제조방법을 나타내는 공정도이고, 도 2 내지 도 11은 제조과정을 도시한다.1 is a process chart illustrating a method for manufacturing a multilayer substrate using selective plating through the formation of an intermediate layer of the present invention, and FIGS. 2 to 11 illustrate a manufacturing process.
도 2 내지 도 3에 나타난 바와 같이, 준비된 기재(10)표면에 알루미늄층(20) 을 이베포레이션 방법 등을 이용하여 균일한 두께로 증착한다.2 to 3, the
다음으로, 도 4에 도시된 바와 같이 알루미늄층(20) 표면에 제1보호피막인 감광성 포토레지스트층(30)을 도포한 뒤에 포토리소그래피를 이용하여 패턴을 형성한다.Next, as shown in FIG. 4, after the photosensitive
도 5는 포토레지스트층(30) 패턴이 형성된 알루미늄층(20)에 양극산화공정을 실시한 모습을 나타낸다. 이러한 양극산화공정은 10V의 전압조건에서 옥살산(oxalic acid)을 용해제로 이용하여 진행될 수 있다. 포토레지스트층(30) 패턴이 형성되지 않은 부분의 알루미늄층(20)은 양극산화공정에 의해 산화되어 절연체인 산화층(20a)으로 변하고, 패턴이 형성된 곳은 산화되지 않은 알루미늄층인 제1금속배선(20b)이 된다. 이렇게 단일층으로 형성된 회로기판의 위에 새로운 회로기판을 형성하여 멀티레이어 기판을 제조하기 위해서는 알루미늄과 산화알루미늄이 혼재된 회로기판 위에 니켈금속 등을 도금하여 제2금속배선을 패터닝하여야 한다. 하지만 알루미늄과 산화알루미늄은 도금이 어려운 재질인 것이 문제이다.5 shows an anodization process on the
도 6 내지 도 7은 이러한 문제를 해결하기 위하여 포토레지스트층(30) 패턴을 제거하고, 제거된 전체면에 중간층(40)을 형성한 모습을 나타낸다. 이 중간층(40)은 도금이 쉬운 Au 또는 Cu 금속층이며, 스퍼터링 또는 PECVD 등의 건식증착방법을 이용하면 알루미늄 영역이나 산화알루미늄 영역에 안정적인 층을 형성할 수 있다.6 to 7 show a state in which the
다음으로, 도 8 내지 도 9에 도시된 바와 같이 중간층(40) 표면에 제2보호피막인 감광성 포토레지스트층(50)을 도포한 뒤에 포토리소그래피를 이용하여 패턴을 형성하고, 포토레지스트층(50) 패턴이 형성되지 않은 부분의 중간층(40)을 에칭하여 제거한다. 이때, 원하는 멀티레이어 기판의 형상에 따라 제1금속배선(20b)과 산화층(20a)의 적당한 영역 위에 중간층(40)이 남도록 조절할 수 있다. 또한, 포토레지스트층(50)을 제거하기 전에 중간층(40)이 제거되어 드러난 알루미늄층(20)에 추가공정을 실시한다면 잔류하는 중간층(40)의 손상 없이 공정을 진행할 수 있을 것이다.Next, as shown in FIGS. 8 to 9, after the photosensitive
도 10 내지 도 11은 포토레지스트층(50)을 제거하고, 잔류하는 중간층(40)위에 도금을 실시한 모습을 나타낸다. 도금이 어려운 알루미늄이나 산화알루미늄 영역을 제외한 중간층(40) 위에만 도금층(60)이 형성되며 제2금속배선으로 작용하는 도금층(60)은 니켈 도금일 수 있다. 이렇게 제1금속배선과 제2금속배선을 갖는 멀티레이어 기판을 제조할 수 있다.10 to 11 show that the
도 12는 본 발명의 다른 실시예를 나타내는 공정도이고, 도 13 내지 도 은 제조과정을 도시한다.12 is a process chart showing another embodiment of the present invention, Figures 13 to 13 show the manufacturing process.
도 13 내지 도 16은 상기 도 2 내지 도 5에서 설명한 것과 같다.13 to 16 are the same as those described with reference to FIGS. 2 to 5.
도 17 내지 도 18은 포토레지스트층(30) 패턴을 제거하고, 전면에 양극산화공정을 실시하여 절연층(70)을 형성한 모습을 나타낸다. 이로써 멀티레이어 기판의 층을 나누는 절연층이 형성된다.17 to 18 show a state in which the insulating
도 19 내지 도 20은 절연층(70)에 관통홀(80)을 형성하고, 전면에 중간층(40)을 형성한 모습을 나타낸다. 관통홀(80)은 멀티레이어 기판에서 다른층의 배선을 연결하는 역할을 한다. 중간층(40)은 도금이 쉬운 Au 또는 Cu 금속층이 며, 스퍼터링 또는 PECVD 등의 건식증착방법을 이용하면 알루미늄 영역이나 산화알루미늄 영역에 안정적인 층을 형성할 수 있다.19 to 20 illustrate a through
이후에 실시하는 도 21 내지 도 24는 상기 도 8 내지 도 11에서 설명한 것과 같다.21 to 24 will be described later with reference to FIGS. 8 to 11.
이상에서는 본 발명을 특정의 바람직한 실시예에 대해서 도시하고 설명하였다. 그러나, 본 발명은 상술한 실시예에만 국한되는 것은 아니며, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자라면 본 발명의 기술적 사상을 벗어남이 없이 얼마든지 다양하게 변경실시할 수 있을 것이다. 따라서 본 발명의 권리범위는 특정 실시예에 한정되는 것이 아니라, 첨부된 특허청구범위에 의해 정해지는 것으로 해석되어야 할 것이다.In the above, the present invention has been shown and described with respect to certain preferred embodiments. However, the present invention is not limited only to the above-described embodiment, and those skilled in the art to which the present invention pertains can make various changes without departing from the technical spirit of the present invention. Therefore, the scope of the present invention should not be limited to the specific embodiments, but should be construed as defined by the appended claims.
도 1은 본 발명의 중간층 형성을 통한 선택적 도금을 이용한 멀티레이어 기판 제조방법을 나타내는 공정도이다.1 is a process chart showing a multilayer substrate manufacturing method using selective plating through the formation of an intermediate layer of the present invention.
도 2 내지 도 11은 도 1의 제조방법으로 멀티레이어 기판을 제조하는 과정을 나타내는 도면이다.2 to 11 are views showing a process of manufacturing a multilayer substrate by the manufacturing method of FIG.
도 12는 본 발명의 다른 실시예에 의한 멀티레이어 기판 제조방법을 나타내는 공정도이다.12 is a process chart showing a multilayer substrate manufacturing method according to another embodiment of the present invention.
도 13 내지 도 24는 도 12의 제조방법으로 멀티레이어 기판을 제조하는 과정을 나타내는 도면이다.13 to 24 are views illustrating a process of manufacturing a multilayer substrate by the manufacturing method of FIG.
< 도면의 주요부분에 대한 부호의 설명 ><Description of Symbols for Major Parts of Drawings>
10: 기재 20: 알루미늄층10: base material 20: aluminum layer
30, 50: 포토레지스트층 40: 중간층30, 50: photoresist layer 40: intermediate layer
60: 도금층 70: 절연층60: plating layer 70: insulating layer
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