1326492 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種薄膜電晶體（thin film transistor， TFT)製程。 【先前技術】 目前’液晶顯示器（liquid crystal display, LCD )逐漸 取代用於電腦之傳統陰極射線管（cath〇de ray tube，crt) 顯示器。因液晶顯示器具輕、薄、小等特點，使其非常適 合應用於桌上型電腦、膝上型電腦、個人數位助理（pers〇nal digital assistant，PDA)、便攜式電話、電視及多種辦公自 動化與視聽設備中。液晶面板係液晶顯示器之一主要元 件’其一般包括一薄膜電晶體基板、一彩色濾光片基板及 夾於該薄膜電晶體基板與該彩色濾光片基板間之液晶層， 其中該薄膜電晶體基板包括一由複數薄膜電晶體組成之薄 膜電晶體陣列。 請參閱圖1，係一種先前技術之薄膜電晶體之結構示 思圖。該薄膜電晶體包括一位於絕緣基板11〇上之閘極 120、一位於該閘極12〇及該絕緣基板11〇上之閘極絕緣層 130、一位於該閘極絕緣層i3〇上之半導體層ι4〇、一位二 該半導體層140及該閘極絕緣層13〇上之源極15〇與汲極 160。通常該閘極12〇與一提供掃描訊號之掃描線（圖未示） 連接，為降低該掃描訊號RC延遲（電阻與電容構成之迴 路所產生之對訊號之延遲效果），需降低閘極12〇之電阻， 因此業界常採用銅等低電阻材質製造薄膜電晶體之閘極 7 1326492 120。 惟’當採用銅材質製造閘極12()時，因銅與絕緣基板 0門之附著力不佳，易導致閘極12〇剝離絕緣基板。 另’因·薄膜f晶體散熱性差’在長時間電訊號操作下，其 受周圍環境溫度升高之影響’可能會解離出銅離子，銅離 子在電壓驅動了會擴散至閘極絕緣I 130,41進入半導 體層140’產生銅污染現象’從而導致薄膜電晶體特性改 變，可靠性變差。 為解決上述問題，業界常採用另一方法製造薄膜電晶 體之閘極20’ _ 2係該製程之流程圖，其包括以下步驟： 於絕緣基板之表面依序沉積三層金屬層及一光阻層 (si);曝光並顯影該光阻層（S2);蝕刻該三層金屬^ (S3);移除剩餘光阻層（S4)。詳述如下： 日 步驟S1 :請參閱圖3，提供一絕緣基板21〇，於該基 板210 ★之表面依序沉積一第一金屬層220,—第二金屬^ 230’一第三金屬層24〇及一光阻層25〇。該第一金屬層2如 ^材質為鈦’其與絕緣基板210具良好之附著能力。該第 金屬層230之材質為銅，其具較低之電阻。該第三金 層240之材質為鈦，其可抗銅離子之擴散。 :、步驟S2:請參閱圖4,提供一光罩（圖未示），藉由 ίο光。罩對該光阻層250進行曝光，並顯影曝光後之光^層 步驟S3 :請參閱圖5，以所剩餘光阻層25〇為遮罩， 用/.，、、式餘刻法钱刻該第—金屬層、第二金屬層23〇 8 1326492 及第三金屬層240,進而形成閘極2〇。 =.驟以·請參閱圖6，移除該剩餘光阻層250。 惟’因銅為不易鞋岁丨丨夕人e # 金屬，其蝕刻速率小於鈦之蝕 全屬I。 屬層220、第二金屬層230及第三 金屬層240時，第二金属展9 金屬層230破蝕刻掉的金屬少，會造 烕第一金屬層230外伸，德蜻力姑 M g* p + 设#在該閘極20上覆蓋閘極絕緣 曰，一’易在閘極20與閘極絕緣層之間產生孔洞27〇 (如圖 極絕：厚？孔’同270易導致閘極絕緣層之斷裂，後續在閘 ，= 極與没極時，亦會導致源極或没極之斷 體問極製程之可靠性。 體失效，降低該薄膜電晶 【發明内容】 有鐘於此，提供一種可靠性康含 程實為必要。 Λ性較回之薄膜電晶體閘極製 有鐘於此’提供一種可靠性齡t 為必要。 罪注較呵之溥膜電晶體製程亦 ”-種薄膜電晶體問極製程，其包括以下步驟：提供一 絕緣基板，於該絕緣基板之表面依岸 下漸增之至少二光阻層；曝光並率自上而 ”，員办該光阻層’剩餘光阻 層見度自上而下遞減；依序沉積多層金屬層於光阻層及未 被先阻層覆蓋之絕緣基板表面；移除該光阻層及該光阻層 上之多層金制，剩餘之多層金屬層即為薄二 極，其寬度自上而下遞增。 Μ -種薄膜電晶體製程’其包括以下步驟：提供一邑緣 基板，於該絕緣基板之表面依序形成顯影速率自上而下漸 9 1326492 增之至少二光阻層；曝光並顯影該光阻層，剩餘光阻層寬 度自上而下遞減；依序沉積多層金屬層於光阻層及未^光 阻層覆蓋之絕緣基板表面；移除該光阻層及該光阻層上之 ^層金制，剩餘之多層金屬層即為薄膜電晶體之^極， •其寬度自上而下遞增；沉積一閘極絕緣層於該絕緣基板 上；、沉積-半導體材質層，圖案化該半導體材質層，進而 形成一半導體層；沉積-金屬材質層’圖案化該金屬材質 層，進而形成-源極及一沒極；沉積一鈍化層，圖案化該 純化層，進而形成一連接孔。 相較於先前技術，本發明之薄膜電晶體及其閘極製 程，係利用顯影速率不同之至少二光阻層，使曝光顯影後 之剩餘光阻層寬度自上而下遞減，於未被剩餘光阻層覆蓋 之、”邑緣基板上形成由多層金屬構成之閘極時，因寬度自上 而下遞減之剩餘光阻層之阻擋，該閘極寬度自上：下遞 增二從而可避免於該間極與閘極絕緣層間產生孔洞，減少 鲁孔洞引起之閘極絕緣層、源極或沒極之斷裂，進而減少薄 膜電晶體之失效’提高薄膜電晶體製程之可靠性。 【實施方式】 、睛參閱第8目，係本發明薄膜電晶體製程一較佳實施 方式之流程圖’其包括以下步驟：於絕緣基板之表面形成 顯影速率自上而下漸增之二光阻層（S11);曝光並顯影該 j阻層（S12);沉積三層金屬層於光阻層及未被光阻層 覆盍之絕緣基板表面（S13);移除該光阻層及沉積於該光 阻層上之三層金屬層，剩餘三層金屬層即為閘極（S14); 一调搞閘極、邑緣層（S15);形成一半導體層（S16);形成 i sW及w及極（S17);沉積一鈍化層並形成一連接孔 Cbl8)。詳述如下： v驟S11 .請參閱圖9，提供一絕緣基板4卜 1二英^明材質。於該絕緣基板41表面依㈣成第 二先阻:〇及第二光阻層422。該第一光阻層420及第 :於“=皆為正光阻’且第—光阻層42G之顯影速率 第二L :光阻層422之顯影速率；該第—光阻層420及 :先阻層422係旋轉塗佈形成，該第 二光阻層422之厚度基本相同。 2〇及弟 未干Γ::1】·請參閱圖10’藉由一具透光圖案之光罩(圖 光阻層420及第二光阻層422進行曝光， 塗佈顯影液，使阻層曝光’之後於光阻層上 溶於顯影液時，因第f光阻：：顯影。曝光部份之光阻層 阻層422之顯影速ί^層之顯影速率大於第二光 第二光阻声422之暖止 光阻層420之曝光部份必然比 不過导丄 部份顯影要快’只需控制顯影時間 即剩餘第二光=二成;f〜自上而下遞減之結構， Sn* 見度小於第二光阻層422之寬度。 -第二層: 422 Ά ^ 及苐二金屬層434於該第二光阻声 及未破剩餘光阻層覆蓋之絕緣基板Ο表面 : 屬層430之材質可為鈦、 X弟金 氮化鈦等之一種或數 鎢、顏、氮化鉬、氮化妲或 ㈣之組合’其與絕緣基板41具良好附 11 著力。該第二金屬層432 該第三金屬層434之材質J質為銅，其為低電阻材質。 氮化組-或氮化鈦等之、絡、嫣、銷、氮化銷、 擴散。，第-金屬層430= 合，其可抗鋼離子之 亦可為不同之材質金屬層434可為同-材質， 及第三金屬声金屬層43〇、第二金屬層432 阻層422厚度之和的二八 m 蓋之絕緣基板41表^'。沉積至純㈣光阻層覆 之光阻層阻擋，且c層，因寬度自上而下遞減 度，其靠近光阻層之全該第一光阻層420之厚 <金屬層漸漸變薄，從而該三層金屬層 又 遞增’且其邊緣為一光滑斜面。 步驟S14:請參閱圖12，將絕緣基板Ο投入剝離液 剝離液係丙嗣。因第-光阻層420及第二光阻層似 易溶於剝離液而第一金屬層430、第二金屬層432及曰第三 金屬層434不易溶於_液’沉積於第：光阻層422表: 金屬層43〇、第二金屬層432及第三金屬層隨 第-光阻層420及第二光阻層422之溶解而剝^。取出該 絕緣基板41並清洗、吹乾，該絕緣基板41表面剩餘 一金屬層430、第二金屬層432及第三金屬層434即為 極43’該閘極43寬度自上而下遞增且其邊緣為一光滑斜 面。 步驟S15 .請參閱圖13，沉積一覆蓋該閘極之閘 12 1326492 =緣層44於該崎基板41上，㈣極絕㈣44 化學軋相沉積形成之氮化矽結構。 步-驟S16··請參閱圖14，沉積一半導體材質及一第三 圖未示）於該閘極絕緣層44之表面，並藉由一光 ^一(=未示）對該第三光阻層進行曝光，並顯影曝光後之 第二先阻層，然、後以剩餘第三光阻層為遮罩 方法颠刻該半導體材質，進而形成一半導體層465 :料 導體材質係藉由化學氣相沉積形成之非晶矽結構。 +步驟S17:請參閱圖15，沉積一源/汲極金屬材質層及 -第四光阻層（圖未示）於該半導體@ 45及閘極絕緣層 44之上’該源/汲極金屬材質層係藉由化學氣相沉積形成 之鉬結構’藉由-光罩（圖未示）對該第四光阻層曝光， 並顯，曝光後之第四光阻層，然後以剩餘第四光阻層為遮 罩，藉由濕蝕刻方法蝕刻該源/汲極金屬材質層，形成一源 極46及一汲極47，進而完成薄膜電晶體製程。 步驟S18 :請參閱圖16，沉積一鈍化層48及一第五 光阻層（圖未示）於該閘極絕緣層44、源極46及汲極47 上，藉由一光罩（圖未示）對該第五光阻層曝光，並顯影 曝光後之第五光阻層，然後以剩餘第五光阻層為遮罩，藉 由濕姓刻方法姓刻該鈍化層48，進而形成一連接孔48〇， 該連接孔480處曝露出該汲極46。 相較於先前技術，前述薄獏電晶體製程，係利用顯影 速率不同之二光阻層’使曝光顯影後之剩餘光阻層寬度= 上而下遞減，於未被剩餘光阻層覆蓋之絕緣基板上形成由 13 成之間.極43 : 度小於T層光阻層厚度，所形 可避免.於該祕43 漸增以緣為—光滑斜面，從而 、pm 與閘極絕緣層44間產生孔洞，減少 =問極絕緣層44、源極46或沒極47 減少f膜電晶體之失效，提高薄膜電晶體製程之可靠,Ϊ 緣美之薄臈電晶體製程亦可做其他變更’如：於絕 速；自上㈤ '成之光阻層可以是三層，該三層光阻之顯影 =自^而下漸增且皆為負光阻；所形成之多層金屬層亦 可為四層。 综上所述’本發明確已符合發明專利之要件，麦依法 θ出專利申4。惟，以上所述者僅爲本發明之較佳實施方 式，本發明之範圍並不以上述實财式纽，舉凡熟習本 案技藝之人士援依本發明之精神所作之等效修飾或變化， 皆應涵蓋於以下申請專利範圍内。 【圖式簡單說明】 圖1係一種先前技術薄膜電晶體之結構示意圖。 圖2係另一種先前技術薄膜電晶體閘極製程流程圖。 圖3係圖2所示薄膜電晶體閘極製程之沉積三層金屬層 及一光阻層步驟之示意圖。 圖4係圖2所示薄膜電晶體閘極製程之曝光並顯影光阻 層步驟之示意圖。 圖5係圖2所示薄膜電晶體閘極製程之蝕刻三層金屬層 步驟之示意圖。 14 1326492 /外、不，¾圖。 Ξ::::6所示之閘極上覆蓋閘極絕緣層之示意圖。 圖9二圖8所示薄膜電晶體製程之形成二二 不忍圖。 圖1〇係圖8所示薄膜電晶體製程之曝光並顯影光阻層步 鄉之示意圖。 圖11係圖8所示薄膜雷晶體激寂夕、、„接_ a八 一 、电日日篮I柱之/儿積二層金屬層步驟 之示意圖。 圖12係圖8所示薄膜電晶體製歡移除綠層及光阻層 上之三層金屬步驟之示意圖。 圖13係圖8所示薄膜電晶體製程之沉積閘極絕緣層步驟 之不意圖。 圖14係圖8所示薄膜電晶體製程之形成半導體層步驟之 示意圖。 圖15係圖8所示薄膜電晶體製程之形成源極及汲極步驟 之示意圖。 圖16係圖8所示薄膜電晶體製程之沉積鈍化層並形成連 接孔步驟之示意圖。 15 4201326492 【主要元件符號說明】 絕緣基板 41 第一光阻層 閘極. 43 第二光阻層 第一金屬層 « 430 第二金屬層 第三金屬層 434 閘極絕緣層 半導體層 45 源極 汲極 47 鈍化層 連接孔 480 422 432 44 46 481326492 IX. Description of the Invention: [Technical Field of the Invention] The present invention relates to a thin film transistor (TFT) process. [Prior Art] At present, liquid crystal display (LCD) is gradually replacing the conventional cathode ray tube (crt) display for computers. Due to the light, thin and small size of the liquid crystal display device, it is very suitable for use in desktop computers, laptop computers, personal digital assistants (PDAs), portable phones, televisions and various office automation systems. In audiovisual equipment. A liquid crystal panel is a main component of a liquid crystal display, which generally includes a thin film transistor substrate, a color filter substrate, and a liquid crystal layer sandwiched between the thin film transistor substrate and the color filter substrate, wherein the thin film transistor The substrate includes a thin film transistor array composed of a plurality of thin film transistors. Referring to Figure 1, there is shown a structural diagram of a prior art thin film transistor. The thin film transistor includes a gate 120 on the insulating substrate 11 , a gate insulating layer 130 on the gate 12 and the insulating substrate 11 , and a semiconductor on the gate insulating layer i3 . The layer 15i, the one of the semiconductor layer 140, and the source 15 〇 and the drain 160 of the gate insulating layer 13 are formed. Usually, the gate 12 is connected to a scan line (not shown) for providing a scan signal. To reduce the delay of the scan signal RC (the delay effect of the signal generated by the circuit formed by the resistor and the capacitor), the gate 12 needs to be lowered. 〇There is a resistor, so the industry often uses a low-resistance material such as copper to manufacture the gate of the thin-film transistor 7 1326492 120. However, when the gate 12 () is made of a copper material, the adhesion between the copper and the insulating substrate 0 is poor, and the gate 12 is easily peeled off from the insulating substrate. In addition, due to the poor heat dissipation of the film f crystal, under the long-term electric signal operation, it may be affected by the increase of the ambient temperature. 'The copper ion may be dissociated, and the copper ion will spread to the gate insulation I 130 when the voltage is driven. The entry of the semiconductor layer 140' into the copper contamination phenomenon is caused to cause a change in the characteristics of the thin film transistor, and the reliability is deteriorated. In order to solve the above problems, the industry often uses another method to manufacture the gate electrode of the thin film transistor 20' _ 2 is a flow chart of the process, which comprises the following steps: sequentially depositing three metal layers and a photoresist on the surface of the insulating substrate a layer (si); exposing and developing the photoresist layer (S2); etching the three-layer metal (S3); removing the remaining photoresist layer (S4). The following is a detailed description of the following: Step S1: Referring to FIG. 3, an insulating substrate 21 is provided, and a first metal layer 220 is sequentially deposited on the surface of the substrate 210. The second metal 230' is a third metal layer 24. 〇 and a photoresist layer 25〇. The first metal layer 2 is made of titanium, which has good adhesion to the insulating substrate 210. The material of the second metal layer 230 is copper, which has a low electrical resistance. The material of the third gold layer 240 is titanium, which is resistant to the diffusion of copper ions. :, step S2: Please refer to FIG. 4, a photomask (not shown) is provided, by ίο光. The mask is exposed to the photoresist layer 250, and the exposed light layer is step S3: Please refer to FIG. 5, and the remaining photoresist layer 25 is used as a mask, and the pattern is engraved with /., The first metal layer, the second metal layer 23〇8 1326492 and the third metal layer 240 further form a gate 2〇. =. Referring to Figure 6, the remaining photoresist layer 250 is removed. However, because copper is not easy to wear shoes, the etch rate is less than that of titanium. When the layer 220, the second metal layer 230, and the third metal layer 240 are formed, the metal of the second metal layer 9 is less etched away, and the first metal layer 230 is stretched out, and the German metal layer 230 is extended. p + 设置# covers the gate insulating 在 on the gate 20, and an 'easy to create a hole 27 闸 between the gate 20 and the gate insulating layer (as shown in the figure: thick? hole ' with 270 easy to cause gate The fracture of the insulation layer, subsequent to the gate, = pole and immersion, will also lead to the reliability of the source or the immersed body. The body failure, reduce the film of the crystal [invention] It is necessary to provide a kind of reliability. It is necessary to provide a reliability age t. It is necessary to provide a reliability age t. The transistor process includes the following steps: providing an insulating substrate, and increasing at least two photoresist layers on the surface of the insulating substrate; the exposure rate is from the top, and the photoresist layer is left The photoresist layer is reduced from top to bottom; multiple layers of metal layers are deposited on the photoresist layer in sequence. The surface of the insulating substrate covered by the layer; the photoresist layer and the plurality of layers of gold on the photoresist layer are removed, and the remaining plurality of metal layers are thin two poles, and the width thereof increases from top to bottom. Μ - a thin film transistor process The method comprises the steps of: providing a rim substrate, sequentially forming a development rate from the top to the bottom of the insulating substrate by at least two photoresist layers; exposing and developing the photoresist layer, and remaining photoresist layer Width decreasing from top to bottom; sequentially depositing a plurality of metal layers on the surface of the insulating substrate covered by the photoresist layer and the photoresist layer; removing the photoresist layer and the layer of gold on the photoresist layer, and remaining the plurality of layers The metal layer is the electrode of the thin film transistor, • its width is increased from top to bottom; a gate insulating layer is deposited on the insulating substrate; a deposition-semiconductor material layer is patterned, and the semiconductor material layer is patterned to form a semiconductor. a layer; a deposition-metal layer' patterning the metal material layer to form a source and a gate; depositing a passivation layer, patterning the purification layer to form a connection hole. Compared to the prior art, the present invention Film The crystal and its gate process are made by using at least two photoresist layers having different development rates, so that the width of the remaining photoresist layer after exposure and development is decreased from top to bottom, and is not covered by the remaining photoresist layer. When a gate composed of a plurality of layers of metal is formed, the barrier of the remaining photoresist layer is reduced from top to bottom in width, and the width of the gate is increased from upper to lower to avoid voids between the interlayer and the gate insulating layer. Reducing the breakdown of the gate insulating layer, source or immersion caused by the ruthenium hole, thereby reducing the failure of the thin film transistor, and improving the reliability of the process of the thin film transistor. [Embodiment] A flow chart of a preferred embodiment of the transistor process includes the steps of: forming a photoresist layer having a developing rate increasing from top to bottom on a surface of the insulating substrate (S11); exposing and developing the j resist layer (S12) Depositing three metal layers on the surface of the photoresist layer and the insulating substrate not covered by the photoresist layer (S13); removing the photoresist layer and three metal layers deposited on the photoresist layer, and remaining three layers of metal The layer is the gate (S14); The gate electrode and the germanium edge layer are first adjusted (S15); a semiconductor layer (S16) is formed; i sW and w and a pole (S17) are formed; a passivation layer is deposited and a connection hole Cbl8) is formed. The details are as follows: v Step S11. Referring to Fig. 9, an insulating substrate 4 is provided. The surface of the insulating substrate 41 is (four) formed into a second pre-resistance: a second photoresist layer 422. The first photoresist layer 420 and the first: the development rate of the photoresist layer 420 and the development rate of the first photoresist layer 42G: the development rate of the photoresist layer 422; the first photoresist layer 420 and the first The resist layer 422 is formed by spin coating, and the thickness of the second photoresist layer 422 is substantially the same. 2〇和弟未干Γ::1】·Please refer to FIG. 10' by a light-transmitting pattern mask (Fig. The photoresist layer 420 and the second photoresist layer 422 are exposed, and the developer is applied to expose the resist layer. After being dissolved on the photoresist layer on the photoresist layer, the photoresist is developed by the f-th photoresist: the exposed portion of the light The development speed of the resist layer 422 is higher than that of the second light second photoresist 422. The exposed portion of the warm photoresist layer 420 is necessarily faster than the conductive portion of the conductive layer 420. The time is the remaining second light = 20%; the structure of f~ decreases from top to bottom, the Sn* visibility is smaller than the width of the second photoresist layer 422. - The second layer: 422 Ά ^ and the second metal layer 434 The second photoresist sound and the insulating substrate covered by the unbroken residual photoresist layer : surface: the material of the genus layer 430 may be one of titanium, X di gold titanium nitride or the like, or tungsten, color, molybdenum nitride The combination of tantalum nitride or (4) has a good adhesion to the insulating substrate 41. The material of the second metal layer 432 is made of copper, which is a low-resistance material. Titanium nitride, etc., entanglement, enthalpy, pin, nitriding pin, diffusion. The first metal layer 430=, which can resist steel ions, can also be different materials. The metal layer 434 can be the same material, and The insulating substrate 41 of the twenty-eight m cover of the sum of the thicknesses of the three metal acoustic metal layers 43 and the second metal layer 432 is formed by a photoresist layer deposited on the pure (four) photoresist layer, and the c layer is The width is reduced from top to bottom, and the thickness of the first photoresist layer 420 is close to the photoresist layer. The metal layer is gradually thinned, so that the three metal layers are incremented again and the edge thereof is a smooth bevel. S14: Referring to Fig. 12, the insulating substrate is thrown into the stripping liquid stripping system. The first photoresist layer 420 and the second photoresist layer are soluble in the stripping liquid, and the first metal layer 430 and the second metal layer are formed. 432 and 曰 third metal layer 434 is not easily soluble in _ liquid' deposited on: photoresist layer 422 table: metal layer 43 〇, second metal layer 432 and The three metal layers are stripped with the dissolution of the first photoresist layer 420 and the second photoresist layer 422. The insulating substrate 41 is taken out and cleaned and dried, and a metal layer 430 and a second metal layer 432 remain on the surface of the insulating substrate 41. And the third metal layer 434 is the pole 43'. The width of the gate 43 is increased from top to bottom and its edge is a smooth slope. Step S15. Referring to Figure 13, deposit a gate covering the gate 12 1326492 = edge layer 44 on the Saki substrate 41, (d) extremely (four) 44 chemical rolling phase deposition of the tantalum nitride structure. Step - S16 · Please refer to Figure 14, depositing a semiconductor material and a third figure not shown) The surface of the insulating layer 44 is exposed to the third photoresist layer by a light (= not shown), and the exposed second resist layer is developed, and then the remaining third photoresist layer is The masking method inscribes the semiconductor material to form a semiconductor layer 465: the material of the material is an amorphous germanium structure formed by chemical vapor deposition. +Step S17: Referring to FIG. 15, a source/drain metal layer and a fourth photoresist layer (not shown) are deposited over the semiconductor @45 and the gate insulating layer 44. The source/drain metal The material layer is formed by chemical vapor deposition of a molybdenum structure by exposing the fourth photoresist layer by a photomask (not shown), and exposing the exposed fourth photoresist layer, and then remaining the fourth The photoresist layer is a mask, and the source/drain metal layer is etched by a wet etching method to form a source 46 and a drain 47, thereby completing the thin film transistor process. Step S18: Referring to FIG. 16, a passivation layer 48 and a fifth photoresist layer (not shown) are deposited on the gate insulating layer 44, the source 46 and the drain 47, by means of a mask (not shown). Exposing the fifth photoresist layer, and developing the exposed fifth photoresist layer, and then using the remaining fifth photoresist layer as a mask, and engraving the passivation layer 48 by a wet surname method to form a A connection hole 48 is formed, and the drain 46 is exposed at the connection hole 480. Compared with the prior art, the foregoing thin germanium transistor process uses the two photoresist layers with different development rates to reduce the width of the remaining photoresist layer after exposure and development = up and down, and the insulation is not covered by the remaining photoresist layer. The surface of the substrate is formed between 13 and 43. The thickness is less than the thickness of the T-layer photoresist layer, and the shape can be avoided. The edge of the secret 43 is gradually increased—the smooth bevel, and thus the pm and the gate insulating layer 44 are formed. Holes, reduction = the polarity of the insulating layer 44, the source 46 or the immersion 47 reduce the failure of the f-film transistor, improve the reliability of the thin-film transistor process, and other changes can be made in the process of thin-film transistor. In the absolute speed; from the top (five) 'the photoresist layer can be three layers, the development of the three-layer photoresist = from the bottom and gradually increase and are negative photoresist; the multilayer metal layer can also be four layers . In summary, the present invention has indeed met the requirements of the invention patent, and the law is based on patent application 4. However, the above description is only a preferred embodiment of the present invention, and the scope of the present invention is not limited to the above-described embodiments, and those skilled in the art will be able to make equivalent modifications or variations in accordance with the spirit of the present invention. It should be covered by the following patent application. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic view showing the structure of a prior art thin film transistor. 2 is a flow chart of another prior art thin film transistor gate process. FIG. 3 is a schematic view showing the steps of depositing a three-layer metal layer and a photoresist layer in the thin film transistor gate process shown in FIG. Figure 4 is a schematic illustration of the steps of exposing and developing the photoresist layer of the thin film transistor gate process of Figure 2. Fig. 5 is a schematic view showing the steps of etching a three-layer metal layer in the thin film transistor gate process shown in Fig. 2. 14 1326492 / outside, no, 3⁄4 diagram. A schematic diagram of the gate insulating layer covered by the gate shown by Ξ::::6. The formation of the thin film transistor shown in Fig. 9 and Fig. 8 is not tolerated. Fig. 1 is a schematic view showing the step of exposing and developing the photoresist layer in the thin film transistor process shown in Fig. 8. Figure 11 is a schematic view showing the steps of the thin film lightning crystal shown in Figure 8, the _ _ a 八, the electric day and the day I column / the second layer of the metal layer. Figure 12 is the thin film transistor shown in Figure 8. FIG. 13 is a schematic view showing the steps of removing the three layers of metal on the green layer and the photoresist layer. FIG. 13 is a schematic view showing the steps of depositing the gate insulating layer of the thin film transistor process shown in FIG. 8. FIG. FIG. 15 is a schematic diagram showing the steps of forming a source and a drain of the thin film transistor process shown in FIG. 8. FIG. 16 is a deposition passivation layer of the thin film transistor process shown in FIG. 15 4201326492 [Description of main component symbols] Insulating substrate 41 First photoresist layer gate. 43 Second photoresist layer First metal layer « 430 Second metal layer Third metal layer 434 Gate insulating layer semiconductor Layer 45 source drain 47 passivation layer connection hole 480 422 432 44 46 48
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