KR20100005329A - Digital to analog converter for a continuous time sigma delta modulator - Google Patents

Abstract

PURPOSE: A digital to analog converter for a continuous time sigma delta modulator is provided to improve performance of the converter by controlling a duty ratio of a clock signal. CONSTITUTION: An adding unit(110) adds up a continuous time analog input signal and an analog signal outputted from a digital to analog converter(140). A loop filter(120) includes at least one integrator to perform an integral operation. The integrator is comprised of an operational amplifier and a capacitor. A quantizer(130) performs the quantization operation based on the signal outputted from the loop filter and outputs the digital signal. The digital signal is comprised of one bit or plural bits. The digital to analog converter outputs the analog signal based on the digital signal outputted from the quantizer.

Description

DIGITAL TO ANALOG CONVERTER FOR A CONTINUOUS TIME SIGMA DELTA MODULATOR}

Embodiments of the present invention relate to sigma delta modulators and, in particular, to a digital to analog converter (DAC) for a continuous time sigma delta modulator.

Generally, sigma delta modulation can be used for some type of analog to digital or digital to analog conversion, and sigma delta modulators use complementary metal oxide semiconductors (CMOS). Can be easily implemented.

Continuous time sigma delta modulator receives continuous analog input signal as opposed to discrete time analog input signal and outputs digital data. Generally, analog to digital converter (ADC) It includes.

The digital-to-analog converter in the sigma delta modulator generates an analog signal corresponding to the input digital signal. If the digital-to-analog converter does not properly generate an analog signal corresponding to the digital signal, the performance of the sigma delta modulator may be poor. Therefore, there is a need for a digital-to-analog converter capable of properly generating an analog signal corresponding to a digital signal.

SUMMARY OF THE INVENTION An object of the present invention is to provide a digital to analog converter (DAC) for a continuous time sigma delta modulator capable of properly generating an analog signal corresponding to a digital signal in order to solve the problems of the prior art. have.

Another object of the present invention is to provide a sigma delta modulator including the digital-to-analog converter.

Still another object of the present invention is to provide an integrated circuit including the sigma delta modulator.

In order to achieve the above object, a digital-to-analog converter (DAC) for a continuous time sigma delta modulator of the present invention is a clock signal having at least one capacitor and a clock period composed of first and second time intervals. Based on charging the at least one capacitor during the first time interval and providing at least a portion of the current charged in the at least one capacitor to the loop filter during the second time interval, the current remaining in the at least one capacitor or And a controller for controlling the first and second time intervals so that a voltage satisfies a predetermined criterion. For example, the clock signal may correspond to a first logic level in the first time period and correspond to a second logic level in the second time period.

According to an embodiment, the controller may control the first and second time periods to minimize an error caused by the current or voltage remaining in the at least one capacitor.

According to an embodiment, the controller may be configured to charge the at least one capacitor or provide at least a portion of the current charged in the at least one capacitor to the loop filter based on the clock signal. It may include a clock generator for controlling at least one end of the switching unit and the duty ratio of the reference clock to provide the clock signal to the switching unit.

According to an embodiment, the controller may charge the at least one capacitor or provide at least a portion of the current charged in the at least one capacitor based on the digital signal output from the quantizer.

According to an embodiment, when the number of the at least one capacitor is two or more, the at least one capacitor may be connected in parallel, and each of the at least one capacitor is operated independently based on a digital signal output from a quantizer. Can be.

In order to achieve the above object, the digital-to-analog converter of the present invention uses at least one capacitor and the at least one capacitor during the first time interval based on a clock signal having a clock period consisting of first and second time intervals. Charge and provide at least a portion of the current charged in the at least one capacitor to the loop filter during the second time period, and control the first and second time periods based on the current or voltage remaining in the at least one capacitor. It includes a control unit. For example, the clock signal may correspond to a first logic level in the first time period and correspond to a second logic level in the second time period.

According to an embodiment, the controller may control the first and second time periods to minimize an error caused by the current or voltage remaining in the at least one capacitor.

According to an embodiment, the controller may be configured to charge the at least one capacitor or provide at least a portion of the current charged in the at least one capacitor to the loop filter based on the clock signal. A switching unit for switching at least one end and a clock generator for providing the clock signal to the switching unit by controlling the duty ratio of the reference clock based on the current or voltage remaining in the at least one capacitor.

According to an embodiment, the controller may charge the at least one capacitor or provide at least a portion of the current charged in the at least one capacitor based on the digital signal output from the quantizer.

According to an embodiment, when the number of the at least one capacitor is two or more, the at least one capacitor may be connected in parallel, and each of the at least one capacitor is independent based on a digital signal output from a quantizer. It can be operated as.

In order to achieve the above object, the continuous time sigma delta modulator of the present invention includes a loop filter including at least one integrator, a quantizer for performing a quantization operation based on a signal output from the loop filter, and outputting a digital signal; And a digital-to-analog converter (DAC), wherein the digital-to-analog converter includes at least one capacitor operated based on the digital signal and a clock period having first and second time intervals. Charging the at least one capacitor during the first time period based on a signal and providing a loop filter with at least a portion of the current charged in the at least one capacitor during the second time period and remaining in the at least one capacitor. Controlling the first and second time intervals based on current or voltage It includes a control unit.

According to an embodiment, when the number of the at least one capacitor is two or more, the at least one capacitor may be connected in parallel, and each of the at least one capacitor may be operated independently based on the digital signal.

According to an embodiment, the controller may control the first and second time periods so that a current or voltage remaining in the at least one capacitor satisfies a predetermined criterion. For example, the controller may minimize an error caused by current or voltage remaining in the at least one capacitor.

In an integrated circuit (IC) including a continuous time sigma delta changer of the present invention to achieve the another object, the sigma delta modulator includes at least one integrator loop filter, from the loop filter A quantizer for outputting a digital signal based on the output signal, and a digital-to-analog converter (DAC), wherein the digital-to-analog converter includes at least one capacitor operated based on the digital signal; At least a portion of the current charged in the at least one capacitor during the first time period and based on a clock signal whose clock period consists of first and second time periods and during the second time period. Is provided to the loop filter, and current or electric current remaining in the at least one capacitor. And a controller for controlling the first and second time intervals based on the pressure.

For example, the integrated circuit includes a sensor device used for applications such as image sensing, infrared sensing, and bio sensing, Code Division Multiple Access (CDMA), Global System for Mobile telecommunication (GSM), Wireless Local Area Network (WLAN), It may be included in a wireless receiver device including digital multimedia broadcasting (DMB) and Bluetooth.

According to an embodiment, the controller may control the first and second time periods to minimize an error caused by the current or voltage remaining in the at least one capacitor.

One embodiment of the present invention can appropriately generate an analog signal corresponding to the input digital signal by controlling the duty ratio of the clock signal.

In addition, an embodiment of the present invention may improve the performance of a digital to analog converter (DAC) by controlling the duty ratio of the clock signal.

Since descriptions of embodiments of the present invention are merely illustrated for structural to functional descriptions of the present invention, the scope of the present invention should not be construed as limited by the embodiments described in the present invention. That is, the embodiments of the present invention may be variously modified and may have various forms, and thus, it should be understood that the present invention includes equivalents capable of realizing the technical idea of the present invention.

On the other hand, the meaning of the terms described in the present invention will be understood as follows.

Terms such as “first” and “second” are used to distinguish one component from other components, and the scope of the present invention should not be limited by these terms. For example, the first component may be named a second component, and similarly, the second component may also be named a first component.

The term “and / or” should be understood to include all combinations that can be presented from one or more related items. That is, the meaning of “first item, second item and / or third item” not only includes the first, second or third item, but also presents from two or more of the first, second and third items. It means a combination of all possible items.

When a component is referred to as being "connected" to another component, it should be understood that there may be other components in between, although it may be directly connected to the other component. On the other hand, when a component is said to be "directly connected" to another component, it should be understood that there is no other component in between. On the other hand, other expressions describing the relationship between the components, such as "between" and "immediately between" or "neighboring to" and "directly neighboring to", should be interpreted as well.

Singular expressions described herein are to be understood to include plural expressions unless the context clearly indicates otherwise, and the terms "comprise" or "having" include elements, features, numbers, steps, operations, and elements described. It is to be understood that the present invention is intended to designate that there is a part or a combination thereof, and does not exclude in advance the possibility of the presence or addition of one or more other features or numbers, steps, actions, components, parts or combinations thereof. .

Each step described in the present invention may occur out of the stated order unless the context clearly dictates the specific order. That is, each step may occur in the same order as specified, may be performed substantially simultaneously, or may be performed in the reverse order.

Unless otherwise defined, all terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present invention belongs. Terms such as those defined in the commonly used dictionaries should be construed as having meanings consistent with the meanings in the context of the related art and shall have ideal or overly formal meanings unless expressly defined in the present application. It cannot be interpreted.

1 is a block diagram illustrating a continuous time sigma delta modulator according to an embodiment of the present invention.

Referring to FIG. 1, the continuous time sigma delta modulator 100 includes an adder 110, a loop filter 120, a quantizer 130, and a digital-to-analog converter (DAC) 140. do.

The adder 110 adds the continuous time analog input signal x (t) with the analog signal y (t) output from the digital-to-analog converter 140.

The loop filter 120 may include at least one integrator and performs an integration operation. For example, the integrator may be implemented with an operational amplifier and a capacitor.

The quantizer 130 outputs a digital signal y (n) by performing a quantization operation based on the signal output from the loop filter 120. According to an embodiment, the digital signal y (n) may be implemented with 1 bit and in another embodiment, the digital signal y (n) may be implemented with a plurality of bits.

The digital-analog converter 140 outputs an analog signal y (t) based on the digital signal y (n) output from the quantizer 130. Hereinafter, the operation of the digital-to-analog converter 140 will be described with reference to FIGS. 2 to 6.

FIG. 2 is a block diagram illustrating an embodiment of the digital-to-analog converter of FIG. 1.

2, the digital-analog converter 140 includes a capacitor 210 and a controller 220, and the controller 220 includes a clock generator 222 and a switching unit 224.

The controller 220 controls the operation of the capacitor 210 based on the digital signal output from the quantizer 130. That is, the capacitor 210 is operated based on the digital signal output from the quantizer 130.

According to an embodiment, when the digital signal y (n) corresponds to logic high, the capacitor 210 may be charged or discharged by the clock generator 222 and the switching unit 224, and the digital When the signal y (n) corresponds to a logic low, the capacitor 210 may not be charged or discharged.

According to another exemplary embodiment, when the digital signal y (n) corresponds to logic high, the capacitor 210 may be charged or discharged by the clock generator 222 and the switching unit 224. When the digital signal y (n) corresponds to a logic low, the capacitor 210 may be simply charged. The charging of the capacitor 210 is intended to increase efficiency later when the digital signal corresponds to logic high.

The controller 220 charges the capacitor 210 during the first time period based on the clock signal whose clock period is composed of the first and second time periods, and at least the current of the current charged in the capacitor 210 during the second time period. A part is provided to the loop filter, and the first and second time periods are controlled to allow the current or voltage remaining in the capacitor 210 to satisfy a predetermined criterion. For example, the first time period may indicate a period in which the clock signal corresponds to a logic high, and the second time period may indicate a period in which the clock signal corresponds to a logic low.

The clock generator 222 controls the duty ratio of the reference clock REF_CLK to provide the clock signal CLK to the switching unit 224. The clock period of the clock signal CLK has first and second time intervals. For example, the clock signal CLK may correspond to a first logic level (eg, logic high) in a first time period and to a second logic level (eg, logic low) in a second time period. May correspond.

According to an embodiment, the reference clock signal REF_CLK may be generated by the digital-to-analog converter 140, and according to another embodiment, the reference clock signal REF_CLK may be input from the outside.

The switching unit 224 includes first and second switches 224a and 224b and is operated based on the clock signal CLK output from the clock generator 230. For example, when the clock signal CLK corresponds to the first logic level (eg, logic high), the switching unit 220 may open both ends of the capacitor 210 to charge the capacitor 210. And the second reference voltages VREF1 and VREF2, and when the clock signal CLK corresponds to the second logic level (eg, logic low), the switching unit 220 is connected to the capacitor 210. In order to provide the charged current to the loop filter 120, both ends of the capacitor 210 may be connected to the summation unit 110 and the third reference voltage (eg, the ground voltage VSS).

According to an exemplary embodiment, the first to third reference voltages VREF1, VREF2, and VSS may be changed according to the digital signal y (n) output from the quantizer 130. This is for efficiently controlling the charging amount or charging speed of the capacitor 210.

3A and 3B are graphs showing the voltage and current of a capacitor in a digital-analog converter according to a clock signal.

3A assumes that the duty ratio of the clock signal is 50%, and FIG. 3B assumes the duty ratio of the clock signal is 25%.

3A and 3B, the controller 220 charges the capacitor 210 during the first time period t1 and discharges the capacitor 220 during the second time period t2. The first time point tp1 represents a time point at which the capacitor 210 has the highest voltage during one period of the clock signal CLK, and the second time point tp2 filters at least a part of the current charged in the capacitor 210 in a loop filter. A time point provided to 120 is shown.

Referring to FIGS. 3A and 3B, the capacitor 210 at the second time point tp2 according to the ratio of the first and second time intervals t1 and t2 (that is, the duty ratio of the clock signal CLK). The error of the digital-to-analog converter 140 due to a current or voltage may be different. That is, the error of the digital-to-analog converter 140 due to the current 320 or the voltage 310 of the capacitor 210 at the second time point tp2 shown in FIG. 3B may be caused by the second time point tp2 shown in FIG. 3A. May be less than the error of the digital-to-analog converter 140 by the current 320 or voltage 310 of the capacitor 210.

3A and 3B, the second and third time intervals t1 and t2 are generated at the second time point tp2 according to the ratio (that is, the duty ratio of the clock signal CLK). The error of the digital-to-analog converter 140 due to jitter may be different. That is, the error of the digital-to-analog converter 140 caused by the jitter of the second time point tp2 shown in FIG. 3B is the error of the digital-to-analog converter 140 caused by the jitter of the second time point tp2 shown in FIG. 3A. May be less than an error.

As a result, the controller 210 charges the capacitor 210 during the first time period t1 and provides the loop filter 120 with at least a portion of the current charged in the capacitor 210 during the second time period t2. The first and second time periods t1 and t2 are controlled to allow the current 320 or the voltage 310 remaining in the capacitor 210 to satisfy a predetermined criterion.

According to an embodiment, the controller 210 may control the first and second time intervals t1 and t2 so as to minimize an error generated due to the current or voltage remaining in the capacitor 210. That is, the digital-to-analog converter 140 may minimize the error in consideration of the voltage at the first time point tp1 and the current 320 or voltage 310 at the second time point tp2.

4 is a block diagram illustrating another embodiment of the digital-to-analog converter of FIG. 1.

Referring to FIG. 4, the digital-to-analog converter 140 includes a capacitor 410 and a controller 420, and the controller 420 includes a clock generator 422 and a switching unit 424. Unlike FIG. 2, the switching unit 424 may connect one end of the capacitor 410 to the reference voltage VREF or the sum unit 110 based on the clock signal CLK. That is, the switching unit 424 may switch one end of the capacitor 410.

Since the capacitor 410 and the controller 420 operate substantially the same way as described in FIG. 2, a detailed description thereof will be omitted.

5 is a block diagram illustrating yet another embodiment of the digital-to-analog converter of FIG. 1.

Referring to FIG. 5, the digital-analog converter 140 includes a plurality of capacitors 510 and a controller 520, and the controller 520 includes a clock generator 522 and a plurality of switching units 524. do. Unlike FIG. 2, the plurality of capacitors 510 may be connected in parallel, and the digital signal y (n) output from the quantizer 130 may include a plurality of bits.

According to an embodiment, when the number of bits constituting the digital signal y (n) corresponds to the number of the capacitors 510, the plurality of capacitors 510 is the digital signal y (n). Each operation may be performed according to the bits constituting the < RTI ID = 0.0 > For example, when the digital signal y (n) corresponds to '010', the first and third capacitors 510a and 510c may not operate and the second capacitor 510b may operate. .

According to another embodiment, if the number of bits of the digital signal y (n) does not correspond to the number of capacitors 510, the controller 520 decodes the digital signal y (n) to decode the plurality of capacitors. The fields 510 can be operated independently. For example, when the digital signal y (n) corresponds to '10', the controller 520 decodes the digital signal y (n) to generate an operation signal of '010' to generate the first and the first signals. The three capacitors 510a and 510c may not operate and the second capacitor 510b may operate.

Since the plurality of capacitors 510 and the controller 520 operate substantially in the same manner as described in FIG. 2, a detailed description thereof will be omitted.

FIG. 6 is a block diagram illustrating another embodiment of the digital-analog converter of FIG. 1.

Referring to FIG. 6, the digital-to-analog converter 140 includes a capacitor 610 and a controller 620, and the controller 620 includes a clock generator 622 and a switching unit 624. Unlike FIG. 2, the clock generator 622 may provide a clock signal CLK to the switching unit 6240 by controlling the duty ratio of the reference clock REF_CLK based on the current or voltage of the capacitor 610. That is, the controller 620 illustrated in FIG. 6 may dynamically control the first and second time sections of the clock signal CLK based on the current or voltage of the capacitor 610.

In addition, the capacitor 610 and the controller 620 of FIG. 6 may be implemented in substantially the same manner as in FIGS. 4 to 5.

FIG. 7 is a block diagram illustrating an integrated circuit including the sigma delta modulator of FIG. 1.

Referring to FIG. 7, the integrated circuit 700 includes a sigma delta modulator 110 that performs a sigma delta modulation based on an analog signal x (t) to provide a digital signal y (n).

According to an embodiment, the integrated circuit 700 may be included in a sensor device used for applications such as image sensing, infrared sensing, and bio sensing. According to another embodiment, the integrated circuit 700 may include a code division (CDMA). It may be included in a wireless receiver device including multiple access (Global System for Mobile telecommunication), wireless local area network (WLAN), digital multimedia broadcasting (DMB), and Bluetooth.

Although described above with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified and changed within the scope of the invention without departing from the spirit and scope of the invention described in the claims below I can understand that you can.

Embodiments of the present invention presented above may have an effect including the following advantages. However, all embodiments of the present invention should not be understood that the scope of the present invention is not limited by this, because it does not mean that all embodiments or specific embodiments of the present invention should include only the following advantages.

One embodiment of the present invention can appropriately generate an analog signal corresponding to the input digital signal by controlling the duty ratio of the clock signal.

In addition, an embodiment of the present invention may improve the performance of a digital-to-analog converter (DAC) by controlling the duty ratio of the clock signal.

1 is a block diagram illustrating a continuous time sigma delta modulator according to an embodiment of the present invention.

FIG. 2 is a block diagram illustrating an embodiment of the digital-to-analog converter of FIG. 1.

3A and 3B are graphs showing the voltage and current of a capacitor in a digital-analog converter according to a clock signal.

4 is a block diagram illustrating another embodiment of the digital-to-analog converter of FIG. 1.

5 is a block diagram illustrating yet another embodiment of the digital-to-analog converter of FIG. 1.

6 is a block diagram illustrating yet another embodiment of the digital-to-analog converter of FIG. 1.

FIG. 7 is a block diagram illustrating an integrated circuit including the sigma delta modulator of FIG. 1.

Claims (19)

At least one capacitor; And At least a portion of the current charged in the at least one capacitor during the first time period and based on a clock signal whose clock period consists of first and second time periods and during the second time period. A digital filter for a continuous time sigma delta modulator comprising a control unit for providing a loop filter and controlling the first and second time intervals such that the current or voltage remaining in the at least one capacitor satisfies a predetermined criterion. Digital to Analog Converter (DAC). The method of claim 1, wherein the control unit And controlling the first and second time intervals to minimize errors caused by the current or voltage remaining in the at least one capacitor. The method of claim 1, wherein the clock signal is And a first logic level in the first time interval and a second logic level in the second time interval. The method of claim 1, wherein the control unit A switching unit for switching at least one end of the at least one capacitor based on the clock signal to charge the at least one capacitor or to provide at least a portion of the current charged in the at least one capacitor to the loop filter; And And a clock generator for controlling a duty ratio of a reference clock to provide the clock signal to the switching unit. The method of claim 1, wherein the control unit Digital-to-analog converter, characterized in that for charging said at least one capacitor or providing at least a portion of the current charged in said at least one capacitor based on a digital signal output from a quantizer. The method of claim 5, wherein when the number of the at least one capacitor is two or more, the at least one capacitor is connected in parallel, and each of the at least one capacitor is independently operated based on a digital signal output from a quantizer. Digital-to-analog converter, characterized in that. At least one capacitor; And At least a portion of the current charged in the at least one capacitor during the first time period and based on a clock signal whose clock period consists of first and second time periods and during the second time period. Is provided to a loop filter, and includes a control unit for controlling the first and second time intervals based on the current or voltage remaining in the at least one capacitor (DAC, Digital) for a continuous time sigma delta modulator. to Analog Converter). The method of claim 7, wherein the control unit And controlling the first and second time intervals to minimize errors caused by the current or voltage remaining in the at least one capacitor. The method of claim 7, wherein the clock signal is And a first logic level corresponding to the first time interval and a second logic level corresponding to the second time interval. The method of claim 7, wherein the control unit A switching unit for switching at least one end of the at least one capacitor based on the clock signal to charge the at least one capacitor or to provide at least a portion of the current charged in the at least one capacitor to the loop filter; And And a clock generator for controlling the duty ratio of the reference clock based on the current or voltage remaining in the at least one capacitor to provide the clock signal to the switching unit. The method of claim 7, wherein the control unit Digital-to-analog converter, characterized in that for charging said at least one capacitor or providing at least a portion of the current charged in said at least one capacitor based on a digital signal output from a quantizer. The method of claim 11, wherein when the number of the at least one capacitor is two or more, the at least one capacitor is connected in parallel, and each of the at least one capacitor is independently operated based on a digital signal output from a quantizer. Digital-to-analog converter, characterized in that. A loop filter comprising at least one integrator; A quantizer configured to output a digital signal by performing a quantization operation based on the signal output from the loop filter; And Including a digital-to-analog converter (DAC), The digital to analog converter At least one capacitor operated based on the digital signal; And At least one of the currents charged in the at least one capacitor during the first time interval and the at least one capacitor during the second time interval based on a clock signal whose clock period is comprised of first and second time intervals. And a control unit for providing a portion to a loop filter and controlling the first and second time intervals based on a current or voltage remaining in the at least one capacitor. The method of claim 13, wherein when the number of the at least one capacitor is two or more, the at least one capacitor is connected in parallel, and each of the at least one capacitor is independently operated based on the digital signal. Continuous time sigma delta modulator. The method of claim 13, wherein the control unit And controlling the first and second time intervals so that the current or voltage remaining in the at least one capacitor satisfies a predetermined criterion. The method of claim 15, wherein the control unit And minimizing errors caused by current or voltage remaining in the at least one capacitor. In an integrated circuit (IC) comprising a continuous time sigma delta modulator, The sigma delta modulator A loop filter comprising at least one integrator; A quantizer for outputting a digital signal based on the signal output from the loop filter; And Including a digital-to-analog converter (DAC), The digital to analog converter At least one capacitor operated based on the digital signal; And At least a portion of the current charged in the at least one capacitor during the first time period and based on a clock signal whose clock period consists of first and second time periods and during the second time period. And a controller for controlling the first and second time intervals based on a current or voltage remaining in the at least one capacitor. 18. The system of claim 17, wherein the integrated circuit is Sensor devices used for applications such as image sensing, infrared sensing, and biosensing, Code Division Multiple Access (CDMA), Global System for Mobile telecommunication (GSM), Wireless Local Area Network (WLAN), Digital Multimedia Broadcasting (DMB), and Bluetooth Integrated circuit, characterized in that included in the wireless receiver device comprising a. The method of claim 17, wherein the control unit And controlling the first and second time periods to minimize an error caused by current or voltage remaining in the at least one capacitor.

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