KR101042989B1 - Delta sigma analog-to-digital converter - Google Patents

Abstract

The delta sigma analog-to-digital converter of the present invention, unlike the conventional structure for receiving an analog voltage, the modulator for receiving an analog current and converting it to generate an oversampled PDM signal (Pulse Density Modulated Signal), and the generated PDM signal And a post-processing unit for generating digital data corresponding to an analog input current by reducing a sampling ratio and generating a selection signal for adjusting a dynamic range of the modulator. The modulator includes a plurality of current sources for generating currents of different magnitudes, and a current supply unit for adding current generated by a current source selected by a selection signal among the plurality of current sources and an analog input current. Therefore, the delta sigma analog-to-digital converter of the present invention can adjust the magnitude of the feedback current according to the magnitude of the input current, and thus has a wider dynamic range than the conventional structure.

Description

Delta Sigma Analog-to-Digital Converters {DELTA SIGMA ANALOG-TO-DIGITAL CONVERTER}

The disclosed technique relates to a Delta Sigma Analog-to-Digital Converter.

The Delta Sigma Analog-to-Digital Converter is an analog-to-digital converter that enables high resolution using low-cost complementary metal oxide semiconductors (CMOS).

Delta sigma analog-to-digital converters finally track the value of the input signal using a quantizer that has a lower number of bits than the desired resolution and operates faster than the oversampling rate, and uses the accumulated error to correct the error. Through this, the average value of the input signal and the average value of the output signal can be equal to each other.

Among the embodiments, the delta sigma analog-to-digital converter is a modulator for converting the analog input current to generate an oversampled PDM signal (Pulse Density Modulated Signal), and reducing the sampling ratio of the generated PDM signal (Sampling Ratio) A post-processing unit generating digital data corresponding to an analog input current and generating a selection signal for adjusting a dynamic range of the modulator, wherein the modulator is configured to generate a plurality of current sources for generating currents of different magnitudes; And a current supply unit configured to add the current generated by the current source selected by the generated selection signal among the plurality of current sources and the analog input current.

The modulator may include an integrator for generating an analog voltage signal by integrating the current supplied from the current supply unit, and a comparator for generating the PDM signal according to a comparison result by comparing the generated analog voltage signal with a predetermined voltage signal ( Comparator) may be further included.

The comparator may generate a digital signal LOW when the generated analog voltage signal is greater than or equal to the predetermined voltage, and generate a digital signal HIGH when the generated analog voltage signal is less than the predetermined voltage.

The post processor decimates the generated PDM signal to generate the digital data corresponding to the analog input current, and compares the generated digital data with a preset threshold voltage according to a comparison result. And a determination unit for updating an internal state of a finite state machine (FSM), wherein the finite state machine may provide the current supply unit with the selection signal corresponding to the internal state.

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The description of the disclosed technique is merely an example for structural or functional explanation and the scope of the disclosed technology should not be construed as being limited by the embodiments described in the text. That is, the embodiments may be variously modified and may have various forms, and thus the scope of the disclosed technology should be understood to include equivalents capable of realizing the technical idea.

On the other hand, the meaning of the terms described in the present application should be understood as follows.

The terms " first ", " second ", and the like are used to distinguish one element from another and should not be limited by these terms. For example, the first component may be named a second component, and similarly, the second component may also be named a first component.

The term “and / or” should be understood to include all combinations that can be suggested from one or more related items. For example, the meaning of “first item, second item and / or third item” may be given from two or more of the first, second or third items as well as the first, second or third items. Any combination of the possible items.

When a component is referred to as being "connected" to another component, it should be understood that there may be other components in between, although it may be directly connected to the other component. On the other hand, when a component is said to be "directly connected" to another component, it should be understood that there is no other component in between. On the other hand, other expressions describing the relationship between the components, such as "between" and "immediately between" or "neighboring to" and "directly neighboring to", should be interpreted as well.

Singular expressions should be understood to include plural expressions unless the context clearly indicates otherwise, and terms such as "include" or "have" refer to features, numbers, steps, operations, components, parts, or parts thereof described. It is to be understood that the combination is intended to be present, but not to exclude in advance the possibility of the presence or addition of one or more other features or numbers, steps, operations, components, parts or combinations thereof.

Each step may occur differently from the stated order unless the context clearly dictates the specific order. That is, each step may occur in the same order as specified, may be performed substantially simultaneously, or may be performed in the reverse order.

All terms used herein have the same meaning as commonly understood by one of ordinary skill in the art unless otherwise defined. Terms defined in commonly used dictionaries should be interpreted to be consistent with meaning in the context of the relevant art and can not be construed as having ideal or overly formal meaning unless expressly defined in the present application.

1 is a block diagram illustrating a configuration of a delta sigma analog digital converter according to an embodiment of the disclosed technology.

Referring to FIG. 1, the delta sigma analog-to-digital converter 1000 includes a modulator 110 and a post processor 120.

The modulator 110 receives the analog input current signal I_in, samples the received analog input current signal I_in with an oversampling clock, and converts the received analog input current signal I_in into a Pulse Density Modulated (PDM) signal. The PDM signal is a digital signal having a pulse number proportional to the magnitude of the input current signal I_in. Here, if the frequency of the oversampling clock is F _s , the oversampling rate is K, the bandwidth of the input current signal I_in is B, and the Nyquist frequency of the input current signal I_in is F _n , 1 holds.

Fs = K × Fn ---------- (1)

K = (F _s ) / (2B) ---------- (2)

The post-processing unit 120 receives the PDM signal and reduces the sampling ratio of the received PDM signal to generate N-bit digital data corresponding to the analog input current signal I_in. Here, N is the resolution of the delta sigma analog-to-digital converter, and is determined by the oversampling ratio. The post-processing unit 120 also generates selection signals, which are signals for adjusting the dynamic range.

2 is a block diagram illustrating a configuration of a post-processing unit according to an embodiment of the disclosed technology.

Referring to FIG. 2, the post processor 120 includes a decimator 210, a decision circuit 220, and a finite state machine 230.

The decimator 210 performs decimation to reduce the sampling ratio of the PDM signal generated by the modulator 110 to output N-bit digital data corresponding to the analog input current signal I_in. Create For example, the decimator 210 may generate an N-bit digital signal corresponding to the counting number by counting the number of HIGH bits included in the bitstream corresponding to the oversampling ratio. If the oversampling ratio is 16 and the bitstream is "0010010010010010", the decimator 210 may generate the digital signal "5 (0101)".

The determination circuit 220 determines whether the N-bit digital data generated by the decimator 210 falls within a predetermined range, and updates the state of the finite state machine 230 according to the determination result. Here, the predetermined range refers to a range in which the N-bit digital data corresponds to the operable region of the modulator 110. For example, the determination circuit 220 compares the N-bit digital data generated by the decimator 210 with a preset threshold value and compares the state of the finite state machine 230 according to the comparison result. Generates a control signal to update.

FIG. 3 is a diagram for describing a determination circuit of FIG. 2.

Referring to FIG. 3, if the N-bit digital data is greater than the first threshold value, the decision circuit 220 outputs a control signal to the finite state machine 230 that is HIGH as an UP signal and LOW as a DN signal. If the N-bit digital signal is less than the second threshold, the decision circuit 220 outputs a control signal, LOW and DN signal HIGH, to the finite state machine 230 as the UP signal. The determination circuit 220 outputs to the finite state machine 230 a control signal that is LOW as an UP signal and LOW as a DN signal if the N-bit digital signal is below the first threshold and above the second threshold.

Referring again to FIG. 2, finite state machine (FSM) 230 provides a modulator 110 with a selection signal corresponding to an internal state. The selection signal provided to the modulator 110 is used to adjust the dynamic range of the modulator 110. The internal state of the finite state machine 230 is transitioned in accordance with the control signal generated by the decision circuit 220.

4 is a state diagram for explaining the state of the finite state machine shown in FIG.

Referring to FIG. 4, the state of the finite state machine 230 corresponds to any one of the first to third states 410, 420, 430. For example, the first state 410 has a full scale of 50 ms, the second state 420 has a full scale of 5 ms, and the third state 430 has a full scale. May correspond to 0.5 ms.

The initial state of the finite state machine 230 corresponds to the first state 410, and the finite state machine 230 in the first state is HIGH, the second and the third select signal with the first select signal Sel_1. (Sel_2, Sel_3) provides LOW to modulator 110.

When LOW is applied as the UP signal and HIGH is applied as the DN signal in the first state 410, the state of the finite state machine 230 transitions to the second state 420. The finite state machine 230 in the second state 420 provides the modulator 110 with HIGH as the second select signal Sel_2 and LOW with the first and third select signals Sel_1 and Sel_3.

In the second state 420, when LOW is applied as the UP signal and HIGH as the DN signal, the state of the finite state machine 230 transitions to the third state 430. The finite state machine 230 in the third state 430 provides the modulator 110 with HIGH as the third select signal Sel_3 and LOW with the first and second select signals Sel_1 and Sel_2.

5 is a block diagram illustrating a configuration of a modulator according to an embodiment of the disclosed technology.

Referring to FIG. 5, the modulator 110 includes a current supply unit 510, an integrator 520, and a comparator 530.

The current supply unit 510 includes a plurality of current sources, and currents and analog inputs generated by any one of the plurality of current sources corresponding to the selection signals Sel_1, Sel_2, and Sel_3 provided from the finite state machine 230. The current I_in is added and output as the difference current I_d.

The selection signals Sel_1, Sel_2, and Sel_3 are signals that are determined according to the magnitude of the analog input current I_in and are signals for selecting any one of a plurality of current sources, so that the current supply unit 510 is an analog input. A current source corresponding to the magnitude of the current I_in may be selected and added to the analog input current I_in.

FIG. 6 is a circuit diagram illustrating the current supply unit illustrated in FIG. 5.

Referring to FIG. 6, the current supply unit 510 includes first to third current circuits 620, 640, and 660.

The first current circuit 620 includes two current sources 624 and 626 for supplying 50 mA of current, four switches MP1, MP2, MN1 and MN2, and a first control circuit 622. It operates when the selection signal Sel_1 is HIGH and generates a difference current I_d by adding a current of +50 mA or -50 mA to the analog input current I_in.

The first control circuit 622 receives a sink signal and a source signal from the comparator 530. The first control circuit 622 turns on the switch MN2 and turns off the switch MP2 when the sink signal is HIGH and the source signal is LOW. In this case, the current source 626 outputs a current of -50 mA. If the sink signal is LOW and the source signal is HIGH, the first control circuit 622 turns off the switch MN2 and turns on the switch MP2. In this case, the current source 624 outputs a current of +50 mA.

In the same way, the second current circuit 640 comprises two current sources 644, 646, four switches MP3, MP4, MN3, MN4 and a second control circuit 642 which supplies 5 mA of current. do. The second current circuit 640 operates when the second selection signal Sel_2 is HIGH, and generates a difference current I_d by adding a current of +5 mA or -5 mA to the analog input current I_in. .

The third current circuit 660 includes two current sources 664, 666, four switches MP5, MP6, MN5, MN6, and a third control circuit 662 that supply 0.5 mA of current. The third current circuit 660 operates when the third select signal Sel_3 is HIGH and generates a difference current I_d by adding a current of +0.5 mA or -0.5 mA to the analog input current I_in. .

Referring again to FIG. 5, an integrator 520 integrates the difference current I_d to generate an analog voltage signal. Integrator 520 includes an OP Amp 522 and a Capacitor 524. The inverting input terminal (−) of the OP Amp 522 is connected to the current supply unit 510, and the non-inverting input terminal (+) is connected to the reference voltage Vcom. The capacitor 524 is inserted between the inverting input terminal (-) and the output terminal of the OP Amp 522.

The comparator 530 quantizes the analog voltage signal generated by the integrator 520 according to an oversampling clock to generate a pulse density modulated (PDM) signal. Here, the PDM signal corresponds to a 1-bit digital signal. In detail, the comparator 530 compares the analog voltage with the reference voltage Vcom according to the oversampling clock, and outputs a digital bit corresponding to the comparison result. For example, if the analog voltage signal generated by the integrator 520 is greater than or equal to the reference voltage Vcom, the comparator 530 may output LOW through the H terminal and HIGH through the L terminal. In addition, the comparator 530 may output HIGH through the H terminal and output LOW through the L terminal when the analog voltage signal generated by the integrator 520 is less than the reference voltage Vcom. The digital bit output through the H terminal of the comparator 530 is a PDM signal and is input to the decimator 210 of the post processor 120. In addition, the digital bit output through the H terminal of the comparator 530 is a sink signal, and the first control circuit 622, the second control circuit 642, and the third control circuit of the current supply unit 510 ( The digital bit input to the 662 and output through the L terminal of the comparator 530 is a source signal, and the first control circuit 622, the second control circuit 642 and the current supply unit 510. It is input to the third control circuit 662.

The disclosed technique may have the following effects. It is to be understood, however, that the scope of the disclosed technology is not to be construed as limited thereby, as it is not meant to imply that a particular embodiment should include all of the following effects or only the following effects.

The delta sigma analog-to-digital converter according to an embodiment may receive an analog current, unlike a conventional structure that receives an analog voltage, and converts a dynamic range by adjusting a feedback current according to the magnitude of the input current. As a result, it can provide a delta sigma analog-to-digital converter with a wide dynamic range.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the present invention as defined by the following claims It can be understood that

1 is a block diagram illustrating a configuration of a delta sigma analog-to-digital converter according to an embodiment of the disclosed technology.

2 is a block diagram illustrating a configuration of a post-processing unit according to an embodiment of the disclosed technology.

FIG. 3 is a diagram for describing a determination circuit of FIG. 2.

4 is a state diagram for explaining the state of the finite state machine shown in FIG.

5 is a block diagram illustrating a configuration of a modulator according to an embodiment of the disclosed technology.

FIG. 6 is a circuit diagram illustrating the current supply unit illustrated in FIG. 5.

Claims (5)

A modulator for converting the analog input current to generate an oversampled PDM signal (Pulse Density Modulated Signal); And And a post-processing unit configured to reduce the sampling ratio of the generated PDM signal to generate digital data corresponding to the analog input current, and to generate a selection signal for adjusting a dynamic range of the modulator. , The modulator is Delta sigma analog including a plurality of current sources for generating current of different magnitudes, and a current supply unit for adding the current and the analog input current generated by the current source selected by the generated selection signal of the plurality of current sources Digital Sigma Analog-to-Digital Converter. The method of claim 1, wherein the modulator An integrator for generating an analog voltage signal by integrating the current supplied from the current supply unit; And And a comparator for comparing the generated analog voltage signal with a predetermined voltage signal to generate the PDM signal according to a comparison result. The method of claim 2, wherein the comparator And generating a digital signal LOW when the generated analog voltage signal is greater than or equal to the predetermined voltage signal and generating a digital signal HIGH when the generated analog voltage signal is less than the predetermined voltage signal. The method of claim 1, wherein the post-processing unit A decimator decimating the generated PDM signal to generate the digital data corresponding to the analog input current; And A determination unit for comparing the generated digital data with a preset threshold voltage and updating an internal state of a finite state machine (FSM) according to a comparison result; The finite state machine provides the selection signal corresponding to an internal state to the current supply. delete

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