KR20100003079A - Method for forming semiconductor device - Google Patents

Method for forming semiconductor device Download PDF

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Publication number
KR20100003079A
KR20100003079A KR1020080063181A KR20080063181A KR20100003079A KR 20100003079 A KR20100003079 A KR 20100003079A KR 1020080063181 A KR1020080063181 A KR 1020080063181A KR 20080063181 A KR20080063181 A KR 20080063181A KR 20100003079 A KR20100003079 A KR 20100003079A
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South Korea
Prior art keywords
via hole
film
semiconductor device
sacrificial
sacrificial layer
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KR1020080063181A
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Korean (ko)
Inventor
김수영
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주식회사 하이닉스반도체
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Priority to KR1020080063181A priority Critical patent/KR20100003079A/en
Publication of KR20100003079A publication Critical patent/KR20100003079A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/7682—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing the dielectric comprising air gaps

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The present invention relates to a method for manufacturing a semiconductor device capable of effectively removing residues remaining at the inlet edge of a via hole when manufacturing a semiconductor device having a dual damascene pattern including a via hole and a trench. The semiconductor device manufacturing method of the present invention for this purpose comprises the steps of forming an insulating film having a via hole; Forming a sacrificial layer on the bottom and sidewalls of the via hole; Selectively etching the insulating film in the upper region of the via hole to connect the trench connected to the via hole and removing the sacrificial layer. According to the present invention, the sacrificial film is formed only on the bottom and sidewalls of the via hole. The residue R remaining at the edge of the via hole inlet can be effectively removed without increasing the overetching amount.

Description

Semiconductor device manufacturing method {METHOD FOR FORMING SEMICONDUCTOR DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a manufacturing technology of a semiconductor device, and more particularly, to a manufacturing method of a semiconductor device having a dual damascene pattern.

In recent years, as semiconductor devices have been highly integrated, copper (Cu) has been in the spotlight in forming metal wiring. In forming metal interconnections using copper, since copper has very poor etching characteristics, copper interconnects are typically formed using a damascene process. As a damascene process, a single damascene process or a dual damascene process is used, and a dual damascene process is mainly applied.

1A to 1B are cross-sectional views illustrating a method of manufacturing a copper wiring using a dual damascene process according to the prior art, and FIG. 2 is an image illustrating a problem according to the prior art.

As shown in FIG. 1A, after the insulating film 12 including the via hole 13A exposing the top surface of the conductive film 11 is formed on the conductive film 11, the inside of the via hole 13A is formed. It is embedded in the sacrificial film (14). In this case, the insulating film 12 uses an oxide film, and the sacrificial film 14 uses a photoresist or a bottom anti-reflective coating (BRAC).

Next, after forming the hard mask pattern 15 on the insulating film 12, the trench is connected to the via hole 13A by etching the insulating film 12 with a predetermined thickness using the hard mask pattern 15 as an etch barrier. 13B is formed.

As shown in FIG. 1B, the sacrificial layer 14 is removed to complete the dual damascene pattern 13 including the via hole 13A and the trench 13B.

Next, after forming the diffusion barrier 16 to prevent out diffusion of copper to be embedded in the dual damascene pattern 13 along the surface of the dual damascene pattern 13, the diffusion barrier 16 Copper is deposited to fill the dual damascene pattern 13) to form a copper wiring 17.

However, the above-described conventional technique remains at the interface between the insulating film 12 and the sacrificial film 14 at the inlet edge of the via hole, as shown in 'A' of FIG. 1B and 'A' of FIG. 2 during the formation of the trench 13B. There is a problem that water (Residue, R) remains. Since the residue R has a pointed shape, as shown in 'A' of FIG. 1B, the diffusion barrier layer 16 is not normally formed on the residue R, and thus copper embedded in the dual damascene pattern 13 is formed. Problem occurs that is spread to the outside. Removing the residue (R) can solve the above-described problem, it is to increase the excessive etching amount in the process of forming the trench (13B) to remove the residue (R). However, if the excessive etching amount is increased, there is a problem that damage occurs on the upper surface of the insulating film 12B.

The present invention has been proposed to solve the above-mentioned problems of the prior art, and in manufacturing a dual damascene pattern including a via hole and a trench, manufacturing a semiconductor device capable of preventing residue from remaining at the inlet edge of the via hole. The purpose is to provide a method.

In addition, another object of the present invention in the manufacture of a dual damascene pattern including a via hole and a trench, the manufacturing of a semiconductor device that can prevent the damage to the upper surface of the insulating film in the process of removing the residue of the via hole inlet edge To provide a method.

In addition, another object of the present invention is to provide a method for manufacturing a semiconductor device that can prevent the metal material embedded in the dual damascene pattern to diffuse to the outside.

In accordance with an aspect of the present invention, a method of manufacturing a semiconductor device includes: forming an insulating layer having a via hole; Forming a sacrificial layer on the bottom and sidewalls of the via hole; Selectively etching the insulating layer in the upper region of the via hole to form a trench connected to the via hole, and removing the sacrificial layer. In this case, the sacrificial film may include an amorphous carbon film.

The forming of the trench may include a main etching step of selectively etching the insulating layer to form a trench connected to the via hole, and a transient etching step of removing residues remaining in the via hole and the trench.

The forming of the sacrificial film on the bottom and sidewalls of the via hole may include blocking the inlet of the via hole, depositing a sacrificial film having a void in the via hole, and selectively etching the sacrificial film blocking the inlet of the via hole. And leaving a sacrificial layer on the bottom and sidewalls of the via hole. Here, the depositing of the sacrificial film may be performed using chemical vapor deposition. In the depositing of the sacrificial layer, the deposition rate in the horizontal direction may be faster than the deposition rate in the vertical direction. In addition, the depositing of the sacrificial layer may be performed using a bias power in the range of 1300W to 1800W.

Selectively etching the sacrificial layer may be performed by using a dry etching method. In addition, the step of selectively etching the sacrificial film may be performed using a mixed gas of nitrogen gas (N 2 ) and hydrogen gas (H 2 ) mixed.

Removing the sacrificial film can be performed by using an oxygen plasma treatment (O 2 plasma treatment).

The present invention may further include forming a diffusion barrier along the via hole and the trench surface and forming a metal film filling the via hole and the trench on the diffusion barrier. In this case, the metal film may include a copper film Cu.

According to the present invention based on the above-described problem solving means, by forming the sacrificial film only on the bottom and sidewalls of the via hole without completely filling the sacrificial film in the via hole, the residue (R) remaining at the edge of the via hole inlet without increasing the transient etching amount. The effect can be effectively removed.

As such, the present invention can prevent the residue from remaining at the inlet edge of the via hole, thereby forming a diffusion barrier film having a uniform thickness on the entire dual damascene pattern. This has the effect of preventing the external diffusion of the metal material embedded in the dual damascene pattern.

In addition, the present invention has an effect of improving the etching margin of the hard mask pattern during the etching process for forming the dual damascene pattern by remaining the sacrificial layer between the hard mask pattern and the insulating film.

Hereinafter, the most preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention.

In the following description of the present invention, in the manufacture of a semiconductor device having a dual damascene pattern including a via hole and a trench, a residue at the inlet edge of the via hole without increasing the excessive etching amount is produced. Provided is a method of manufacturing a semiconductor device that can prevent this from remaining. In addition, the present invention provides a method of manufacturing a semiconductor device capable of preventing the metal material embedded in the dual damascene pattern from being diffused to the outside. To this end, the present invention forms a sacrificial film for protecting the via hole in the process of forming a trench, the technical principle is to form the sacrificial film only on the bottom and sidewalls of the via hole.

3A through 3E are cross-sectional views illustrating a method of manufacturing metal wirings in a semiconductor device according to an embodiment of the present invention.

As shown in FIG. 3A, an insulating film 22 having a via hole 23A is formed on the conductive pattern 21. The conductive pattern 21 may be any one selected from the group consisting of a word line, a bit line, and a metal line.

The via hole 23A forms a hole-type hard mask pattern (not shown) on the insulating film 22, and then exposes the top surface of the conductive pattern 21 by using the hard mask pattern as an etch barrier. The insulating film 22 may be etched until it is formed. In this case, an etching process for forming the via hole 23A may be performed using a dry etching method, and a reactive ion etching method (RIE) may be used as the dry etching method.

The insulating film 22 may be formed of any one selected from the group consisting of an oxide film, a nitride film, and an oxynitride, or a laminated film in which these layers are stacked. Oxides include silicon oxide (SiO 2 ), Boron Phosphorus Silicate Glass (BPSG), Phosphorus Silicate Glass (PSG), Tetra Ethyle Ortho Silicate (TEOS), Un-doped Silicate Glass (USG), Spin On Glass (SOG) Plasma oxide films (High Density Plasma, HDP), SOD (Spin On Dielectric) may be used. As the nitride film, a silicon nitride film (Si 3 N 4 ) may be used. As the oxynitride film, a silicon oxynitride film (SiON) may be used. In this case, the insulating film 22 is preferably formed of an oxide film having a relatively low dielectric constant among the above-described materials in order to prevent an increase in RC delay time between metal lines to be formed through a subsequent process.

Next, a part of the via hole 23A is filled and a sacrificial film 24 covering the upper surface of the insulating film 22 is formed. In detail, the sacrificial layer 24 blocks an inlet of the via hole 23A to leave the sacrificial layer 24 on the bottom and sidewalls of the via hole 23A through a subsequent process, and has an air gap inside the via hole 23A. 25). Therefore, in order to effectively form the sacrificial film 24 having the voids 25 in the via hole 23A, the chemical vapor deposition method may control the deposition rate in the vertical direction and the horizontal direction. , CVD) is preferable. In addition, the sacrificial layer 24 may be formed of an amorphous carbon layer in order to improve the etching margin of the hard mask pattern during the etching process for forming the trench of the subsequent dual damascene pattern.

In summary, the sacrificial film 24 is preferably formed of an amorphous carbon film using chemical vapor deposition. Specifically, a method of forming a sacrificial film 24 having a void 25 in the via hole 23A as an amorphous carbon film using chemical vapor deposition is as follows.

As a reaction gas for forming an amorphous carbon film in the chamber, any one selected from the group consisting of methane fluoride gas, fluorocarbon gas and hydrocarbon gas or a mixed gas thereof is injected. In this case, in order to easily control the amorphous carbon film deposition process, it is preferable to inject only one of methane fluoride gas, fluorocarbon gas, or hydrocarbon gas into the chamber, and more preferably, use hydrocarbon gas alone. CHF 3 may be used as the methane fluoride gas. As the fluorocarbon gas, CF 4 , C 2 F 6 , C 3 F 8, etc. may be used. Hydrocarbon gases include CH 4 , C 2 H 4 , C 3 H 6 Etc. can be used. Here, an inert gas such as helium (He) may be used as a carrier gas for transporting the reaction gas.

Next, in order to form the voids 25 in the via holes 23A, the sacrificial film 24 deposition process is performed so that the deposition speed in the horizontal direction is faster than the deposition speed in the vertical direction. In this case, when a bias power of 1300W to 1800W is applied to the chamber, the deposition speed in the horizontal direction may be faster than the deposition speed in the vertical direction. As such, if the process is controlled so that the deposition rate in the horizontal direction is faster than the deposition rate in the vertical direction, the inlet portion of the via hole 23A is blocked before the via holes 23A are filled, and the voids are formed in the via hole 23A. 25 can be formed.

As shown in FIG. 3B, a hard mask pattern 26 having a line shape is formed on the sacrificial layer 24. At this time, the hard mask pattern 26 serves as an etch barrier during the etching process of the insulating film 22 to form a trench of the subsequent dual damascene pattern. Therefore, the hard mask pattern 26 may be formed of any one selected from the group consisting of an oxide film, a nitride film, and an oxynitride film or a laminated film in which these layers are stacked. Here, the hard mask pattern 26 may be formed of an oxynitride layer, for example, silicon oxynitride (SiON), which may simultaneously serve as an etch barrier and a bottom anti reflection coating (BARC).

Next, the sacrificial layer 24 blocking the entrance of the via hole 23A is selectively etched using the hard mask pattern 26 as an etch barrier, so that a part of the sacrificial layer 24 is left on the bottom and sidewalls of the via hole 23A. . Specifically, by sacrificially etching the sacrificial film 24 formed in the upper inlet portion of the via hole 23A using the hard mask pattern 26 as an etch barrier to expose the voids 25, the sacrificial film is sacrificed on the bottom and sidewalls of the via hole 23A. The film 24 can remain. In this case, the process of selectively etching the sacrificial layer 24 may be performed using a dry etching method, and the plasma etching method may be used as a dry etching method.

Specifically, only the sacrificial layer 24 is selectively selected using the plasma of the mixed gas (N 2 / H 2 ) in which nitrogen gas (N 2 ) and hydrogen gas (H 2 ) are mixed as the hard mask pattern 26 as an etch barrier. Can be etched with In this case, in order to prevent damage to the sidewall of the via hole 23A and the upper surface of the conductive pattern 21 exposed by the via hole 23A, the sacrificial film 24 remains on the bottom and sidewalls of the via hole 23A. It is desirable to adjust For example, an amorphous carbon film having a thickness of 10000 μs is etched using a plasma of a mixed gas (N 2 / H 2 ) in which nitrogen gas (N 2 ) and hydrogen gas (H 2 ) are mixed. If you proceed to can selectively etch only thickness in the range of 6500Å ~ 7500Å.

The sacrificial layer 24 may be left on the bottom and sidewalls of the via hole 23A through the above-described etching process. In addition, while the sacrificial layer 24 is left on the bottom and sidewalls of the via hole 23A through the above-described etching process, the sacrificial layer 24 remains between the insulating layer 22 and the hard mask pattern 26. The remaining sacrificial film 24 between the insulating film 22 and the hard mask pattern 26 serves as an etch barrier along with the hard mask pattern 26 during the etching process of the insulating film 22 to form a subsequent dual damascene pattern. . Through this, the etching margin of the hard mask pattern 26 may be improved.

Hereinafter, the reference numerals of the sacrificial film 24 remaining in the via hole 23A will be changed to “24A” to sacrifice the sacrificial film 24 remaining between the insulating film 22 and the hard mask pattern 26. The mask pattern 24B is referred to.

As illustrated in FIG. 3C, the insulating layer 22 is etched a predetermined thickness using the hard mask pattern 26 and the sacrificial hard mask pattern 24B as an etch barrier to form a line-shaped trench 23B connected to the via hole 23A. The main etch process is performed to form. The main etching process can be carried out using dry etching, for example, reactive ion etching (RIE). In this case, due to the sacrificial layer 24A formed on the bottom and sidewalls of the via hole 23A, the upper surface of the conductive pattern 21 exposed by the sidewall and the via hole 23A of the via hole 23A may be prevented from being damaged. .

Here, the sacrificial layer 24A may be partially etched at the same time as the insulating layer 22 is etched during the main etching process. At this time, the etching by-products generated by etching the insulating film 22 and the sacrificial film 24A by the etching gas are accumulated at the interface between the inlet edge insulating film 22 and the sacrificial film 24A of the via hole 23A. (R) can be formed. As such, it is preferable to remove the residue R remaining at the inlet edge of the via hole 23A because it has a negative effect on subsequent processes.

Accordingly, as shown in FIG. 3D, an over etch process is performed using the hard mask pattern 26 and the sacrificial hard mask pattern 24B as an etch barrier to form the inside of the via hole 23A and the trench 23B. Remove remaining residues (R). In particular, the residue R remaining on the inlet edge of the via hole 23A is removed through the transient etching process. In this case, it is preferable to adjust the transient etching time so that the upper surface of the conductive pattern 21 and the upper surface of the insulating layer 22 exposed by the via hole 23A are not damaged.

In general, the amount of transient etching must be increased in order to cleanly remove the residue R remaining in the via hole 23A and the trench 23B. However, when the excessive etching amount is increased, the upper surface of the conductive pattern 21 and the upper surface of the insulating film 22 exposed by the via hole 23A may be damaged.

In contrast, since the sacrificial film 24 is formed to have the voids 25 in the via hole 23A, the sacrificial film 24A remaining on the sidewall of the via hole 23A has a very thin thickness. Therefore, the sacrificial film 24A and the residue R remaining at the inlet edge of the via hole 23A during the etching process for forming the trench 23B can be easily removed without increasing the excessive etching amount.

As shown in FIG. 3E, the hard mask pattern 26 is removed.

Meanwhile, the hard mask pattern 26 may be removed and removed during the etching process for forming the trench 23B. If the hard mask pattern 26 remains even after the trench 23B is formed, it is preferable to remove the remaining hard mask pattern 26 through a separate removal process and then proceed to the subsequent process.

Next, the sacrificial film 24A and the sacrificial hard mask pattern 24B remaining on the bottom and sidewalls of the via hole 23A are simultaneously removed. In this case, the sacrificial layer 24A and the sacrificial hard mask pattern 24B may be simultaneously removed by performing an O 2 plasma treatment.

Through the above-described process, the dual damascene pattern 23 including the via-shaped via hole 23A and the line-shaped trench 23B may be formed.

Next, the diffusion barrier 27 is formed along the surface of the dual damascene pattern 23. The diffusion barrier 27 serves to prevent diffusion of the metal material to be embedded in the dual damascene pattern 23 through the subsequent process, and may be formed of a heat resistant metal. Heat-resistant metal is composed of titanium (Ti), cobalt (Co), molybdenum (Mo), platinum (Pt), iridium (Ir), ruthenium (Ru), chromium (Cr), tantalum (Ta) and zirconium (Zr) Any one selected from the group can be used. In addition, the diffusion barrier 27 may use a metal nitride, for example, titanium nitride (TiN) in which the above-mentioned heat-resistant metal and nitrogen (N) are combined.

Next, the dual damascene pattern 23 is embedded with the metal material on the diffusion barrier 27 to form the metal wiring 28. The metal wire 28 may be formed of any one selected from the group consisting of copper (Cu), tungsten (W), and aluminum (Al). Preferably, the metal wire 28 has a higher melting point than tungsten or aluminum, and has a high resistance to EM (Electro Migration) and SM (Stress Migration), and thus can be highly integrated, and copper having low specific resistance may increase signal transmission speed. It is good to form using.

Through the above-described process, the metal wiring of the semiconductor device according to the embodiment of the present invention can be formed.

4 is an image illustrating a dual damascene pattern of a semiconductor device according to an embodiment of the present invention.

As shown in FIG. 4, the dual damascene pattern 23 of the present invention can confirm that no residue remains at the inlet edge of the via hole 23A.

As described above, the present invention does not completely fill the sacrificial film in the via hole 23A, and forms the sacrificial film only on the bottom and sidewalls of the via hole 23A, so that the residue remaining at the inlet edge of the via hole 23A without increasing the excessive etching amount. (R) can be removed effectively.

As such, the present invention prevents the residue R from remaining at the inlet edge of the via hole 23A, thereby forming a diffusion barrier layer having a uniform thickness on the entire dual damascene pattern. Through this, it is possible to prevent the external diffusion of the metal material embedded in the dual damascene pattern.

In addition, the present invention may improve the etching margin of the hard mask pattern 26 during the etching process for forming the dual damascene pattern by remaining the sacrificial layer between the hard mask pattern 26 and the insulating layer 22.

Although the technical spirit of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will appreciate that various embodiments within the scope of the technical idea of the present invention are possible.

Figure 1a to 1b is a process cross-sectional view showing a copper wiring manufacturing method using a dual damascene process according to the prior art.

Figure 2 is an image showing a problem according to the prior art.

3A to 3E are cross-sectional views illustrating a method of manufacturing metal wirings in a semiconductor device according to an embodiment of the present invention.

Figure 4 is an image showing a dual damascene pattern of a semiconductor device according to an embodiment of the present invention.

* Description of symbols on the main parts of the drawings *

21: conductive film 22: insulating film

23A: Via Hole 23B: Trench

23: dual damascene pattern 24, 24A: sacrificial film

24B: sacrificial hard mask pattern 25: air gap

26: hard mask pattern 27: diffusion barrier

28: metal film

Claims (12)

Forming an insulating film having via holes; Forming a sacrificial layer on the bottom and sidewalls of the via hole; Selectively etching the insulating layer in the upper region of the via hole to form a trench connected to the via hole; And Removing the sacrificial layer Semiconductor device manufacturing method comprising a. The method of claim 1, Forming the trench, Selectively etching the insulating layer to form a trench connected to the via hole; And Transient etching to remove residues remaining in the via hole and the trench Semiconductor device manufacturing method comprising a. The method of claim 1, Forming a sacrificial layer on the bottom and sidewalls of the via hole; Blocking an inlet of the via hole and depositing a sacrificial film having a void inside the via hole; And Selectively etching the sacrificial layer blocking the inlet of the via hole to leave the sacrificial layer on the bottom and sidewalls of the via hole; Semiconductor device manufacturing method comprising a. The method of claim 3, And depositing the sacrificial film using a chemical vapor deposition method. The method of claim 3, Depositing the sacrificial film, A method of manufacturing a semiconductor device, wherein the deposition rate in the horizontal direction is faster than the deposition rate in the vertical direction. The method of claim 3, Depositing the sacrificial film, A semiconductor device manufacturing method using a bias power in the range of 1300W to 1800W. The method of claim 3, Selectively etching the sacrificial layer is performed using a dry etching method. The method of claim 3, Selectively etching the sacrificial layer, A semiconductor device manufacturing method using a mixed gas of nitrogen gas (N 2 ) and hydrogen gas (H 2 ) mixed. The method of claim 1, Removing the sacrificial layer is a semiconductor device manufacturing method using the oxygen plasma treatment (O 2 plasma treatment). The method according to any one of claims 1 to 9, The sacrificial layer includes an amorphous carbon film. The method of claim 1, Forming a diffusion barrier along the via hole and the trench surface; And Forming a metal film filling the via hole and the trench on the diffusion barrier layer A semiconductor device manufacturing method further comprising. The method of claim 11, The metal film is a semiconductor device manufacturing method comprising a copper film (Cu).
KR1020080063181A 2008-06-30 2008-06-30 Method for forming semiconductor device KR20100003079A (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103376487A (en) * 2012-04-23 2013-10-30 中芯国际集成电路制造(上海)有限公司 Method for manufacturing optical gratings
KR101477494B1 (en) * 2013-07-08 2014-12-30 주식회사 테스 Air gap forming method using amorphous carbon layer
US9379118B2 (en) 2013-11-13 2016-06-28 Samsung Electronics Co., Ltd. Methods of fabricating semiconductor devices including interlayer wiring structures

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103376487A (en) * 2012-04-23 2013-10-30 中芯国际集成电路制造(上海)有限公司 Method for manufacturing optical gratings
KR101477494B1 (en) * 2013-07-08 2014-12-30 주식회사 테스 Air gap forming method using amorphous carbon layer
US9379118B2 (en) 2013-11-13 2016-06-28 Samsung Electronics Co., Ltd. Methods of fabricating semiconductor devices including interlayer wiring structures

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