KR20100003040A - Semiconductor memory device and method for testing the same - Google Patents

Semiconductor memory device and method for testing the same Download PDF

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Publication number
KR20100003040A
KR20100003040A KR1020080063136A KR20080063136A KR20100003040A KR 20100003040 A KR20100003040 A KR 20100003040A KR 1020080063136 A KR1020080063136 A KR 1020080063136A KR 20080063136 A KR20080063136 A KR 20080063136A KR 20100003040 A KR20100003040 A KR 20100003040A
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KR
South Korea
Prior art keywords
memory cells
data values
reference data
dat1
compression test
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Application number
KR1020080063136A
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Korean (ko)
Inventor
김대석
조진희
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주식회사 하이닉스반도체
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Priority to KR1020080063136A priority Critical patent/KR20100003040A/en
Publication of KR20100003040A publication Critical patent/KR20100003040A/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/1201—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details comprising I/O circuitry
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/36—Data generation devices, e.g. data inverters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/38—Response verification devices
    • G11C29/40—Response verification devices using compression techniques

Abstract

PURPOSE: Semiconductor memory device and a method for testing the same are provided to improve the reliability of a compression test mode by detecting a compression signal through which a state of a memory cell is determined failure or not. CONSTITUTION: In a device, a reference data value storage(210) stores a reference data value corresponding to a test signal. The reference data value storage is designed as an inverter type latch including a first and a second inverter(INV1,INV2). The test signal is a signal which is generated outside or inside by tester in the compression test mode. The compression test result detection unit(230) compares data value and the reference data value corresponding to a plurality of memory cells and outputs normal/abnormal state of the memory cells as a compression test detection signal. A compression test result detection unit includes first-third compression parts(232,234,236) and a compression test result output part(238).

Description

Semiconductor memory device and test method therefor {SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR TESTING THE SAME}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor design technology, and more particularly, to a semiconductor memory device that performs a compression test mode.

In general, as the integration density of semiconductor memory devices including DDR Double Data Rate Synchronous DRAM (SDRAM) is rapidly increasing, tens of millions of memory cells are provided in one semiconductor memory device. If any one of these memory cells fails, the semiconductor memory device is treated as a defective product without being able to make a shed. Therefore, in order to increase the yield of the semiconductor memory device, a process of testing the semiconductor memory device must be essential, and accordingly, the semiconductor memory device is repaired or defectively processed.

On the other hand, as the number of memory cells increases, considerable test time is required to determine whether all memory cells are normal or defective. Since test time is an important factor in determining the cost of a product, several test modes are proposed to shorten it. One of them is the compression test mode. The compression test mode is a test mode in which the same data is written to a plurality of memory cells and the data of the plurality of memory cells are compressed and detected during a read operation. The test runner can determine whether the memory cell is normal or defective based on the compressed test detection signal thus detected.

FIG. 1 is a circuit diagram illustrating a conventional compression test operation, in which first to third exclusive negative logic gates XNOR1, XNOR2, and XNOR3, negative logic gate NAND, and inverter INV are shown. .

The first exclusive negative logic gate XNOR1 receives a plurality of first data values DAT1_A, DAT1_B, DAT1_C, and DAT1_D, compresses them, and outputs them. The second exclusive negative logic gate XNOR2 receives a plurality of second data values (XNOR2). DAT2_A, DAT2_B, DAT_2_C, and DAT2_D are received and compressed, and the third exclusive negative logic gate XNOR3 receives and compresses a plurality of third data values DAT3_A, DAT3_B, DAT3_C, and DAT3_D.

Here, a plurality of first data values DAT1_A, DAT1_B, DAT1_C, and DAT1_D input to the first exclusive negative logic gate XNOR1 and a plurality of second data values (input to the second exclusive negative logic gate XNOR2). DAT2_A, DAT2_B, DAT_2_C, DAT2_D and a plurality of third data values (DAT3_A, DAT3_B, DAT3_C, and DAT3_D) input to the third exclusive negative logic gate XNOR3 are stored in a plurality of memory cells (not shown). It has a value corresponding to the data. For reference, the exclusive negative logic gate outputs a logic 'high' if the input data has the same value, and the logic 'low' if any one of the input data is different. Outputs false.

The negative logical gate NAND receives and outputs the output signals of the first to third negative logical sum gates XNOR1, XNOR2, and XNOR3, and the inverter INV receives the output signal of the negative logical gate NAND. Output as a compression test detection signal (ZIP).

Hereinafter, the operation in the compression test mode (hereinafter referred to as a compression test operation) will be briefly described. For convenience of description, it is assumed that all of the memory cells store logic 'high' data in a plurality of memory cells during a write operation.

First, when the plurality of memory cells are all normal, the first to third exclusive negative logic gates XNOR1, XNOR2, and XNOR3 may correspond to the first to third data values DAT1_A, DAT1_B, DAT1_C, and DAT1_D of corresponding logic 'high'. , DAT2_A, DAT2_B, DAT2_C, DAT2_D, DAT3_A, DAT3_B, DAT3_C, DAT3_D) and receive true. Thereafter, the compression test detection signal ZIP becomes TRUE in response to the logic 'high', and the test operator determines that all the memory cells are normal.

That is, in the compression test detection signal ZIP, a plurality of first data values DAT1_A, DAT1_B, DAT1_C, and DAT1_D that are input to the first exclusive negative logic gate XNOR1 are all the same, and the second exclusive negative logic gate ( A plurality of second data values DAT2_A, DAT2_B, DAT_2_C, and DAT2_D inputted to XNOR2 are all the same, and a plurality of third data values DAT3_A, DAT3_B, and DAT3_C inputted to the third exclusive negative logic gate XNOR3. And DAT3_D) are all the same, the logic becomes 'high'. Here, the compression test detection signal ZIP is logic 'high', which means that the first to third data values DAT1_A, DAT1_B, DAT1_C, DAT1_D, DAT2_A, DAT2_B, DAT2_C, DAT2_D, DAT3_A, DAT3_B, and DAT3_C , DAT3_D) means that the plurality of memory cells corresponding to each of them is normal. If a bad memory cell exists among the plurality of memory cells, the compression test detection signal ZIP becomes false, which is logic 'low'.

However, the conventional circuit for the compression test operation has the following problems.

For example, when the memory cells corresponding to the plurality of first data values DAT1_A, DAT1_B, DAT1_C, and DAT1_D are all defective, that is, the logical 'high' data is stored in the memory cell during the write operation, but the read operation is caused by the failure. When all of the first to third data values DAT1_A, DAT1_B, DAT1_C, DAT1_D, DAT2_A, DAT2_B, DAT2_C, DAT2_D, DAT3_A, DAT3_B, DAT3_C, and DAT3_D corresponding to the memory cells are all inverted to logic 'low' , The compression test detection signal (ZIP) outputs a logic of true 'high'. That is, it is determined that all the memory cells are normal despite the failure of the memory cells. Such false detection results in a problem of lowering reliability in commercializing semiconductor memory devices.

The present invention has been proposed to solve the above problems, and provides a semiconductor memory device and a test method thereof capable of generating a compression test detection signal using data values and reference data values corresponding to a plurality of memory cells. The purpose is.

A semiconductor memory device according to an aspect of the present invention for achieving the above object, the storage means for storing a reference data value corresponding to the test signal, the data value corresponding to a plurality of memory cells and the reference data value is compared And compression test result detecting means for outputting whether the plurality of memory cells are normal or defective as a compression test detection signal.

According to another aspect of the present invention, there is provided a method of testing a semiconductor memory device, the method comprising: storing reference data values in response to a test signal, data values corresponding to a plurality of memory cells, and the reference data values And determining whether the plurality of memory cells are normal or defective by compressing a value, wherein determining whether the plurality of memory cells is normal or defective is normal when the data values stored in the plurality of memory cells correspond to the reference data values. If not, characterized in that it is determined to be defective.

Conventional semiconductor memory devices have a problem in that a compression test detection signal becomes true when a data test corresponding to a plurality of memory cells is inverted due to a defect during a compression test operation. The semiconductor memory device according to the present invention sets a reference data value and compares the reference data value with a data value corresponding to the plurality of memory cells to determine whether the plurality of memory cells are normal or defective. Can be output as Therefore, the present invention can increase the reliability of the compression test results.

The present invention can increase the reliability of the compression test mode by detecting a more reliable compression test detection signal that can determine whether a plurality of memory cells are normal or defective using reference data values.

Hereinafter, the most preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the technical idea of the present invention. .

2 is a circuit diagram illustrating a compression test operation according to the present invention, and may include a reference data value storage unit 210 and a compression test result detection unit 230.

The reference data value storage unit 210 stores the reference data value DAT_REF corresponding to the test signal TM, and includes an inverter type latch including first and second inverters INV1 and INV2. It can be designed as a latch. Here, the test signal TM may be a signal generated externally or internally by the test operator in the compression test mode, and may be a signal output from a mode register set. In addition, the test signal TM may have a logic 'high' or a logic 'low', and in this embodiment, the reference data value DAT_REF corresponding to data stored in a plurality of memory cells (not shown) to be compressed. ) May be a signal for storing the reference data value storage unit 210. Here, the plurality of data values DAT1_A, DAT1_B, DAT1_C, DAT2_A, DAT2_B, DAT2_C, DAT3_A, DAT3_B, and DAT3_C correspond to data stored in the plurality of memory cells.

The compression test result detector 230 compares the data values DAT1_A, DAT1_B, DAT1_C, DAT2_A, DAT2_B, DAT2_C, DAT3_A, DAT3_B, DAT3_C, and the reference data values DAT_REF corresponding to a plurality of memory cells. The first to third compression units 232, 234, and 236 and the compression test result output unit 238 may be provided to output a normal / bad state as a compression test detection signal ZIP.

The first compression unit 232 compresses a plurality of first data values DAT1_A, DAT1_B, and DAT1_C and reference data values DAT_REF, and includes a plurality of first data values DAT1_A, DAT1_B, and DAT1_C and reference data. A first exclusive negative logic gate XNOR1 that receives a value DAT_REF may be provided. The second compression unit 234 compresses the plurality of second data values DAT2_A, DAT2_B, and DAT2_C and the reference data values DAT_REF, and the second data values DAT2_A, DAT2_B, DAT2_C and the reference data values ( A second exclusive negative logic gate XNOR2 receiving the DAT_REF may be provided. The third compression unit 236 compresses the plurality of third data values DAT3_A, DAT3_B, and DAT3_C and the reference data values DAT_REF. The third compression unit 236 and the third data values DAT3_A, DAT3_B, and DAT3_C and the reference data values ( A third exclusive negative logic gate XNOR3 receiving the DAT_REF may be provided. Here, the first data values DAT1_A, DAT1_B, and DAT1_C, the second data values DAT2_A, DAT2_B, and DAT2_C, and the third data values DAT3_A, DAT3_B, and DAT3_C are stored in data stored in the plurality of grouped memory cells. The corresponding value.

Subsequently, the compression test result output unit 238 outputs the compression test detection signal ZIP in response to the output signals of the first to third compression units 232, 234, and 236. A third inverter configured to receive a negative logic gate NAND for receiving the output signals of the units 232, 234, 236, and an output signal of the negative logic gate NAND, and output a compression test detection signal ZIP; INV3).

Hereinafter, the compression test operation according to the present invention will be briefly described. For convenience of explanation, it is assumed that a logic 'high' is stored in a memory cell to be subjected to a compression test, and a plurality of first to third data values DAT1_A, DAT1_B, DAT1_C, DAT2_A, DAT2_B, DAT2_C, DAT3_A, DAT3_B, and DAT3_C) are also assumed to be logic 'high'.

First, the reference data value DAT_REF stored in the reference data value storage unit 210 corresponds to a plurality of first to third data values DAT1_A, DAT1_B, DAT1_C, DAT2_A, DAT2_B, DAT2_C, DAT3_A, DAT3_B, and DAT3_C. It must have a value that is Therefore, the reference data value DAT_REF must also have a logic 'high', and for this purpose, the test signal TM preferably has a logic 'low'.

The first compressor 232 compresses the first data values DAT1_A, DAT1_B, and DAT1_C and the reference data value DAT_REF, and the second compressor 234 compresses the second data values DAT2_A, DAT2_B, and DAT2_C. The reference data value DAT_REF is compressed, and the third compression unit 236 compresses the third data values DAT3_A, DAT3_B, and DAT3_C and the reference data value DAT_REF. The compression test result output unit 238 outputs the compression results of the first to third compression units 232, 234, and 236 as a compression test detection signal ZIP, and the test operator performs normal operation of the plurality of memory cells. Judge for defects.

For convenience of description, the first compression unit 232 will be described as a representative. If logic 'high' is normally stored in a plurality of memory cells and a read operation is normally performed, all of the first data values DAT1_A, DAT1_B, and DAT1_C have data values of logic 'high'. Here, since the reference data value DAT_REF becomes a logic 'high', the first compression unit 232 receives all of the same data values as the logic 'high'. That is, the first exclusive negative logic gate XNOR1 of the first compression unit 232 outputs a logic of 'high'. In this manner, the second and third exclusive negative logic gates XNOR2 and XNOR3 also output true of logic 'high', and finally the compression test detection signal ZIP outputs true of logic 'high'. The tester can determine that the semiconductor memory device is normal.

For example, assuming that the first data values DAT1_A, DAT1_B, and DAT1_C are all inverted logic 'low' due to a failure of the semiconductor memory device, the first exclusive negative logic gate XNOR1 is the reference data of logic 'high'. According to the value DAT_REF, a logic 'low' is outputted. The compression test detection signal ZIP then outputs false, which is logic 'low'. The tester can determine that the semiconductor memory device is defective. In the conventional case, if it outputs true in the same situation, the compression test detection signal ZIP of the present invention can be regarded as a more reliable test result than the conventional.

That is, in the conventional circuit, when generating the compression test detection signal ZIP, it is simply determined whether a plurality of first to third data values have the same value. True even when reversed due to a defect. However, according to the present invention, it is determined whether the first to third data values DAT1_A, DAT1_B, DAT1_C, DAT2_A, DAT2_B, DAT2_C, DAT3_A, DAT3_B, and DAT3_C are all the same values in generating the compression test detection signal ZIP. At the same time, since the first to third data values DAT1_A, DAT1_B, DAT1_C, DAT2_A, DAT2_B, DAT2_C, DAT3_A, DAT3_B, DAT3_C and the reference data value DAT_REF can be determined to be equal to each other, the same situation as before. It is possible to detect falsehoods even if they occur. This can more reliably determine whether a plurality of memory cells are normal or defective. That is, it is possible to increase the reliability of the test results and further, the semiconductor memory device to be mass-produced later.

Although the technical spirit of the present invention has been described in detail according to the above-described preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible with various substitutions, modifications, and changes within the scope of the technical idea of the present invention.

In addition, in the above-described embodiment, a case in which false is detected when all data is defective has been described as an example. However, according to the design, a correct detection result can be output even when a failure occurs in all or less data. This may apply even if present.

In addition, the logic gate and the transistor illustrated in the above embodiment should be implemented in different positions and types depending on the polarity of the input signal.

1 is a circuit diagram for explaining a conventional compression test operation.

2 is a circuit diagram for explaining a compression test operation according to the present invention.

* Explanation of symbols for the main parts of the drawings

210: reference data value storage unit

230: compression test result detection unit

Claims (5)

Storage means for storing reference data values corresponding to the test signals; Compression test result detection means for outputting a normal / defect status of the plurality of memory cells as a compression test detection signal by comparing the data values corresponding to the plurality of memory cells with the reference data values. A semiconductor memory device having a. The method of claim 1, The reference data value has a value corresponding to a data value stored in the plurality of memory cells. The method of claim 1, The compression test result detection means, A plurality of compression units for grouping the plurality of memory cells, and compressing data values corresponding to each of the grouped plurality of memory cells and the reference data value; And an output unit configured to output the compression test detection signal in response to output signals of the plurality of compression units. Storing the reference data value in response to the test signal; Determining whether the memory cells are normal or defective by compressing data values corresponding to the plurality of memory cells and the reference data values, The determining of whether the data is normal or defective comprises determining that the data values stored in the plurality of memory cells are normal when the data values correspond to the reference data values. The method of claim 4, wherein The step of determining whether the normal / defective, Determining whether data values corresponding to the plurality of memory cells are the same value; And determining whether the same value and the reference data value are the same.
KR1020080063136A 2008-06-30 2008-06-30 Semiconductor memory device and method for testing the same KR20100003040A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8782476B2 (en) 2011-04-25 2014-07-15 Hynix Semiconductor Inc. Memory and test method for memory

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8782476B2 (en) 2011-04-25 2014-07-15 Hynix Semiconductor Inc. Memory and test method for memory

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