KR20080079753A - Method and apparatus for testing memory - Google Patents

Abstract

A method for testing a memory and an apparatus therefore are provided to detect an error of the memory accurately through simultaneous compressing method. According to an apparatus for testing a memory including a plurality of memory regions, a test control part(300) outputs a control signal to write and read test data to/from the memory. An address generation part(302) outputs an address signal according to the control of the test control part. A test pattern generation part outputs the test data according to the control of the test control part. A test result analysis part(306) reads 1 bit data from each memory region, and inputs the k bit data to a data compressing part including k-input logic gates and then compresses the k bit data, and judges failure of the memory through a test result flag outputted through the compressing.

Description

Memory test method and device {Method and Apparatus for testing Memory}

1 is a diagram illustrating an example of a data compression process in a memory test according to the prior art.

2 illustrates another example of a data compression process in a memory test according to the prior art.

3 is a block diagram of a memory test system in accordance with one preferred embodiment of the present invention.

4 is a diagram illustrating a data compression process according to a first preferred embodiment of the present invention.

5 is a diagram illustrating a data compression process according to a second preferred embodiment of the present invention.

6 is a block diagram showing an example of a logic gate configuration of a data compression unit according to the present invention;

7 is a flowchart of a memory test process according to the first embodiment of the present invention.

8 is a flowchart of a memory test process according to the second embodiment of the present invention.

The present invention relates to a memory test method and an apparatus, and more particularly, to a method and an apparatus capable of improving a fault coverage during a memory test by improving a compression scheme.

In recent years, the density of circuits on a single chip is rapidly increasing due to the development of design process technology along with the demand for high performance, high functionality, and miniaturization of a system.

Ultra-integrated semiconductor design and fabrication technology capable of integrating more than 20 million transistors in one chip, and the accumulated rich design library have been integrated into a highly integrated chip by embedding various types of cores already designed and proven on one chip. SOC: System-on-Chip.

System-on-chip uses reusable cores, greatly reducing the time needed to develop new systems, enabling lower power, versatility and miniaturization.

However, as modules such as memory are embedded in one chip with the core, testing memory failures becomes an important issue. A method of writing predetermined test data into a memory cell array for testing a memory, reading the written data, and comparing it with an output value in normal operation is mainly used.

Comparing the data read from all memory cells with the output during normal operation requires a large amount of storage capacity and increases hardware overhead, so it is not possible to read from the memory under test (eg RAM, ROM, etc.) during the test process. A method of compressing data to generate a flag and detecting a memory failure through a flag is widely used.

1 is a diagram illustrating an example of a data compression process in a memory test according to the prior art.

FIG. 1 is a diagram illustrating a process of generating a flag by compressing 1-bit data read in four memory areas M0 to M3 and 100 to 106 by 2 bits.

Here, each of the memory areas 100 to 106 is a physically divided area in one memory, and may be a bank area having a predetermined size, or a block area having a predetermined size in one bank. Can be.

Conventionally, data read in the first and second memory areas 100 and 102 is compressed through the first XOR logic 108, and data read in the third and fourth memory areas 104 and 106 is compressed to the second XOR logic 110. ) Is compressed.

Here, the first and second XOR logics 108 and 110 are implemented as two-input exclusive OR gates, and the compressed data is output as a test result flag while passing through the OR gate 112.

In general, the normal operation flag is set to a high (logical value 1) or a low (logical value 0), and the test result flag is high or low to detect whether a memory has failed.

However, according to the prior art as shown in FIG. 1, when bit0 and bit1 input to the first XOR logic 108 have an error at the same time, that is, when there is a failure in both the memory cells outputting bit0 and bit1, the test result flag. Has the same problem as that in the normal operation flag, so that a failure of the memory cell cannot be detected.

This is true even when bit2 and bit3 input to the second XOR logic 110 have an error at the same time.

For example, when the normal operation flag is set to low and writes data of a logic value '0' to memory cells corresponding to bit0 to bit3 of each memory area, and reads it out, if the normal data is read out, an exclusive logical sum By the gate, the first XOR logic 108 and the second XOR logic 110 respectively output logic values '0', and they pass through the OR gate 112 to finally output the '0' flag.

However, when a specific memory cell in the M0 and M1 memory regions 100 and 102 has failed and bit0 and bit1 output a logic value '1', the first XOR logic 108 outputs a logic value '0' by an exclusive OR. Therefore, the final flag is '0'.

This is true even when both the M2 and M3 memory areas 104 and 106 have a fault.

In other words, when the 2-input XOR logic is used in the memory test method that reads one bit data from four memory areas, if all data input to each XOR logic has an error, the test result flag is the same value as the flag in normal operation. There is a problem in that it is practically impossible to detect a fault because the output of the.

2 is a diagram illustrating another example of a data compression process in a memory test according to the prior art.

FIG. 2 compresses 4-bit data corresponding to adjacent memory cells in the same data set, that is, each memory area 100 to 106, into the first to fourth logics 200 to 206, and compresses the compressed data into the logical sum gate 112. FIG. Is a diagram illustrating a process of outputting a flag by passing through a.

However, such a test method provides a worse failure detection rate than the method shown in FIG.

This is because when one memory cell fails due to the characteristics of a memory manufacturing process, adjacent memory cells are also likely to fail. As a result, even though all adjacent memory cells have failed, the test result flag generated by compression is the same as the normal operation flag, so that an error cannot be accurately detected.

In the present invention, to solve the problems of the prior art as described above, it is proposed a memory test method and apparatus that can accurately detect the error of the memory through the simultaneous compression method.

Another object of the present invention is to provide a memory test method and apparatus capable of reducing test time through an efficient memory test.

In order to achieve the above object, according to a preferred embodiment of the present invention, in the method for testing a memory including a plurality of memory areas, (a) k (k is a natural number of 3 or more) memory areas Reading k 1-bit data from the; (b) inputting and compressing the k 1-bit data into a data compression unit including a k-input logic gate; And (c) determining whether the memory is faulty based on a test result flag output through compression by the data compression unit.

According to another aspect of the present invention, there is provided a method of testing a memory including a plurality of memory regions, comprising: (a) reading n-bit data from each of n (n is a natural number of two or more) memory regions; (b) combining each n-bit data into n data sets, wherein the preset data set is n-bit data; (c) inputting and compressing the combined data set into a plurality of data compression units including n-input logic gates; (d) generating a test result flag by calculating data output from the plurality of data compression units; And (e) determining whether the memory has failed based on the test result flag.

According to another aspect of the present invention, an apparatus for testing a memory including a plurality of memory areas, the apparatus comprising: a test controller for outputting a control signal for writing and reading test data into the memory; An address generator for outputting an address signal under control of the test controller; A test pattern generator configured to output the test data under the control of the test controller; And read 1 bit data from k memory regions (k is a natural number of 3 or more), input the compressed k bit data into a data compression unit including a k-input logic gate, and compress the compressed data. There is provided a memory test apparatus including a test result analyzer configured to determine whether a memory has failed through an output test result flag.

According to another aspect of the present invention, an apparatus for testing a memory including a plurality of memory areas, the apparatus comprising: a test controller for outputting a control signal for writing and reading test data into the memory; An address generator for outputting an address signal under control of the test controller; A test pattern generator configured to output the test data under the control of the test controller; And n-bit data are respectively read from n memory regions (n is a natural number of two or more), each n-bit data is combined into n data sets, and the preset data set is n-bit data. A test result of determining whether a memory is broken through a test result flag generated by inputting and compressing a data set into a plurality of data compression units including n-input logic gates, and calculating data output from the plurality of data compression units. There is provided a memory test apparatus comprising an analysis unit.

As the invention allows for various changes and numerous embodiments, particular embodiments will be illustrated in the drawings and described in detail in the written description. However, this is not intended to limit the present invention to specific embodiments, it should be understood to include all modifications, equivalents, and substitutes included in the spirit and scope of the present invention. In describing the drawings, similar reference numerals are used for similar elements.

Terms such as first, second, A, and B may be used to describe various components, but the components should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be referred to as the second component, and similarly, the second component may also be referred to as the first component. The term and / or includes a combination of a plurality of related items or any item of a plurality of related items.

When a component is referred to as being "connected" or "connected" to another component, it may be directly connected to or connected to that other component, but it may be understood that other components may be present in between. Should be. On the other hand, when a component is said to be "directly connected" or "directly connected" to another component, it should be understood that there is no other component in between.

The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of the present invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this application, the terms "comprise" or "have" are intended to indicate that there is a feature, number, step, operation, component, part, or combination thereof described in the specification, and one or more other features. It is to be understood that the present invention does not exclude the possibility of the presence or the addition of numbers, steps, operations, components, components, or a combination thereof.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art. Terms such as those defined in the commonly used dictionaries should be construed as having meanings consistent with the meanings in the context of the related art and shall not be construed in ideal or excessively formal meanings unless expressly defined in this application. Do not.

 Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the following description of the present invention, the same reference numerals will be used for the same means regardless of the reference numerals in order to facilitate the overall understanding.

3 is a block diagram of a memory test system according to an exemplary embodiment of the present invention.

As shown in FIG. 3, the memory test system according to the present invention corresponds to a test controller 300, an address generator 302, a test pattern generator 304, a test result analyzer 306, and a test target circuit. Memory 308 may be included.

The test controller 300 performs a test start, end, and determination process, and controls the operations of the address generator 302, the test pattern generator 304, and the test result analyzer 306 for the self test during the test mode. do

The test control unit 300 outputs an address generation control signal (Address Order) for selecting a memory cell in which data is written or read in the test mode, a test data generation control signal (Data select) for writing data, and also generates an address generation. A clock AGL_CLK for outputting a clock, a clock TCLK for timing operation of writing or reading data into a memory cell, and a clock DCL_CLK for analyzing a test result are output.

The address generator 302 receives the address generation control signal described above to generate an address in the test mode. The address generator 302 may include a counter to sequentially generate addresses in an increasing or decreasing direction.

The test pattern generator 304 generates data to be written in each memory cell according to a control signal applied from the test controller 300.

The address and data generated through the above process are input to the memory 308 through the first mux 310 and the second mux 312, respectively.

In addition, the test clock TCLK output from the test controller 300 is input to the memory 308 through the third mux 314, activates the memory cell to be tested, and writes data to the activated memory cell. Alternatively, the test control signal Test CTR for reading is input to the memory 308 through the fourth mux 316.

When the first to fourth muxes 310 to 316 are in the test mode, the first mux to fourth mux are inputted from the processor connected to the memory 308, the normal data, the clock CLK, and the control signal. Normal CTR) is muxed so that only the address / data / clock / control signals input in the test mode are selectively input to the memory 308.

The memory 308 writes or reads data into a memory cell array having a word line and a bit line at the request of a processor or a request of a test controller. The memory 308 may be a random access memory (RAM) or a read only memory (ROM). In more detail, it may be a static RAM (SRAM), a dynamic RAM (DRAM), a flash memory, an erasable programmable ROM (EPROM), or an electrically erasable PROM (EEPROM).

The memory 308 receives an address, a control signal, a clock, and data from a processor (not shown), decodes the address into a row address and a column address, and according to an operation timing set in advance in a memory cell corresponding to the decoded address. Read or write data.

For this purpose, the memory 308 may include a memory interface (not shown), and the memory interface may include a command decoder (not shown), a row decoder (not shown), and a column decoder. (Not shown) and an input / output buffer (not shown).

Meanwhile, the memory cell array may be divided into a plurality of memory regions 400 to 406, as illustrated in FIGS. 4 to 5. The plurality of memory areas may be a bank area having a predetermined size physically divided, or may be a block area having a predetermined size in one bank.

In the test mode, data written to an individual memory area is read under the control of the test controller 300.

The test result analyzer 306 processes the read data and outputs a memory failure or normal signal through the test result flag.

According to an exemplary embodiment of the present invention, the test result analyzer 306 simultaneously compresses the data output from the individual memory areas 400 to 406 to generate a test result flag, thereby detecting whether the memory is broken. do.

In this case, since the flag may be preset to low or high in the normal operation, when the test result flag is generated through the compression of the read data as described above, the test result analyzer 306 determines whether the memory has failed. Can be detected.

4 is a diagram illustrating a data compression process according to a first embodiment of the present invention. The test result analyzer 306 according to the present invention may include a data compressor 408.

As shown in FIG. 4, the data compression unit 408 according to the first embodiment of the present invention has k bits of 1 bit each from k memory regions 400 to 406 (k is a natural number of 3 or more). Receive and compress data simultaneously.

4 illustrates the case where k is 4.

The data compression unit 408 is implemented to output the same value as the normal operation flag only when the data read out through the simultaneous compression of the data read out from the individual memory areas 400 to 406 are all normal and if all are in error.

6 is a block diagram illustrating an example of a logic gate configuration of a data compression unit according to the present invention.

Referring to FIG. 6, the data compressor 408 according to the first exemplary embodiment of the present invention may include an AND logic 600, an inverse logical gate 602, and a two input OR logic gate. 604).

According to the first embodiment of the present invention, as described above, in the case of reading 1-bit data from the k individual memory areas 400 to 406, the data compression unit 408 according to the present invention has a k-input logic gate. That is, it may include a k-input AND gate 600 and a k-inverse logical gate (602).

Hereinafter, when k is 4, the flag generation process of the data compression unit 408 will be described.

For example, when a logic value '0' is written to each memory area 400 to 406, the data bits 0 to bit3 read out from each memory area 400 to 406 become a logic value '0000' during normal operation. .

When the read data is input to the 4-input AND gate 600 of FIG. 6, the output A becomes a logic value '0', and when the inputted data is input to the 4-input logical logic gate 602, the output B becomes a logic value '1'. 'Becomes. Accordingly, the test result flag output through the 2-input OR gate 604 in normal operation becomes '1'.

However, if there is an error in at least one of the read data (for example, at least one of bit0 to bit3 is the logic value '1'), the four-input AND gate 600 sets the logic value '0' to four. The input inverse logic gate 602 outputs a logic value '0'.

As a result, the final test result flag is '0'.

Meanwhile, according to the present invention, when all memory cells to be compressed have a failure, that is, in the above example, when bit0 to bit3 are all logic values' 1111 ', the four-input AND gate 600 is' 1. ', The 4-input inverse logic gate 602 outputs' 1' so that the test result flag is output as' 1 '. That is, the data compression unit 408 according to the present invention outputs the same value as the normal operation flag only when all input data is an error.

Conventionally, although compression is performed to some groups of individual memory areas, the present invention compresses all the data read from different memory areas at the same time, so that if there is an error in at least one read data, a failure of the memory cell may be detected. If only all the data read out have an error, the failure cannot be detected, and the failure detection rate can be further improved.

5 is a diagram illustrating a data compression process according to a second preferred embodiment of the present invention.

According to the second embodiment of the present invention, n-bit data is read from n memory areas 400 to 406 (n is a natural number of two or more), and the read data is combined into a preset data set to perform compression. .

When the test is performed in units of words, as described above, n bits of data may be read from each memory area 400 to 406.

FIG. 5 illustrates a case where n is 4, and 4-bit data read in each memory area 400 to 406 is data read from a neighboring memory cell.

Referring to FIG. 5, the data combiner 500 according to the present invention combines each 4-bit data read from each memory area 400 to 406 and outputs the combined data to the first to fourth data compressors 502 to 508. do.

Herein, the process of combining the read 4-bit data is performed by separating the 4-bit data read in each of the memory areas 400 to 406 and using different data areas 400 to 508 as shown in FIG. 5. A process of allowing 1-bit data corresponding to 406 to be simultaneously input.

The combination process is performed to prevent memory cell data existing in different memory areas that are physically separated from each other instead of adjacent memory cells to generate the same value as a normal operation flag even in the case of a failure.

For example, as illustrated in FIG. 5, bit0 to bit3 in the first memory area 400, bit4 to bit7 in the second memory area 402, and bit8 to bit11 and fourth in the third memory area 404. When data corresponding to bits 12 to bit 15 are read from the memory area 406, the data combination unit 500 according to the present invention may use bit 0, bit 4, bit 8, and 4 bit data among the 4 bit data output from the memory areas 400 to 406. Generate a first data set comprising bit12.

The first data set has four bits, i.e., the same number of bits as the read data, and includes one-bit data corresponding to each of the memory areas 400 to 406 without overlapping.

The first data set is simultaneously input to the first data compressor 502 and compressed.

In addition, the data combination unit 500 inputs each memory area (2) so that bit1, bit5, bit9 and bit13 (second data set) corresponding to the second bit of each 4-bit data are input to the second data compression unit 504. In step 400 to 406, a process of combining the data read is performed.

Through the above process, bit2, bit6, bit10, and bit14 (third data set) corresponding to the third bit of each 4-bit data are input to the third data compressor 506, and the fourth data compressor 508 ), Bit3, bit7, bit11 and bit15 (fourth data set) corresponding to the fourth bit of each 4-bit data are input.

In the above description, a combination of data sets including bit data corresponding to the same position in each 4-bit data has been described. However, the combination method may be variously implemented unless bit data input to each data compression unit is overlapped with each other. Those skilled in the art will understand that there is.

The n data compression units 502 to 508 according to the present invention do not overlap bit data corresponding to predetermined positions of the n bit data read from the four memory areas 400 to 406 through the data combining process. Is entered.

Meanwhile, when the combined data sets are input, the first to fourth data compression units 502 to 508 perform a process of compressing the data input through the logic gate shown in FIG. 6.

According to the second embodiment of the present invention, the number of inputs of the AND gate 600 and the inverse logical gate 602 of FIG. 6 may be determined according to the number of bits of data read from each individual memory area 400 to 406. have.

That is, each data compression unit according to the second embodiment of the present invention may include an n-input logic gate having n input numbers of the AND gate 600 and the inverse logical gate 602.

Since the data compression process has been described above in detail with reference to FIG. 6, a detailed description thereof will be omitted.

7 is a flowchart of a memory test process according to a first embodiment of the present invention.

Referring to FIG. 7, in the test mode, the test controller 300 outputs a control signal / address / data for writing data to a memory for testing (step 700).

The test data is written in k memory areas that are physically divided according to the signal of the test controller 300 (step 702). In the first embodiment of the present invention, k is a natural number of three or more.

In the memory test, the same test data is preferably written in a memory cell (a memory cell in which data simultaneously input to the data compression unit of FIG. 4) is used as a unit for generating a flag.

On the other hand, when the test control unit 300 outputs an address and a control signal for reading data, one bit of data is read from k memory areas (step 704).

The test result analyzer 306 compresses the read data through a data compression unit including a k-input logic gate having an input equal to the number of the memory areas described above (step 706).

According to the above-described process, since the same value as the normal operation flag is generated only when all data corresponding to the k-input are normal or all have an error, the failure detection rate can be further improved.

The test result flag is generated through the compression process (step 708), and the test result analyzer 306 outputs a valid or invalid signal through the test result flag (step 710).

8 is a flowchart of a memory test process according to a second embodiment of the present invention.

Referring to FIG. 8, in the test mode, the test controller 300 outputs a control signal / address / data for writing data to a memory for testing (step 800).

The test data is written to n memory areas physically divided according to the signal of the test controller 300 (step 802). In the second embodiment of the present invention, n is a natural number of two or more.

In addition, in the second embodiment of the present invention, it is preferable that the same test data is written in the memory cells (memory cells in which data simultaneously input to the respective data compression units of FIG. 5 are read).

On the other hand, when the test control unit 300 outputs an address and a control signal for reading data, n-bit data is read from the n memory areas, respectively (step 804).

The read n-bit data is combined into n data sets through a combination process according to the present invention, and each data set is output to the corresponding n data compressors (step 806).

In this case, the combining process is a process of generating n data sets from n bit data read from each memory area 400 to 406.

The data set produced by the combination is compressed in a data compression section containing n-input logic gates (step 808).

The compression result test result flag is generated (step 810), and the test result analyzer 306 outputs a normal or fault signal through the test result flag (step 812).

According to the above process, since memory cell data existing in different memory areas that are physically separated from each other rather than adjacent memory cells is compressed, a value equal to the normal operation flag can be prevented from being generated even in the case of a failure, and n- The data compression unit including the input logic gate generates the same value as the normal operation flag only when the input data has an error in its entirety, thereby increasing the failure detection rate.

Preferred embodiments of the present invention described above are disclosed for purposes of illustration, and those skilled in the art will be able to make various modifications, changes, and additions within the spirit and scope of the present invention. Additions should be considered to be within the scope of the following claims.

As described above, according to the first embodiment of the present invention, when reading one bit of data from at least three or more memory areas, data read from each memory area is simultaneously compressed, thereby increasing the failure detection rate. There is an advantage.

Further, according to the second embodiment of the present invention, when n bits of data are read in at least two memory areas, a failure detection rate is obtained by combining the n bits of data read in each memory area by compressing the data in another memory area. There is an advantage to increase.

Further, according to the second embodiment of the present invention, since the n-bit data input to each data compression unit is simultaneously compressed by the combination, there is an advantage that the failure detection rate can be increased.

In addition, according to the present invention there is an advantage that the memory test time can be shortened by a high failure detection rate.

Claims (15)

In the method for testing a memory including a plurality of memory areas, (a) reading k one-bit data from k memory regions where k is a natural number of three or more; (b) inputting and compressing the k 1-bit data into a data compression unit including a k-input logic gate; And and (c) determining whether the memory is faulty based on a test result flag output through compression by the data compression unit. The method of claim 1, And the k memory regions are at least one of a bank region having a predetermined size and a block region having a predetermined size within the bank region. The method of claim 1, And the data compression unit comprises a k-input AND gate, a k-input INOR gate, and a two-input OR gate to which the outputs of the AND and IN logic gates are input. In the test method of a memory including a plurality of memory areas, (a) reading n-bit data from n memory regions where n is a natural number of two or more; (b) combining each n-bit data into n data sets, wherein the preset data set is n-bit data; (c) inputting and compressing the combined data set into a plurality of data compression units including n-input logic gates; (d) generating a test result flag by calculating data output from the plurality of data compression units; And (e) determining whether the memory has failed based on the test result flag. The method of claim 4, wherein The n memory areas are at least one of a bank area having a predetermined size and a block area having a predetermined size within the bank area. The method of claim 4, wherein And the combined data set includes 1-bit data corresponding to each memory area. The method of claim 4, wherein The combined data set is a set of bit data corresponding to the same position among n-bit data corresponding to each memory area. The method of claim 4, wherein And said combined data set includes the same bit data in normal operation. The method of claim 4, wherein And each of the plurality of data compression units outputs a test result flag identical to a normal operation flag when n inputs are all normal and all errors are present. The method of claim 4, wherein And the data compression unit comprises an n-input AND gate, an n-input INOR gate, and a two-input OR gate to which outputs of the AND gate and the inverse AND gate are input. An apparatus for testing a memory including a plurality of memory regions, the apparatus comprising: A test controller configured to output a control signal for writing and reading test data into the memory; An address generator for outputting an address signal under control of the test controller; A test pattern generator configured to output the test data under the control of the test controller; And 1 bit data is read from k memory regions (k is a natural number of 3 or more), and the read k-bit data is inputted to a data compression unit including a k-input logic gate and compressed, and output through the compression. And a test result analyzer to determine whether the memory has failed through the test result flag. The method of claim 11, And the data compression unit comprises a k-input AND gate, a k-input INOR gate, and a two-input OR gate to which outputs of the AND and IN logic gates are input. An apparatus for testing a memory including a plurality of memory regions, the apparatus comprising: A test controller configured to output a control signal for writing and reading test data into the memory; An address generator for outputting an address signal under control of the test controller; A test pattern generator configured to output the test data under the control of the test controller; And n-bit data is read from n memory regions (n is a natural number of two or more), and each n-bit data is combined into n data sets, and the preset data set is n-bit data. Analyzing the test result by inputting the set into a plurality of data compression units including n-input logic gates and compressing the data, and determining whether the memory has failed through a test result flag generated by calculating data output from the plurality of data compression units. A memory test apparatus comprising a portion. The method of claim 13, And the combined data set includes 1-bit data corresponding to each memory area. The method of claim 13, And the data compression unit comprises an n-input AND gate, an n-input AND logic gate, and a two-input OR gate to which outputs of the AND gates and the inverse AND gate are input.

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