KR20100002874A - Semiconductor package - Google Patents

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Publication number
KR20100002874A
KR20100002874A KR1020080062923A KR20080062923A KR20100002874A KR 20100002874 A KR20100002874 A KR 20100002874A KR 1020080062923 A KR1020080062923 A KR 1020080062923A KR 20080062923 A KR20080062923 A KR 20080062923A KR 20100002874 A KR20100002874 A KR 20100002874A
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South Korea
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substrate
insulating layer
semiconductor chip
semiconductor package
electrical connection
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KR1020080062923A
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Korean (ko)
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도은혜
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주식회사 하이닉스반도체
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Priority to KR1020080062923A priority Critical patent/KR20100002874A/en
Publication of KR20100002874A publication Critical patent/KR20100002874A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Abstract

PURPOSE: A semiconductor package is provided to improve connection reliability of the semiconductor package by forming a BGA package type semiconductor package including a guide unit made of the same material as the substrate. CONSTITUTION: A substrate includes an insulation layer. A guide unit(120) is formed on the insulation layer. The semiconductor chip is attached on the upper side of the substrate. An electric connection unit connects the semiconductor chip and the substrate. A capping unit(150) is formed in an inner side of the guide unit to cover the electric connection unit and the semiconductor chip on the upper side of the substrate.

Description

반도체 패키지{Semiconductor package}Semiconductor Package {Semiconductor package}

본 발명은 반도체 패키지에 관한 것으로서, 보다 상세하게는, 반도체 패키지를 구성하는 이종 물질들 간의 접합 신뢰성을 향상시킬 수 있는 반도체 패키지에 관한 것이다. The present invention relates to a semiconductor package, and more particularly, to a semiconductor package capable of improving the bonding reliability between different materials constituting the semiconductor package.

반도체 산업에서 집적회로에 대한 패키징 기술은 소형화에 대한 요구 및 실장 신뢰성을 만족시키기 방식으로 발전되어 왔다. 예컨데, 소형화에 대한 요구는 칩 크기에 근접한 패키지에 대한 기술 개발을 가속화시켰으며, 실장 신뢰성에 대한 요구는 실장작업의 효율성 및 실장후의 기계적·전기적 신뢰성을 향상시킬 수 있는 패키징 기술에 대한 중요성을 부각시켰다. In the semiconductor industry, packaging technology for integrated circuits has been developed in a manner that satisfies the demand for miniaturization and mounting reliability. For example, the demand for miniaturization has accelerated the development of technology for packages that are close to chip size, and the demand for mounting reliability highlights the importance of packaging technologies that can improve the efficiency of mounting and mechanical and electrical reliability after mounting. I was.

패키지의 소형화를 이룬 한 예로서, BGA(Ball Grid Array) 패키지를 들 수 있으며, 상기 일반적인 BGA 타입의 반도체 패키지는 절연막의 상하면에 금속배선 및 솔더마스크가 형성된 기판 상에 배치된 반도체 칩과 상기 반도체 칩과 기판 간에 전기적인 연결하는 금속와이어 및 상기 반도체 칩을 보호하기 위하여 기판 상에 형성된 봉지부를 포함하여 이루어진다. As an example of miniaturization of a package, a BGA (Ball Grid Array) package may be used. The general BGA type semiconductor package includes a semiconductor chip and a semiconductor disposed on a substrate on which upper and lower surfaces of an insulating layer are formed with metal wiring and solder mask. It comprises a metal wire for electrically connecting between the chip and the substrate and an encapsulation formed on the substrate to protect the semiconductor chip.

상기 BGA 패키지는 전체적인 패키지의 크기가 반도체 칩의 크기와 동일하거 나 거의 유사하다. 특히, 외부회로와의 전기적 실장 수단으로서, 솔더볼이 구비됨에 따라 실장 면적을 최소화시킬 수 있고, 솔더볼에 의해 외부 회로와의 전기적 연결이 이루어지므로 전기적 신호 전달 경로의 최소화를 통해 향상된 전기적 특성을 갖는다.The BGA package has an overall package size that is substantially the same as or similar to that of a semiconductor chip. In particular, as an electric mounting means with an external circuit, the mounting area can be minimized as the solder ball is provided, and since the electrical connection with the external circuit is made by the solder ball, the electrical signal is improved through the minimization of the electric signal transmission path.

그러나, 상기 BGA 타입 반도체 패키지는 흡습률이 각각 약 0.2%, 1.5% 및 0.4%인 절연막, 솔더마스크 및 봉지부와 같은 이종 물질들이 접합되어 있음에 따라 상기 흡습률 및 열팽창계수의 차이에 따라 반도체 패키지에 크랙 등이 발생할 수 있으며 계면 박리 등이 발생하여 접합 신뢰성이 나쁘다. However, the BGA type semiconductor package has a semiconductor according to a difference in moisture absorption rate and thermal expansion coefficient as heterogeneous materials such as an insulating film, a solder mask, and an encapsulation portion having a moisture absorption rate of about 0.2%, 1.5%, and 0.4% are bonded to each other. Cracks may occur in the package, and interfacial peeling may occur, resulting in poor bonding reliability.

또한, 반도체 칩과 기판 간을 전기적으로 연결하는 금속와이어의 보호를 위한 봉지부 형성 공정의 작업성을 향상시키기 위하여 상기 기판 상에 부착되어 있는 반도체 칩 상면으로 공간적인 마진의 확보가 필요함에 따라 박형 반도체 패키지를 형성하는데 한계가 있다.In addition, in order to improve the workability of the encapsulation forming process for protecting the metal wires electrically connecting the semiconductor chip and the substrate, it is necessary to secure a spatial margin to the upper surface of the semiconductor chip attached to the substrate. There is a limit in forming a semiconductor package.

본 발명은 반도체 패키지를 구성하는 이종 물질들 간의 접합 신뢰성을 향상시킬 수 있는 반도체 패키지를 제공한다.The present invention provides a semiconductor package capable of improving the bonding reliability between the dissimilar materials constituting the semiconductor package.

본 발명에 따른 반도체 패키지는, 절연층을 포함하는 기판; 상기 기판 가장자리의 절연층 상에 형성된 가이드부; 상기 기판 상면에 부착된 반도체 칩; 상기 반도체 칩과 기판 간을 연결하는 전기적 연결 부재; 및 상기 기판의 상면에 상기 반도체 칩 및 전기적 연결 부재를 덮도록 상기 가이드부의 내측에 형성된 캡핑부를 포함한다.A semiconductor package according to the present invention includes a substrate including an insulating layer; A guide part formed on the insulating layer at the edge of the substrate; A semiconductor chip attached to an upper surface of the substrate; An electrical connection member connecting the semiconductor chip to the substrate; And a capping part formed inside the guide part to cover the semiconductor chip and the electrical connection member on an upper surface of the substrate.

상기 절연층 상면의 상기 가이드부 내측과 상기 절연층 하면에 각각 형성된 금속배선 및 솔더마스크를 더 포함한다.Further comprising a metal wiring and a solder mask formed on the inner side of the guide portion of the upper surface of the insulating layer and the lower surface of the insulating layer.

상기 가이드부는 상기 절연층과 동일한 물질로 이루어지거나 상기 절연층과 흡습률이 동일한 물질로 이루어진다.The guide part may be made of the same material as the insulating layer, or may be made of a material having the same moisture absorption as the insulating layer.

상기 캡핑부는 에폭시로 이루어진다.The capping part is made of epoxy.

상기 가이드부의 최상단부는 상기 전기적 연결 부재의 최상단부보다 높은 높이를 갖는다.The top end of the guide portion has a height higher than the top end of the electrical connection member.

상기 전기적 연결 부재는 금속와이어 또는 범프이다.The electrical connection member is a metal wire or bump.

본 발명은 기판 상에 상기 기판과 동일한 물질로 이루어진 가이드부를 형성하여 BGA 패키지 타입의 반도체 패키지를 형성함에 따라, 이종 물질 간의 접합 계면이 줄어들어 반도체 패키지의 접합 신뢰성을 향상시킬 수 있으며, 또한, 상대적으로 흡습률이 낮은 기판의 절연층과 동일한 물질로 가이드부의 흡습 관련 신뢰성을 향상시킬 수 있다. According to the present invention, as the guide portion made of the same material as the substrate is formed on the substrate to form a BGA package type semiconductor package, the bonding interface between different materials can be reduced, thereby improving the bonding reliability of the semiconductor package. The moisture absorption-related reliability of the guide part may be improved by using the same material as the insulating layer of the substrate having a low moisture absorption rate.

또한, 종래 봉지부를 대신하여 반도체 칩 및 금속와이어를 보호하기 위하여 캡핑부을 형성함으로써 금속와이어에 대한 종래 봉지부 형성에 따른 공정성 확보를 위하여 필요하였던 반도체 칩 상부 마진의 확보가 필요 없어 얇은 두께를 갖는 반도체 패키지를 형성할 수 있다. In addition, by forming a capping portion to protect the semiconductor chip and the metal wire in place of the conventional encapsulation portion, a semiconductor having a thin thickness without the need to secure the upper margin of the semiconductor chip, which is necessary to secure the fairness according to the conventional encapsulation portion for the metal wire Packages may be formed.

아울러, 반도체 칩과 기판 간의 전기적인 연결을 범프를 통하여 형성하는 경우, 캡핑부 형성 공정으로 상기 반도체 칩을 보호함에 따라 반도체 칩과 기판 간에 범프의 전기적 연결 신뢰성을 향상시키기 위하여 사용되는 충진재의 형성 공정이 필요없어 제조 공정을 간소화할 수 있으며, 이에 따라, 종래 충진재와 봉지부와의 접합 계면 불량을 원천적으로 방지할 수 있다. In addition, when the electrical connection between the semiconductor chip and the substrate is formed through the bumps, a process of forming a filler used to improve the electrical connection reliability of the bumps between the semiconductor chip and the substrate as the semiconductor chip is protected by a capping part forming process. Since it is not necessary, the manufacturing process can be simplified, and therefore, the conventional bonding interface defect between the filler and the sealing portion can be prevented at the source.

이하에서는, 본 발명의 실시예에 따른 반도체 패키지 및 그의 제조 방법을 상세히 설명하도록 한다.Hereinafter, a semiconductor package and a method of manufacturing the same according to an embodiment of the present invention will be described in detail.

도 1은 본 발명의 일 실시예에 따른 반도체 패키지를 도시한 도면이다.1 illustrates a semiconductor package according to an embodiment of the present invention.

도시된 바와 같이, 본 발명에 따른 BGA 타입 반도체 패키지(100)는 기판(110)의 가장자리 부분에 구비된 가이드부(120) 및 상기 기판(110)의 상면에 형성된 캡핑부(150)를 포함하여 이루어진다.As shown, the BGA type semiconductor package 100 according to the present invention includes a guide part 120 provided at an edge of the substrate 110 and a capping part 150 formed on the upper surface of the substrate 110. Is done.

자세하게, 상기 기판(110)은 절연층(112)과 상기 절연층(112)의 상하면 및 내부에 패터닝되어 형성된 금속배선(114) 및 상기 금속배선(114)의 일부분이 노출되도록 상기 금속배선(114)을 포함한 상기 절연층(112)의 상하면에 형성된 솔더마스크(116)를 포함하여 이루어진다. 상기 금속배선(114) 및 솔더마스크(116)는 상기 절연층(112)의 가장자리 부분이 일부 길이로 노출되도록 형성되며, 즉, 상기 금속배선(114) 및 솔더마스크(116)는 상기 절연층(112) 상면의 상기 가이두부(120)의 내측 및 상기 절연층(112) 하면에 각각 형성되며, 상기 노출된 금속배선(114) 부분은 전기적인 연결을 위한 패드 및 볼랜드 부분으로 사용된다. In detail, the substrate 110 is patterned on the upper and lower surfaces of the insulating layer 112 and the insulating layer 112, and the metal wiring 114 is formed to expose portions of the metal wiring 114 and the metal wiring 114. It includes a solder mask 116 formed on the upper and lower surfaces of the insulating layer 112, including. The metallization 114 and the solder mask 116 are formed so that the edge portion of the insulating layer 112 is exposed to some length, that is, the metallization 114 and the solder mask 116 are formed in the insulating layer ( 112 is formed on the inner surface of the guide head portion 120 and the lower surface of the insulating layer 112, the exposed metal wiring 114 is used as a pad and a ball land portion for electrical connection.

상기 기판(110) 가장자리 부분의 노출된 절연층(112) 부분 상에는 상기 기판(110)을 구성하는 절연층(112)과 동일한 물질로 이루어지거나, 또는, 상기 절연층(112)과 동일한 흡습률을 갖는 물질로 이루어진 가이드부(120)가 배치된다. 상기 가이드부(120)는 반도체 패키지를 구성하는 이종 물질들 간의 접촉 면적을 줄여 반도체 패키지의 접합 신뢰성을 향상시키기 위해 형성한다. On the exposed portion of the insulating layer 112 at the edge of the substrate 110, the same material as that of the insulating layer 112 constituting the substrate 110 or the same moisture absorption rate as the insulating layer 112 is provided. Guide portion 120 made of a material having is disposed. The guide part 120 is formed to reduce the contact area between the dissimilar materials constituting the semiconductor package to improve the bonding reliability of the semiconductor package.

상기 기판(110) 상에는 반도체 칩(130)이 접착 부재를 매개로 부착되며, 상기 반도체 칩(130)과 기판(110)의 노출된 금속배선(114) 부분 사이에는 상기 반도체 칩(130)과 기판(110)을 전기적으로 연결시키기 위한 금속와이어(140)가 형성된다. The semiconductor chip 130 is attached to the substrate 110 through an adhesive member, and the semiconductor chip 130 and the substrate are disposed between the semiconductor chip 130 and the exposed metal wiring 114 of the substrate 110. The metal wire 140 for electrically connecting the 110 is formed.

상기 기판(110)의 상면에는 상기 기판(110)의 가장자리에 배치된 가이드부(120)의 내측으로 상기 반도체 칩(130) 및 금속와이어(140)를 감싸도록 캡핑부(150)가 형성된다. 상기 캡핑부(150)는 종래 BGA 패키지에서 사용되었던 봉지부를 대신하여 형성하는 것으로서, 상기 캡핑부(150) 형성 물질은 에폭시로 이루어진다. 상기 기판(110) 하면의 노출된 금속배선(114) 부분에는 외부와의 전기적인 연결을 위하여 솔더볼로 이루어진 외부접속단자(160)가 형성된다.A capping part 150 is formed on an upper surface of the substrate 110 to surround the semiconductor chip 130 and the metal wire 140 inside the guide part 120 disposed at the edge of the substrate 110. The capping part 150 is formed in place of the encapsulation part used in the conventional BGA package, and the capping part 150 forming material is made of epoxy. An external connection terminal 160 made of solder balls is formed on the exposed metal wiring 114 on the lower surface of the substrate 110 for electrical connection with the outside.

한편, 본 발명에 따른 BGA 타입 반도체 패키지는 도 2a 내지 도 2e에 도시된 바와 같은 방법으로 형성한다.Meanwhile, the BGA type semiconductor package according to the present invention is formed by the method shown in FIGS. 2A to 2E.

도 2a를 참조하면, 절연층(112)의 내부에 전기적인 연결을 위한 비아홀(V)들을 형성한 후, 상기 절연층(112)의 상하면에 상기 비아홀(V)이 매립되도록 금속층을 형성한다.Referring to FIG. 2A, after forming via holes V for electrical connection in the insulating layer 112, a metal layer is formed to fill the via holes V in the upper and lower surfaces of the insulating layer 112.

그런 다음, 상기 금속층을 패터닝하여 상기 절연층(112)의 상하면에 금속배선(114)을 형성한다. 상기 금속배선(114)은 후속 공정에서 상기 절연층(112)의 상면에 형성되는 가이드부의 형성을 위하여 상기 절연층(112)의 가장자리 부분에는 형성하지 않는다. Then, the metal layer is patterned to form metal wiring 114 on the upper and lower surfaces of the insulating layer 112. The metal wiring 114 is not formed at the edge portion of the insulating layer 112 to form a guide part formed on the upper surface of the insulating layer 112 in a subsequent process.

이어서, 상기 절연층(112)의 상하면에 상기 금속배선(114)을 덮도록 솔더레지스트를 도포한 후, 패터닝 공정을 수행하여 솔더마스크(116)가 형성된 기판(110)의 형성을 완료한다. 상기 솔더마스크(116)는 상기 절연층(112)의 상하면에 전기적인 연결을 위한 패드부(117) 및 볼랜드(118)로 사용되는 상기 금속배선(114)의 일부분을 노출시킴과 아울러 후속 공정에서 가이드부의 형성을 위하여 상기 절연층(112)의 가장자리 부분을 노출시키도록 형성한다.Subsequently, after the solder resist is applied to the upper and lower surfaces of the insulating layer 112 to cover the metal wiring 114, a patterning process is performed to complete the formation of the substrate 110 having the solder mask 116 formed thereon. The solder mask 116 exposes a portion of the metal wiring 114 used as the pad portion 117 and the borland 118 for electrical connection to the upper and lower surfaces of the insulating layer 112, and in a subsequent process. In order to form the guide part, the edge portion of the insulating layer 112 is formed to be exposed.

도 2b를 참조하면, 상기 기판(110) 상면의 상기 절연층(112) 가장자리 부분에 상기 절연층(112)과 동일한 물질로 이루어진 가이드부(120)를 형성한다. 상기 가이드부(120)는 반도체 패키지를 구성하는 이종물질 간의 접촉면적을 줄여 패키지의 접합 신뢰성을 향상시키기 위해 형성함과 아울러, 후속공정에서 형성되는 캡핑부의 형성시, 캡핑부 형성물질이 외부로 유출되지 않도록 하기 위하여 형성한다.Referring to FIG. 2B, the guide part 120 made of the same material as the insulating layer 112 is formed on the edge portion of the insulating layer 112 on the upper surface of the substrate 110. The guide part 120 is formed to reduce the contact area between the dissimilar materials constituting the semiconductor package to improve the bonding reliability of the package, and when the capping part is formed in a subsequent process, the capping part forming material leaks to the outside. It is formed so as not to be.

도 2c를 참조하면, 상기 가이드부(120)가 형성된 기판(110)의 상면에 접착 부재(미도시)를 매개로 반도체 칩(130)을 부착한다.Referring to FIG. 2C, the semiconductor chip 130 is attached to an upper surface of the substrate 110 on which the guide part 120 is formed through an adhesive member (not shown).

그런 다음, 상기 반도체 칩(130)과 상기 기판(110) 상면의 노출된 금속배선(114) 부분, 즉, 패드부(117) 사이에 상기 반도체 칩(130)과 기판(110) 간의 전기적인 연결을 위하여 금속와이어(140)를 형성한다.Then, the electrical connection between the semiconductor chip 130 and the substrate 110 between the semiconductor chip 130 and the exposed metal wiring 114 portion of the upper surface of the substrate 110, that is, the pad portion 117. To form a metal wire 140.

도 2d를 참조하면, 상기 반도체 칩(130)이 부착된 상기 기판(110) 상에 상기 반도체 칩(130) 및 금속와이어(140)를 덮도록 상기 가이드부(120)의 내측으로 에폭시로 이루어진 캡핑부(150)를 형성한다. 이를 위해, 상기 가이드부(120)는 상기 금속와이어(140)보다 높은 높이를 갖도록 형성할 필요는 없으나, 상기 캡핑부(150)가 상기 금속와이어(140)를 완전히 덮을 수 있도록 상기 금속와이어(140)의 최상단부보다 높은 높이로 형성하는 것이 바람직하다.Referring to FIG. 2D, a cap made of epoxy is formed inside the guide part 120 to cover the semiconductor chip 130 and the metal wire 140 on the substrate 110 to which the semiconductor chip 130 is attached. The ping part 150 is formed. To this end, the guide portion 120 does not need to be formed to have a higher height than the metal wire 140, but the metal wire 140 so that the capping portion 150 completely covers the metal wire 140. It is preferable to form the height higher than the uppermost end of the).

그런 다음, 상기 기판(110) 하면의 노출된 금속배선(114) 부분, 즉, 볼랜드(118) 부분에 외부와의 전기적인 연결을 위하여 솔더볼로 이루어진 외부접속단자(160)를 부착하여 본 발명에 따른 반도체 패키지의 제조를 완료한다.Then, an external connection terminal 160 made of solder balls is attached to the exposed metal wiring 114 portion, that is, the ball land 118 portion of the lower surface of the substrate 110 for electrical connection with the outside. The manufacture of the semiconductor package according to this is completed.

아울러, 본 발명에 따른 BGA 타입 반도체 패키지는, 도 3에 도시된 바와 같이, 반도체 칩(230)과 기판(210) 간의 연결을 범프(270)를 통하여 형성할 수 있다.In addition, in the BGA type semiconductor package according to the present invention, as shown in FIG. 3, a connection between the semiconductor chip 230 and the substrate 210 may be formed through the bump 270.

도시된 바와 같이, 기판(210)의 상면에 배치되는 반도체 칩(230)은 기판(210) 상면의 금속배선(214)과 연결되는 범프(230)를 통하여 전기적으로 연결된다. As illustrated, the semiconductor chip 230 disposed on the top surface of the substrate 210 is electrically connected to each other through a bump 230 connected to the metal wire 214 on the top surface of the substrate 210.

상기 기판(210)의 가장자리 부분에는 상기 기판(210)의 절연막(212)과 동일한 물질로 이루어진 가이드부(220)가 배치되며, 상기 기판(210)의 상면에는 상기 반도체 칩(230)을 덮음과 아울러, 동시에 상기 반도체 칩(230)과 기판(210) 사이의 공간에 캡핑부(250)가 형성된다. The guide portion 220 made of the same material as the insulating film 212 of the substrate 210 is disposed on the edge of the substrate 210, and the upper surface of the substrate 210 covers the semiconductor chip 230. At the same time, a capping part 250 is formed in a space between the semiconductor chip 230 and the substrate 210.

상기 캡핑부(250)는 종래 반도체 칩을 보호하기 위한 봉지부 및 상기 반도체 칩(230)과 기판(210) 사이에 형성되어 상기 범프(230)의 전기적 및 물리적 연결 신 뢰성을 향상시키기 위한 충진재의 역할을 동시에 갖는다. 상기 캡핑부(250)는 공정성의 향상을 위해 반도체 칩과 기판 사이에 1차적으로 형성 공정을 수행한 후, 상기 반도체 칩을 덮도록 2차적으로 형성 공정을 수행하여 형성할 수 있다. The capping part 250 is formed between an encapsulation part for protecting a conventional semiconductor chip and a filler for improving the electrical and physical connection reliability of the bump 230 by being formed between the semiconductor chip 230 and the substrate 210. Have a role at the same time. The capping part 250 may be formed by first performing a forming process between the semiconductor chip and the substrate to improve processability, and then performing a second forming process to cover the semiconductor chip.

이상에서와 같이, 본 발명에 따른 반도체 패키지는 종래 EMC(Epoxy molding compound)로 이루어진 봉지부와 기판의 솔더마스크 및 기판의 다른 3종류의 물질이 접합되어 열팽창계수 차에 의한 크랙 및 접합 신뢰성이 문제가 생기는 것을 방지하기 위해 기판의 가장자리에 절연막과 동일한 물질로 이루어진 가이드부을 형성한다. As described above, in the semiconductor package according to the present invention, an encapsulation portion made of an epoxy molding compound (EMC), a solder mask of a substrate, and three other materials of the substrate are bonded to each other, thereby causing problems in cracking and bonding reliability due to thermal expansion coefficient differences. In order to prevent the formation of a guide portion formed of the same material as the insulating film on the edge of the substrate.

이에 따라, 이종 물질 간의 접합 계면이 줄어들어 반도체 패키지의 접합 신뢰성을 향상시킬 수 있으며, 또한, 상대적으로 흡습률이 낮은 기판의 절연층과 동일한 물질로 가이드부의 흡습 관련 신뢰성을 향상시킬 수 있다. Accordingly, the bonding interface between the dissimilar materials may be reduced to improve the bonding reliability of the semiconductor package, and the moisture absorption-related reliability of the guide unit may be improved using the same material as the insulating layer of the substrate having a relatively low moisture absorption rate.

또한, 종래 봉지부를 대신하여 반도체 칩 및 금속와이어를 보호하기 위하여 캡핑부을 형성함으로써 금속와이어에 대한 종래 봉지부 형성에 따른 공정성 확보를 위하여 필요하였던 반도체 칩 상부 공간의 마진 확보가 필요 없어 얇은 두께를 갖는 반도체 패키지를 형성할 수 있다. In addition, by forming a capping part to protect the semiconductor chip and the metal wire in place of the conventional encapsulation part, it is not necessary to secure the margin of the upper space of the semiconductor chip, which is necessary to secure the fairness according to the conventional encapsulation part for the metal wire, and thus has a thin thickness. A semiconductor package can be formed.

아울러, 반도체 칩과 기판 간의 전기적인 연결을 범프를 통하여 형성하는 경우, 캡핑부 형성 공정으로 상기 반도체 칩을 보호함에 따라 반도체 칩과 기판 간에 범프의 전기적 연결 신뢰성을 향상시키기 위하여 사용되는 충진재의 형성 공정이 필요없어 제조 공정을 간소화할 수 있으며, 이에 따라, 종래 충진재와 봉지부와의 접합 계면 불량을 원천적으로 방지할 수 있다. In addition, when the electrical connection between the semiconductor chip and the substrate is formed through the bumps, a process of forming a filler used to improve the electrical connection reliability of the bumps between the semiconductor chip and the substrate as the semiconductor chip is protected by a capping part forming process. Since it is not necessary, the manufacturing process can be simplified, and therefore, the conventional bonding interface defect between the filler and the sealing portion can be prevented at the source.

이상, 여기에서는 본 발명을 특정 실시예에 관련하여 도시하고 설명하였지만, 본 발명이 그에 한정되는 것은 아니며, 이하의 특허청구의 범위는 본 발명의 정신과 분야를 이탈하지 않는 한도 내에서 본 발명이 다양하게 개조 및 변형될 수 있다는 것을 당업계에서 통상의 지식을 가진 자가 용이하게 알 수 있다.As mentioned above, although the present invention has been illustrated and described with reference to specific embodiments, the present invention is not limited thereto, and the following claims are not limited to the scope of the present invention without departing from the spirit and scope of the present invention. It can be easily understood by those skilled in the art that can be modified and modified.

도 1은 본 발명의 일 실시예에 따른 반도체 패키지를 도시한 도면.1 illustrates a semiconductor package according to an embodiment of the present invention.

도 2a 내지 도 2d는 본 발명의 일 실시예에 따른 반도체 패키지의 제조 방법을 설명하기 위한 공정별 도면.2A to 2D are process-specific diagrams for describing a method of manufacturing a semiconductor package according to an embodiment of the present invention.

도 3은 본 발명의 다른 실시예에 따른 반도체 패키지를 도시한 도면.3 illustrates a semiconductor package in accordance with another embodiment of the present invention.

Claims (6)

절연층을 포함하는 기판;A substrate including an insulating layer; 상기 기판 가장자리의 절연층 상에 형성된 가이드부;A guide part formed on the insulating layer at the edge of the substrate; 상기 기판 상면에 부착된 반도체 칩;A semiconductor chip attached to an upper surface of the substrate; 상기 반도체 칩과 기판 간을 연결하는 전기적 연결 부재; 및An electrical connection member connecting the semiconductor chip to the substrate; And 상기 기판의 상면에 상기 반도체 칩 및 전기적 연결 부재를 덮도록 상기 가이드부의 내측에 형성된 캡핑부;A capping part formed inside the guide part to cover the semiconductor chip and the electrical connection member on an upper surface of the substrate; 를 포함하는 것을 특징으로 하는 반도체 패키지.Semiconductor package comprising a. 제 1 항에 있어서,The method of claim 1, 상기 절연층 상면의 상기 가이드부 내측과 상기 절연층 하면에 각각 형성된 금속배선 및 솔더마스크를 더 포함하는 것을 특징으로 하는 반도체 패키지.And a metal wiring and a solder mask respectively formed on the inner side of the guide portion and the lower surface of the insulating layer on the upper surface of the insulating layer. 제 1 항에 있어서,The method of claim 1, 상기 가이드부는 상기 절연층과 동일한 물질로 이루어지거나 상기 절연층과 흡습률이 동일한 물질로 이루어진 것을 특징으로 하는 반도체 패키지. The guide part is made of the same material as the insulating layer or a semiconductor package, characterized in that made of a material having the same moisture absorption rate as the insulating layer. 제 1 항에 있어서,The method of claim 1, 상기 캡핑부는 에폭시로 이루어진 것을 특징으로 하는 반도체 패키지. The capping unit is a semiconductor package, characterized in that made of epoxy. 제 1 항에 있어서,The method of claim 1, 상기 가이드부의 최상단부는 상기 전기적 연결 부재의 최상단부보다 높은 높이를 갖는 것을 특징으로 하는 반도체 패키지. And the top end of the guide portion has a height higher than the top end of the electrical connection member. 제 1 항에 있어서,The method of claim 1, 상기 전기적 연결 부재는 금속와이어 또는 범프인 것을 특징으로 하는 반도체 패키지. The electrical connection member is a semiconductor package, characterized in that the metal wire or bump.
KR1020080062923A 2008-06-30 2008-06-30 Semiconductor package KR20100002874A (en)

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