KR20100002866A - Semiconductor package - Google Patents

Abstract

PURPOSE: A semiconductor package with a penetration electrode is provided to form an electrode without a void on a semiconductor chip while passing through the semiconductor chip. CONSTITUTION: A semiconductor chip has a circuit unit, bonding pads electrically connected to the circuit unit, and penetration holes(140). Penetration electrode units(210) are arranged on each penetration hole, includes conductive polarization particles electrically connected to each other, and are electrically connected to each bonding pad. An insulation unit(220) insulates each penetration electrode unit. The conductive connection unit covers one end of the penetration electrode unit.

Description

Semiconductor Package {SEMICONDUCTOR PACKAGE}

The present invention relates to a semiconductor package.

Recently, semiconductor packages including semiconductor chips and semiconductor chips capable of storing massive data and processing massive data in a short time have been developed.

Recently, in order to improve data storage capacity and improve data processing speed, a multilayer semiconductor package in which a plurality of semiconductor chips are stacked has been developed.

In order to manufacture a multilayer semiconductor package, a plurality of stacked semiconductor chips must be electrically connected.

In the stacked semiconductor package, the plurality of stacked semiconductor chips may be electrically connected using conductive wires. However, when the stacked semiconductor chips are electrically connected using conductive wires, the volume of the stacked semiconductor package is increased.

Recently, a multilayer semiconductor package having a reduced volume by manufacturing a multilayer semiconductor chip by stacking a plurality of semiconductor chips having a through electrode has been developed.

However, in the case of a laminated semiconductor package using a through electrode, a process of forming a through hole and a process of filling a metal in the through hole are required, and in particular, a void or the like is formed in the through hole during filling of the metal in the through hole. .

One object of the present invention is to provide a semiconductor package having a through electrode which suppresses the generation of voids.

The semiconductor package according to the present invention is a semiconductor chip having a circuit portion, bonding pads and through holes electrically connected to the circuit portion, and a second polarity disposed in each of the through holes and opposite to the first polarity and the first polarity, respectively. And conductive polarization particles electrically connected to each other, the through electrode parts electrically connected to the respective bonding pads, and an insulating part to insulate the through electrode parts.

Each of the conductive polarization particles of the semiconductor package includes a conductive rhelogical material.

The bonding pads of the semiconductor package are disposed at positions corresponding to the through holes.

The bonding pads of the semiconductor package are disposed at an edge of the top surface of the semiconductor chip.

The semiconductor package further includes a conductive connection member covering at least one end of the through electrode portion.

The conductive connecting member of the semiconductor package includes an anisotropic conductive film comprising a resin and conductive particles aligned in the resin.

The conductive connecting member of the semiconductor package includes a conductive film.

The conductive film of the semiconductor package includes solder.

The through holes and the bonding pads corresponding to the through holes of the semiconductor package are spaced apart from each other by a predetermined interval.

The semiconductor package further includes wiring portions electrically connecting the through electrode portions and the bonding pads corresponding to the through electrode portions.

At least two semiconductor chips of the semiconductor package are stacked.

Hereinafter, a semiconductor package according to embodiments of the present invention will be described in detail with reference to the accompanying drawings, but the present invention is not limited to the following embodiments, and those skilled in the art will appreciate The semiconductor package according to the present invention may be implemented in various other forms without departing from the spirit of the invention.

A semiconductor package according to the present invention includes a semiconductor chip having a circuit portion, bonding pads and through holes electrically connected to the circuit portion, and a second polarity disposed in each of the through holes and opposite to the first polarity, respectively. And through-electrodes having conductive polarization particles electrically connected to each other, the through-electrodes having electrically connected to the respective bonding pads, and an insulating part surrounding each through-electrode.

Hereinafter, semiconductor packages according to various embodiments of the present disclosure will be described.

1 is a cross-sectional view illustrating a semiconductor package according to an embodiment of the present invention.

Referring to FIG. 1, the semiconductor package 300 includes a semiconductor chip 100, a through electrode part 210, and an insulating part 220.

The semiconductor chip 100 includes a semiconductor chip body 110, a circuit unit 120, bonding pads 130, and through holes 140.

The semiconductor chip body 110 may have, for example, a rectangular parallelepiped shape, and the semiconductor chip body 110 having a rectangular parallelepiped shape may include a first surface 111 and a second surface facing the first surface 111. 112). In the present exemplary embodiment, the passivation layer 114 exposing the bonding pad 130 and the through hole 140 is disposed on the first surface 111 of the semiconductor chip body 110.

The circuit unit 120 is disposed in the semiconductor chip body 110, and the circuit unit 120 may include, for example, a data storage unit (not shown) for storing data and / or a data processing unit (not shown) for processing data. Include.

The bonding pads 130 are disposed on the first surface 111 of the semiconductor chip body 110, and the plurality of bonding pads 130 are disposed along an edge of the first surface 111. In this embodiment, each of the bonding pads 130 is electrically connected to the circuit unit 120. Signals applied from the outside by the bonding pads 130 are input to the circuit unit 120 or signals generated from the circuit unit 120 by the bonding pads 130 are output to the external device. In this embodiment, each bonding pad 130 includes an opening 132.

The through holes 140 penetrate the first surface 111 and the second surface 112 of the semiconductor chip body 110. In the present embodiment, each through hole 140 is disposed at a position corresponding to the opening 132 of each bonding pad 130.

The through electrode part 210 includes a plurality of conductive polarization particles 212 electrically connected to each other. Each conductive polarized particle 212 comprises a conductive rhelogical material having a first polarity and a second polarity. In this embodiment, the first polarity has, for example, (+) polarity and the second polarity has, for example, (-) polarity. Each of the plurality of conductive polarization particles 212 may be electrically connected with different polarities.

The insulating part 220 insulates the through electrode part 210 formed of the plurality of conductive polarization particles 212 from the inner surface of the semiconductor chip body 110 formed by the through hole 140. The insulation unit 220 not only insulates the through electrode unit 210, but also prevents the electrically connected conductive polarization particles 212 from being disconnected by external force and / or vibration applied from the outside.

The through electrode part 210 including the conductive polarization particles 212 is electrically connected to the bonding pad 130.

In the present exemplary embodiment, the through electrode part 210 and the insulating part 220 are disposed in, for example, the through hole 140.

2 is a cross-sectional view illustrating a semiconductor package according to another embodiment of the present invention. The semiconductor package shown in FIG. 2 includes substantially the same components as the semiconductor package shown and described above in FIG. 1 except for the conductive connection member. Therefore, duplicate descriptions of the same components will be omitted, and the same components and the same reference numerals will be given to the same components.

Referring to FIG. 2, the semiconductor package 300 may include a semiconductor chip 100 including a semiconductor chip body 110, a circuit unit 120, a bonding pad 130, and through holes 140 and a through electrode portion 210. , The insulating part 220 and the conductive connection members 240.

The conductive connection members 230 and 240 are disposed at at least one of the first end 201 and the second end 202 of the through electrode part 210 disposed in the through hole 140. In the present exemplary embodiment, the first end 201 of the through electrode part 210 is disposed on the first surface 111 of the semiconductor chip body 110, and the second end 202 of the through electrode part 210 is formed. The second surface 112 of the semiconductor chip body 110 is disposed.

In the present embodiment, the conductive connection members 230 and 240 are disposed on the first end 201 and the second end 202 of the through electrode part 210, respectively, and the through electrode part 210 is formed to each conductive connection member ( 230 and 240 are electrically connected to each other.

The conductive connection members 230 and 240 may be, for example, an anisotropic conductive film (ACF) having a plate shape and including resin and conductive particles aligned in the resin. Alternatively, the conductive connection members 230 and 240 may be metal films having a plate shape. In this embodiment, the metal film may include a solder that is a low melting point metal. The conductive connection members 230 and 240 may be particularly useful when manufacturing a laminated semiconductor package in which at least two semiconductor packages are stacked.

3 is a cross-sectional view illustrating a semiconductor package according to still another embodiment of the present invention. The semiconductor package illustrated in FIG. 3 includes substantially the same components as the semiconductor package illustrated and described with reference to FIG. 1 except for the locations and the wiring portions of the bonding pads. Therefore, duplicate descriptions of the same components will be omitted, and the same components and the same reference numerals will be given to the same components.

The semiconductor package 300 includes the semiconductor chip body 110, the circuit unit 120, the bonding pads 134, and the semiconductor chip 100 including the through holes 140, the through electrode unit 210, and the insulation unit 220. ) And the wiring units 400.

In the present exemplary embodiment, the bonding pads 134 may be disposed in one row or two rows at a central portion of the first surface 111 of the semiconductor chip body 110. In the present embodiment, the bonding pads 134 are disposed on, for example, one row on the first surface 111 of the semiconductor chip body 110.

When the bonding pads 134 are disposed at the center portion of the first surface 111, the bonding pads 134 may include the through electrode portion 210 and the insulation portion 220 disposed at the edge of the first semiconductor chip body 110. ) Is spaced apart from the predetermined interval.

The wiring unit 400 is disposed on the first surface 111 of the semiconductor chip body 110. The wiring unit 400 electrically connects each of the bonding pads 124 and each of the through electrodes 210 corresponding to the bonding pads 124. In the present embodiment, the wiring unit 400 may include copper having excellent electrical characteristics, and the wiring unit 400 has a line shape when viewed in plan view.

4 is a cross-sectional view illustrating a semiconductor package according to still another embodiment of the present invention. The semiconductor package illustrated in FIG. 4 includes substantially the same components as the semiconductor package illustrated and described above with reference to FIG. 1 except for the positions of the bonding pads and the through electrode portion. Therefore, duplicate descriptions of the same components will be omitted, and the same components and the same reference numerals will be given to the same components.

Referring to FIG. 4, the semiconductor package 300 may include a semiconductor chip 100 including a semiconductor chip body 110, a circuit unit 120, bonding pads 134, and through holes 140, and a through electrode unit 210. ), And an insulation unit 220.

The bonding pads 134 are disposed at the center portion of the first surface 111 of the semiconductor chip body 110. Each bonding pad 134 is electrically connected to the circuit unit 120.

The through electrode part 210 includes a through part 214 and an extension part 216. The through part 214 is disposed in the through hole 140, and the extension part 216 extends from the through part 214 along the first surface 111 of the semiconductor chip 100 so that the respective bonding pads 134 may be formed. Is electrically connected to the

The through part 214 and the extension part 216 of the through electrode part 210 are integrally formed, and the through part 214 and the extension part 216 have conductive polarization particles having a first polarity and a second polarity, respectively. 212, and adjacent conductive polarization particles 212 are electrically connected in contact with each other with different polarities.

5 is a cross-sectional view illustrating a semiconductor package according to still another embodiment of the present invention.

Referring to FIG. 5, the semiconductor package 800 includes a first semiconductor chip 500, a second semiconductor chip 600, and a substrate 700.

In the present exemplary embodiment, the first semiconductor chip 500 is disposed on the substrate 700, and the second semiconductor chip 600 is disposed on the first semiconductor chip 500.

The first semiconductor chip 500 may include a first semiconductor chip body 515, a first circuit part 517, first bonding pads 530, first through holes 540, and a first through electrode part 510. And a first insulation unit 520.

The first semiconductor chip body 515 may have, for example, a rectangular parallelepiped shape, and the first semiconductor chip body 515 having a rectangular parallelepiped shape faces the first surface 511 and the first surface 511. A second face 512. In the present exemplary embodiment, the passivation layer 514 exposing the first bonding pads 130 and the first through hole 140 are disposed on the first surface 111 of the first semiconductor chip body 515.

The first circuit unit 517 is disposed in the first semiconductor chip body 515, and the first circuit unit 517 may be, for example, a data storage unit (not shown) for storing data and / or data for processing data. It includes a processing unit (not shown).

The first bonding pads 530 are disposed on the first surface 511 of the first semiconductor chip body 515, and the plurality of first bonding pads 530 are disposed along an edge of the first surface 511. . In this embodiment, each of the first bonding pads 530 is electrically connected to the first circuit portion 517. Signals externally applied by the first bonding pads 530 are input to the first circuit portion 517 or signals generated from the first circuit portion 517 by the first bonding pads 530 are output to the external device. do. In this embodiment, each of the first bonding pads 530 includes a first opening 532.

The first through holes 540 pass through the first surface 511 and the second surface 512 of the first semiconductor chip body 515. In this embodiment, each of the first through holes 540 is disposed at a position corresponding to the first opening 532 of each of the first bonding pads 530.

The first through electrode part 510 includes conductive polarization particles 512 that are electrically connected to each other. Each conductive polarized particle 512 comprises a conductive realizable material having a first polarity and a second polarity. In this embodiment, the first polarity has, for example, (+) polarity and the second polarity has, for example, (-) polarity. Each of the plurality of conductive polarization particles 512 is electrically connected with different polarities.

The first insulating part 520 is formed from the inner surface of the first semiconductor chip body 515 formed by the first through hole 540 by forming the first through electrode part 510 including the plurality of conductive polarization particles 512. Insulate. The first insulating part 520 not only insulates the first through electrode part 510 but also prevents the electrically connected conductive polarization particles 212 from being disconnected by external force and / or vibration applied from the outside.

The first through electrode part 510 including the conductive polarization particles 212 is electrically connected to the first bonding pad 530.

In the present exemplary embodiment, the first through electrode part 510 and the first insulating part 520 are disposed in, for example, the first through hole 540.

The second semiconductor chip 600 disposed on the first semiconductor chip 500 may include a second semiconductor chip body 615, a second circuit part 617, second bonding pads 630, and a second through hole 640. ), A second through electrode part 610, and a second insulating part 620.

The second semiconductor chip body 615 may have, for example, a rectangular parallelepiped shape, and the second semiconductor chip body 615 having a rectangular parallelepiped shape faces the third side 611 and the third side 611. And a fourth side 612. In this embodiment, the first surface 511 of the first semiconductor chip body 515 is opposite to the third surface 611 of the second semiconductor chip body 615. In the present exemplary embodiment, a passivation layer 614 exposing the second bonding pads 630 and the second through hole 640 is disposed on the third surface 611 of the second semiconductor chip body 615.

The second circuit unit 617 is disposed in the second semiconductor chip body 615, and the second circuit unit 617 may be, for example, a data storage unit (not shown) for storing data and / or data for processing data. It includes a processing unit (not shown).

The second bonding pads 630 are disposed on the third surface 611 of the second semiconductor chip body 615, and the plurality of second bonding pads 630 are disposed along the edge of the third surface 611. . In the present embodiment, each of the second bonding pads 630 is electrically connected to the second circuit portion 617. Signals externally applied by the second bonding pads 630 are input to the second circuit portion 617 or signals generated from the second circuit portion 617 by the second bonding pads 630 are output to the external device. do. In this embodiment, each second bonding pad 630 includes a second opening 632.

The second through holes 640 pass through the third surface 611 and the fourth surface 612 of the second semiconductor chip body 615. In the present embodiment, each of the second through holes 640 is disposed at a position corresponding to the second opening 632 of each second bonding pad 630.

The second through electrode part 610 includes conductive polarization particles 612 that are electrically connected to each other. Each conductive polarization particle 612 includes a conductive reale material having a first polarity and a second polarity. In this embodiment, the first polarity has, for example, (+) polarity and the second polarity has, for example, (-) polarity. Each of the plurality of conductive polarization particles 612 may be electrically connected with different polarities.

The second insulating part 620 is formed from the inner surface of the second semiconductor chip body 615 formed by the second through hole 640 by forming the second through electrode part 610 including the plurality of conductive polarization particles 612. Insulate. The second insulating part 620 not only insulates the second through electrode part 610 but also prevents the electrically connected conductive polarization particles 612 from being disconnected by external force and / or vibration applied from the outside.

The second through electrode part 610 including the conductive polarization particles 612 is electrically connected to the second bonding pad 630.

In the present exemplary embodiment, the second through electrode part 610 and the second insulating part 620 are disposed in, for example, the second through hole 640.

Meanwhile, conductive connection members 550 and 650 may be disposed at ends of the first through electrode part 510 of the first semiconductor chip 500 and the second through electrode part 610 of the second semiconductor chip 600, respectively. The first and second semiconductor chips 500 and 600 are electrically connected to each other by the conductive connection members 550 and 560.

The substrate 700 includes a substrate body 710, a connection pad 720, a ball land pattern 730, and a conductive ball 740.

The substrate body 710 may be, for example, a printed circuit board having a plate shape.

The connection pad 720 is disposed on an upper surface of the substrate body 710 facing the second surface 512 of the first semiconductor chip 500. The connection pad 720 is electrically connected to the through electrode part 510 of the first semiconductor chip 500. The through electrode part 510 of the first semiconductor chip 500 is electrically connected to the connection pad 720 by the conductive connection member 550.

The ball land pattern 730 is disposed on a bottom surface facing the top surface of the substrate body 710, and the ball land pattern 730 is electrically connected to the connection pad 720 through conductive vias or the like.

The conductive balls 740 are disposed on the ball land patterns 730, and the conductive balls 740 may include solder having a low melting temperature.

According to the above description, it has the effect that a voidless electrode which penetrates a semiconductor chip can be formed in a semiconductor chip.

In the detailed description of the present invention described above with reference to the embodiments of the present invention, those skilled in the art or those skilled in the art having ordinary knowledge in the scope of the present invention described in the claims and It will be appreciated that various modifications and variations can be made in the present invention without departing from the scope of the art.

1 is a cross-sectional view illustrating a semiconductor package according to an embodiment of the present invention.

2 is a cross-sectional view illustrating a semiconductor package according to another embodiment of the present invention.

3 is a cross-sectional view illustrating a semiconductor package according to still another embodiment of the present invention.

4 is a cross-sectional view illustrating a semiconductor package according to still another embodiment of the present invention.

5 is a cross-sectional view illustrating a semiconductor package according to still another embodiment of the present invention.

Claims (11)

A semiconductor chip having a circuit portion and bonding pads and through holes electrically connected to the circuit portion; And Through-electrode portions disposed in the through-holes, each of the conductive polarization particles having a first polarity and a second polarity opposite to the first polarity, and electrically connected to each other, and electrically connected to the respective bonding pads; And A semiconductor package including an insulating portion for insulating each through electrode portion. The method of claim 1, And wherein each of the conductive polarized particles comprises a conductive rhelogical material. The method of claim 1, And the bonding pads are disposed at positions corresponding to the through holes. The method of claim 3, The bonding pads are disposed on the edge of the upper surface of the semiconductor chip. The method of claim 3, And a conductive connection member covering at least one end of the through electrode portion. The method of claim 5, And the conductive connecting member comprises an anisotropic conductive film comprising a resin and conductive particles aligned in the resin. The method of claim 5, The conductive connecting member includes a conductive film. The method of claim 7, wherein The conductive film comprises a solder, characterized in that the semiconductor package. The method of claim 1, And the bonding pads corresponding to the through holes and the through holes are spaced apart from each other by a predetermined interval. The method of claim 9, And wiring lines electrically connecting the through electrode portions and the bonding pads corresponding to the through electrode portions. The method of claim 1, At least two semiconductor chips are stacked.

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