KR20100001819A - Method for forming semiconductor devices - Google Patents

Method for forming semiconductor devices Download PDF

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Publication number
KR20100001819A
KR20100001819A KR1020080061890A KR20080061890A KR20100001819A KR 20100001819 A KR20100001819 A KR 20100001819A KR 1020080061890 A KR1020080061890 A KR 1020080061890A KR 20080061890 A KR20080061890 A KR 20080061890A KR 20100001819 A KR20100001819 A KR 20100001819A
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KR
South Korea
Prior art keywords
pattern
film
reflection film
forming
photoresist
Prior art date
Application number
KR1020080061890A
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Korean (ko)
Inventor
허중군
Original Assignee
주식회사 하이닉스반도체
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Priority to KR1020080061890A priority Critical patent/KR20100001819A/en
Publication of KR20100001819A publication Critical patent/KR20100001819A/en

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    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/26—Processing photosensitive materials; Apparatus therefor
    • G03F7/40—Treatment after imagewise removal, e.g. baking
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H01L21/0276—Photolithographic processes using an anti-reflective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0338—Process specially adapted to improve the resolution of the mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Photosensitive Polymer And Photoresist Processing (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)

Abstract

In the method of forming a semiconductor device of the present invention, a step of sequentially forming an etched layer, a lower layer, and an anti-reflection film on the upper surface of the semiconductor substrate, and applying a photoresist film to the upper portion of the anti-reflection film, and then performing a photolithography process on the photoresist film to form a photoresist pattern. Forming an anti-reflection film by etching the anti-reflection film by using the photoresist pattern as an etch mask and relaxing the upper surface of the entire surface including the anti-reflection film pattern and the photoresist pattern remaining on the anti-reflection film pattern. Forming a spacer pattern by coating a material, depositing an insulating film on an entire surface including the antireflection film pattern and the release material, etching the insulating film to expose the release material, and forming the spacer pattern The relaxation material, the photoresist pattern and the reflection so as to remain only Characterized by including the step of removing the last pattern.

Description

Method for forming semiconductor devices

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a semiconductor device, and more particularly, to a method of forming a semiconductor device using a spacer patterning technology (SPT).

Recently, with the rapid spread of information media such as personal portable devices equipped with memory devices and personal computers, a high-density semiconductor device having a large storage capacity and improved reliability and operation speed for accessing data has been developed. Development of process equipment and process technology is urgently required.

Since the speed of the semiconductor device increases as the critical dimension of the pattern line width, that is, the size of the pattern line width, various photolithography techniques for improving the integration degree of the semiconductor device have been proposed.

Among these, photolithography is the most easily used technology for photolithography to realize fine patterns. Photolithography using ArF immersion exposure equipment is difficult to realize patterns of 40 nm or less in a single exposure process. Therefore, there is a limit in reflecting a design rule that decreases as the integration degree of a semiconductor device is improved.

In order to overcome these limitations, we used multiple hyper-NA exposure equipment with high index fluid (HIF) materials, but it is difficult to realize fine patterns below 30 nm.

Accordingly, there is a further demand for development of an exposure apparatus using a short wavelength source of 13.5 nm such as EUV (extreme ultra violet) instead of an ArF wavelength and a photoresist material suitable for the same.

In addition, in order to realize a fine pattern, a double patterning technology that can improve resolution by lowering the process constant K1 factor with a conventional exposure apparatus in a photolithography process has been developed.

Among the double patterning technologies, spacer patterning technology (hereinafter referred to as 'SPT') is a self-align technology that prevents misalignment because only one mask process is required to pattern the cell area. .

1A to 1E are schematic views illustrating a method of forming a semiconductor device using SPT according to the prior art.

Referring to FIG. 1A, the first hard mask layer 15, the second hard mask layer 17, and the third hard mask layer 19 may be sequentially disposed on the etched layer 13 formed on the semiconductor substrate 11. To form.

The photoresist pattern 21 is formed by performing an exposure process and a development process on the photoresist film (not shown) coated on the third hard mask layer.

Next, as shown in FIG. 1B, the third hard mask layer 19 is etched using the photoresist pattern 21 as an etch mask to form a third hard mask layer pattern (not shown).

The second hard mask layer pattern 23 is etched using the third hard mask layer pattern as an etch mask to form a second hard mask layer pattern 23.

Next, as shown in FIG. 1C, an insulating film 25 having excellent step coverage is formed on the entire upper surface including the second mask layer pattern 23.

Next, as illustrated in FIG. 1D, the insulating layer 25 is etched by performing an etch back process on the insulating layer 25 until the upper portion of the second mask layer pattern 23 is exposed, thereby etching the second mask layer pattern 23. Sidewall spacers 27 are formed on the sidewalls of the < RTI ID = 0.0 >

Next, as shown in FIG. 1E, the second hard mask layer pattern 23 having an exposed top portion is removed so that only the sidewall spacer pattern 27 remains.

At this time, the sidewall spacer pattern 27 has a horn shape, and the portion where the second hard mask layer pattern 23 is removed has a vertical profile, but the portion where the insulating layer 25 is etched by the etch back process is arched. Has a profile.

Therefore, when the first mask layer 15 is etched using the sidewall spacer pattern 27 as an etch mask, the pattern is formed in a non-uniform profile as shown in FIG. There is a problem in that it is impossible to reduce the yield of the device.

In the method of forming a semiconductor device of the present invention, the spacer pattern is asymmetrically formed during the SPT process to solve the problem that the line width is not uniformly formed during the subsequent lower layer etching.

The method of forming a semiconductor device of the present invention comprises the steps of sequentially forming an etched layer, a lower layer, an antireflection film on the semiconductor substrate;

 Forming a photoresist pattern by applying a photoresist film on top of the antireflection film and then performing a photolithography process on the photoresist film;

Etching the anti-reflection film by using the photoresist pattern as an etching mask to form an anti-reflection film pattern;

Applying a release material on the entire surface including the antireflection film pattern and the photoresist pattern remaining on the antireflection film pattern;

Depositing an insulating film on an entire surface including the anti-reflection film pattern and the relaxation material;

Etching the insulating layer to expose the relaxation material to form a spacer pattern; and

And removing the release material, the photoresist pattern, and the anti-reflection film pattern so that only the spacer pattern remains.

 In this case, the anti-reflection film pattern may be formed by etching the anti-reflection film so that the photoresist pattern remains on the anti-reflection film pattern.

In addition, the anti-reflection film is formed of a material having a larger etching selectivity than the photosensitive film.

In addition, the release material reacts with the photoresist pattern remaining on the anti-reflection film pattern and aggregates on the photoresist pattern.

In addition, the release material does not react with the anti-reflection film pattern and is not aggregated to the anti-reflection film pattern.

At this time, the thickness of the photoresist pattern remaining on the anti-reflection film pattern is characterized in that 30 ~ 300Å.

In addition, the thickness of the relaxed release material reacted with the photosensitive film pattern is characterized in that the 3nm to 30nm.

And, after the step of applying the release material is characterized in that it further comprises a baking process.

At this time, the temperature of the baking process is characterized in that 90 ℃ to 160 ℃.

In addition, the baking process is characterized in that the temperature is 130 ℃ to 150 ℃.

And, the process temperature of the step of depositing the insulating film is characterized in that the 15 ℃ to 150 ℃.

At this time, the insulating film is characterized in that the low-temperature oxide film, polysilicon or nitride film.

In addition, the spacer pattern may be formed by etching the insulating film so as to have a bilateral symmetrical arch shape.

In addition, the insulating film may be etched through an etch back process.

The lower layer may include a structure in which different material layers are stacked.

The plasma rework process may be performed to remove the release material, the photoresist pattern, and the anti-reflection film pattern.

The present invention has the advantage of improving the production yield of semiconductor devices by simplifying the SPT process and improving the line width uniformity by providing stable etching process conditions during the subsequent lower layer etching process during the SPT process.

Hereinafter, with reference to the accompanying drawings an embodiment of the present invention will be described in detail.

3A to 3G are schematic views illustrating a method of forming a semiconductor device using SPT according to the prior art.

As shown in FIG. 3A, the etched layer 102, the lower layer 104, and the anti-reflection layer 106 are sequentially formed on the semiconductor substrate 100.

In this case, the lower layer 104 may include a first insulating layer, a hard mask layer, a second insulating layer, a third insulating layer, and the like, and is not necessarily limited thereto.

3B, a photoresist (not shown) is coated on the antireflection film 106, and then a photolithography process is performed on the photoresist to form a photoresist pattern 108.

3C, the antireflection film 106 is etched using the photoresist pattern 108 as an etch mask to form the antireflection film pattern 110.

In this process, it is preferable that the photoresist pattern 112 remains on the antireflection film pattern 110 on a predetermined thickness. For this purpose, the antireflection film 106 preferably uses a material having a larger etching selectivity than the photoresist film.

At this time, the thickness of the remaining photoresist pattern 112 is preferably 30 kPa to 300 kPa, but does not necessarily have the thickness as described above and may vary depending on the degree of integration of the semiconductor device.

Then, as shown in FIG. 3D, a resist enhancement lithography assisted by chemical shrink (RELACS, 114) material on the entire surface including the antireflection film pattern 110 and the photoresist pattern 112 remaining thereon. Apply.

In this case, since the release material 114 reacts with the photoresist pattern 112 but does not react with the antireflection pattern 110, it is aggregated only on the photoresist pattern 112 and remains on the upper portion of the antireflection pattern 110. It will be larger than the thickness of 112.

In this case, the thickness of the release material 114 aggregated on the photoresist pattern 112 is preferably 3 nm to 30 nm, but may not necessarily have the thickness as described above, but may vary depending on the degree of integration of the semiconductor device.

It is preferable to perform a bake process after the application of the release material 114.

At this time, it is preferable to make baking temperature 90 degreeC-160 degreeC, and it is more preferable to set it as 130 degreeC-150 degreeC.

Next, as shown in FIG. 3E, an insulating film 116 is deposited on the entire surface including the anti-reflection film pattern 110 and the release material 114.

At this time, the temperature for depositing the insulating film 116 is preferably 15 ℃ to 150 ℃, the oxide film is most preferred as the insulating film 116, but other materials having excellent low-temperature process and step coverage characteristics, for example, polysilicon, nitride film Etc. are also possible.

Next, as shown in FIG. 3F, the insulating layer 116 is partially etched so that the relax material 114 is exposed so that the relax material 114 remains a predetermined thickness so that the relax material 114 is exposed. Although etching is preferably performed to have the form of 118, the etching degree of the insulating layer 116 may vary depending on the degree of integration of the semiconductor device.

The etching process used to etch the insulating film 116 is preferably an etch back.

In this case, the profile of the spacer pattern 118 may be modified by controlling the etching degree of the insulating layer 116 by controlling various process temperatures after applying the release material 114.

In addition, by using the reaction with the photosensitive film pattern 112, it can also be modified by using a relaxation material of another product group that can control the CD.

Next, as shown in FIG. 3G, the release material 114, the photoresist layer pattern 112, and the anti-reflection layer pattern 110 are removed so that only the spacer pattern 118 remains.

In this case, the release material 114, the photoresist film pattern 112, and the anti-reflection film pattern 110 may be removed through a plasma rework process.

In the process of removing the relax material 114 remaining on the spacer pattern 118, the spacer pattern 118 contacting the lower part of the relax material 114 is etched together, so that the spacer pattern 118 has an arch shape. You have a profile.

Thus, unlike the prior art, the spacer pattern 118 has an arch-shaped profile rather than a profile perpendicular to the portion in contact with the anti-reflection film pattern 110 by the release material 114, so that the spacer pattern 118 is formed by a subsequent process. In the case where the lower layer 104 is etched using the etching mask, the uniformity of the profile may be improved.

1A to 1E are schematic views showing a method of forming a semiconductor device using SPT according to the prior art.

2 is an electron micrograph of a lower pattern formed by the SPT method according to the prior art.

3A to 3G are schematic views showing a method of forming a semiconductor device using SPT according to the present invention.

Claims (16)

Sequentially forming an etched layer, a lower layer, and an anti-reflection film on the semiconductor substrate;  Forming a photoresist pattern by applying a photoresist on the antireflection film and then performing a photolithography process on the photoresist; Etching the anti-reflection film by using the photoresist pattern as an etching mask to form an anti-reflection film pattern; Applying a release material on the entire surface including the anti-reflection film pattern and the photoresist pattern remaining on the anti-reflection film pattern; Depositing an insulating film on an entire surface including the anti-reflection film pattern and the relax material; Etching the insulating layer to expose the release material to form a spacer pattern; And And removing the relax material, the photoresist pattern, and the anti-reflection film pattern so that only the spacer pattern remains. The method of claim 1, And the anti-reflection film pattern is formed by etching the anti-reflection film so that the photoresist pattern remains on the anti-reflection film pattern. The method of claim 1, And the anti-reflection film is formed of a material having an etching selectivity greater than that of the photosensitive film. The method of claim 1, And the release material reacts with the photoresist pattern remaining on the antireflection layer pattern to aggregate the photoresist pattern. The method of claim 1, And wherein the release material does not react with the antireflection film pattern and does not aggregate with the antireflection film pattern. The method of claim 1, The thickness of the photosensitive film pattern remaining on the anti-reflection film pattern is a method of forming a semiconductor device, characterized in that 30 ~ 300Å. The method of claim 4, wherein The thickness of the release material agglomerated by reacting with the photosensitive film pattern is a method of forming a semiconductor device, characterized in that 3nm to 30nm. The method of claim 1, The method of forming a semiconductor device, characterized in that it further comprises a baking step after the step of applying the release material. The method of claim 8, The temperature of the baking step is a method for forming a semiconductor device, characterized in that 90 ℃ to 160 ℃. The method of claim 8, The temperature of the baking process is a method for forming a semiconductor device, characterized in that 130 ℃ to 150 ℃. The method of claim 1, Process temperature of the step of depositing the insulating film is a method of forming a semiconductor device, characterized in that 15 ℃ to 150 ℃. The method of claim 1, And the insulating film is a low temperature oxide film, polysilicon or nitride film. The method of claim 1, The spacer pattern is a method of forming a semiconductor device, characterized in that the insulating film is formed to be etched to have a bilateral symmetrical arch. The method of claim 1, And the insulating layer is etched through an etch back process. The method of claim 1, The lower layer may have a structure in which different material layers are stacked. The method of claim 1, And removing the relax material, the photoresist pattern, and the anti-reflective pattern from the substrate, wherein a plasma rework process is performed.
KR1020080061890A 2008-06-27 2008-06-27 Method for forming semiconductor devices KR20100001819A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103311109A (en) * 2012-03-12 2013-09-18 上海华虹Nec电子有限公司 Method for forming side wall and method for defining graph structure by using side wall

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103311109A (en) * 2012-03-12 2013-09-18 上海华虹Nec电子有限公司 Method for forming side wall and method for defining graph structure by using side wall

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