KR20100000439A - Semiconductor package using thermoelectric element - Google Patents

Semiconductor package using thermoelectric element Download PDF

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KR20100000439A
KR20100000439A KR1020080059943A KR20080059943A KR20100000439A KR 20100000439 A KR20100000439 A KR 20100000439A KR 1020080059943 A KR1020080059943 A KR 1020080059943A KR 20080059943 A KR20080059943 A KR 20080059943A KR 20100000439 A KR20100000439 A KR 20100000439A
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type semiconductor
semiconductor
thermoelectric element
substrate
thermoelectric
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KR1020080059943A
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Korean (ko)
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김석봉
손은숙
차세웅
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앰코 테크놀로지 코리아 주식회사
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Priority to KR1020080059943A priority Critical patent/KR20100000439A/en
Publication of KR20100000439A publication Critical patent/KR20100000439A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N10/00—Thermoelectric devices comprising a junction of dissimilar materials, i.e. devices exhibiting Seebeck or Peltier effects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

PURPOSE: A semiconductor package using a thermoelectric element is provided to rapidly emit heat generated in each semiconductor chip to the outside by installing a thermoelectric element between semiconductor chips and supplying DC power. CONSTITUTION: A plurality of semiconductor chips(10) is laminated and are communicated with each other through a penetration silicon via(16). A substrate(46) mounts a plurality of semiconductor chips so that they are electrically connected with each other. A molding compound resin is molded on the substrate while protecting the semiconductor chips. A plurality of thermoelectric elements(20) are inserted into semiconductor chips. A power supply unit supplies DC power to thermoelectric elements.

Description

열전소자를 이용한 반도체 패키지{Semiconductor package using thermoelectric element}Semiconductor package using thermoelectric element

본 발명은 열전소자를 이용한 반도체 패키지에 관한 것으로서, 더욱 상세하게는 웨이퍼 레벨에서 관통 실리콘 비아가 형성된 반도체 칩을 적층하여 제조된 반도체 패키지에 있어서, 각 반도체 칩 사이에 열전소자를 개재하여 반도체 칩에서 발생되는 열을 효과적으로 방출시킬 수 있도록 한 열전소자를 이용한 반도체 패키지에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package using a thermoelectric element, and more particularly, to a semiconductor package manufactured by stacking semiconductor chips having through silicon vias formed at a wafer level, wherein the semiconductor chip is disposed between thermoelectric elements. The present invention relates to a semiconductor package using a thermoelectric device capable of effectively releasing generated heat.

반도체 집적회로의 패키징 기술중 3차원 적층 기술은 전자소자의 크기를 줄이는 동시에 실장 밀도를 높이면서 그 성능을 향상시킬 수 있는 목표를 두고 개발되어 왔으며, 이러한 3차원 적층 패키지는 동일한 기억 용량의 칩을 복수개 적층한 패키지로서, 이를 통상 적층 칩 패키지(Stack Chip Package)라 한다.Three-dimensional lamination technology of packaging technology of semiconductor integrated circuits has been developed with the goal of improving the performance while reducing the size of electronic devices and increasing the mounting density. A plurality of stacked packages, which are commonly referred to as stack chip packages.

적층 칩 패키지의 기술은 단순화된 공정으로 패키지의 제조 단가를 낮출 수 있으며, 또한 대량 생산 등의 잇점이 있는 반면, 적층되는 칩의 수 및 크기 증가에 따른 패키지 내부의 전기적 연결을 위한 배선 공간이 부족하다는 단점이 있다.The technology of the multilayer chip package can reduce the manufacturing cost of the package by a simplified process, and also has advantages such as mass production, while lacking wiring space for the electrical connection inside the package due to the increase in the number and size of the stacked chips. The disadvantage is that.

즉, 기존의 적층 칩 패키지는, 기판의 칩부착영역에 복수개의 칩이 부착된 상태에서, 각 칩의 본딩패드와 기판의 전도성회로패턴간이 와이어로 통전 가능하게 연결된 구조로 제조됨에 따라, 와이어 본딩을 위한 공간이 필요하고, 또한 와이어가 연결되는 기판의 회로패턴 면적이 필요하여, 결국 반도체 패키지의 크기가 증가되는 단점이 있다.That is, the conventional laminated chip package is manufactured in a structure in which a plurality of chips are attached to the chip attaching region of the substrate, so that the bonding pads of the chips and the conductive circuit patterns of the substrate are electrically connected to each other by wire, so that the wire bonding is possible. Space is needed for the circuit pattern area of the substrate to which the wire is connected, and thus the size of the semiconductor package is increased.

이러한 점을 감안하여, 적층 칩 패키지의 한 예로 관통 실리콘 비아(TSV: Through silicon via)를 이용한 패키지가 제안되었는 바, 웨이퍼 상태에서 각 반도체 칩 내에 관통 실리콘 비아를 형성하고, 이 관통 실리콘 비아에 의해 수직으로 칩들간 물리적 및 전기적 연결이 이루어지도록 한 점에 특징이 있다.In view of this, a package using through silicon vias (TSV) has been proposed as an example of a stacked chip package, and through silicon vias are formed in each semiconductor chip in a wafer state. It is characterized by the physical and electrical connection between the chips vertically.

이렇게, 종래의 관통 실리콘 비아를 이용한 반도체 칩 적층형 패키지는 여러개의 반도체 칩이 관통 실리콘 비아를 통해 서로 적층된 후, 몰딩 컴파운드 수지로 감싸여진 구조로 제작된다.As described above, the semiconductor chip stack package using the conventional through silicon via is fabricated in a structure in which a plurality of semiconductor chips are stacked on each other through the through silicon via and then wrapped with a molding compound resin.

그러나, 종래의 관통 실리콘 비아를 이용한 반도체 칩 적층형 패키지는 여러개의 반도체 칩이 적층된 상태에서 구동함에 따라, 각 반도체 칩에서 상당히 많은 열이 발생하는 단점이 있다.However, the conventional semiconductor chip stack package using the through-silicon vias has a disadvantage in that a considerable amount of heat is generated in each semiconductor chip as the semiconductor chip stacked package is driven in a stacked state.

특히, 각 반도체 칩에서 발생되는 열의 방출 경로가 별도로 구성되어 있지 않기 때문에, 해당 반도체 패키지의 고장 내지 수명 저하를 가중시키는 원인이 되고 있다. In particular, since the path for dissipating heat generated in each semiconductor chip is not configured separately, it is a cause of increasing the failure or the life degradation of the semiconductor package.

이에, 관통 실리콘 비아를 이용한 적층 칩 패키지에 열방출수단을 포함시켜, 반도체 칩에서 발생되는 열을 효과적으로 방출시킬 수 있는 새로운 방안이 요구되고 있다.Accordingly, a new method for effectively dissipating heat generated from a semiconductor chip is required by including heat dissipation means in a laminated chip package using through silicon vias.

본 발명은 상기와 같은 점을 감안하여 안출한 것으로서, 관통 실리콘 비아 를 이용하여 웨이퍼 상태의 반도체 칩을 상하로 적층 구성하고, 적층된 칩을 기판상에 탑재하여 이루어진 적층 칩 패키지에 열전소자를 내재시켜 각 반도체 칩에서 발생되는 열을 외부로 신속하게 방출하여 열방출 효과를 크게 얻을 수 있도록 한 반도체 패키지를 제공하는데 그 목적이 있다.The present invention has been made in view of the above, and a thermoelectric device is embedded in a laminated chip package formed by stacking semiconductor chips in a wafer state up and down using through silicon vias and mounting the stacked chips on a substrate. The purpose of the present invention is to provide a semiconductor package capable of rapidly dissipating heat generated from each semiconductor chip to the outside to obtain a large heat dissipation effect.

상기한 목적을 달성하기 위한 본 발명은 관통 실리콘 비아를 통해 전기적 신호 교환 가능하게 적층된 복수개의 반도체 칩과; 상기 복수개의 반도체 칩이 전기적 신호 교환 가능하게 탑재되는 기판과; 상기 기판상에 반도체 칩들을 감싸면서 몰딩된 몰딩 컴파운 수지와; 상기 각 반도체 칩 사이에 내재되는 복수개의 열전소자와; 상기 열전소자들에 직류전원를 공급하는 전원공급수단; 을 포함하여 구성된 것을 특징으로 하는 열전소자를 이용한 반도체 패키지를 제공한다.The present invention for achieving the above object is a plurality of semiconductor chips stacked so as to exchange electrical signals through the through silicon via; A substrate on which the plurality of semiconductor chips are mounted to exchange electrical signals; A molding compound resin molded while wrapping the semiconductor chips on the substrate; A plurality of thermoelectric elements embedded between the semiconductor chips; Power supply means for supplying DC power to the thermoelectric elements; It provides a semiconductor package using a thermoelectric element, characterized in that configured to include.

바람직한 구현예로서, 상기 열전소자는: 순차적으로 교번 배열된 다수의 N형 반도체소자 및 P형 반도체소자와; 서로 인접한 N형 반도체소자와 P형 반도체소 자의 상면이 제1금속패턴으로 연결된 발열부와; 서로 인접한 P형 반도체소자와 N형 반도체소자의 저면이 제2금속패턴으로 연결된 냉각부와; 상기 N형 반도체소자와 P형 반도체소자의 사이 공간 또는 상기 P형 반도체소자와 N형 반도체소자의 사이 공간에 채워지는 절연체와; 상기 제1 및 제2금속패턴과, 절연체의 상하면에 부착되는 절연필름; 으로 구성된 것을 특징으로 한다.In a preferred embodiment, the thermoelectric device includes: a plurality of N-type semiconductor devices and P-type semiconductor devices sequentially arranged; A heat generating unit having upper surfaces of adjacent N-type semiconductor devices and P-type semiconductor devices connected to each other by a first metal pattern; A cooling unit in which bottom surfaces of adjacent P-type semiconductor elements and N-type semiconductor elements are connected to each other by a second metal pattern; An insulator filled in a space between the N-type semiconductor element and the P-type semiconductor element or a space between the P-type semiconductor element and the N-type semiconductor element; Insulating films attached to upper and lower surfaces of the first and second metal patterns and an insulator; Characterized in that consisting of.

바람직한 구현예로서, 상기 전원공급수단은: 각 반도체 칩의 소정 위치에 관통 형성된 한 쌍의 전극삽입홀과; 한 쌍의 전극삽입홀중 하나에 삽입되어 각 열전소자의 일측단부에 연결되는 동시에 그 하단끝은 기판에 전기적으로 연결되는 (+)전극봉과; 한 쌍의 전극삽입홀중 다른 하나에 삽입되어 각 열전소자의 타측단부에 연결되는 동시에 그 하단끝은 기판에 전기적으로 연결되는 (-)전극봉; 으로 구성된 것을 특징으로 한다.In a preferred embodiment, the power supply means includes: a pair of electrode insertion holes formed through a predetermined position of each semiconductor chip; (+) Electrode rods inserted into one of the pair of electrode insertion holes and connected to one end of each thermoelectric element, and the lower end thereof is electrically connected to the substrate; A negative electrode rod which is inserted into the other one of the pair of electrode insertion holes and connected to the other end of each thermoelectric element, and the lower end thereof is electrically connected to the substrate; Characterized in that consisting of.

상기한 과제 해결 수단을 통하여, 본 발명은 다음과 같은 효과를 제공할 수 있다.Through the above problem solving means, the present invention can provide the following effects.

본 발명에 따르면, 관통 실리콘 비아를 이용하여 웨이퍼 상태의 반도체 칩을 상하로 적층 구성하고, 적층된 칩을 기판상에 탑재하여 이루어진 적층 칩 패키지에 있어서, 적층된 각 반도체 칩의 사이에 열전소자를 내재시켜 직류전원을 공급함으로써, 열전소자의 냉각 및 발열 작용에 의하여 각 반도체 칩에서 발생되는 열을 냉각시킬 수 있고, 동시에 열전소자와 기판간에 연결된 전기적 경로를 따라 반도체 칩에서 발생된 열이 전달되어 외부로 방출되어지므로, 적층 칩 패키지의 열방출 효과를 극대화시킬 수 있다.According to the present invention, in a stacked chip package in which a semiconductor chip in a wafer state is stacked up and down using through silicon vias, and the stacked chips are mounted on a substrate, a thermoelectric element is interposed between the stacked semiconductor chips. By internally supplying DC power, it is possible to cool the heat generated from each semiconductor chip by the cooling and heating action of the thermoelectric element, and at the same time, the heat generated from the semiconductor chip is transferred along the electrical path connected between the thermoelectric element and the substrate. Since it is emitted to the outside, it is possible to maximize the heat dissipation effect of the laminated chip package.

이하, 본 발명의 바람직한 실시예를 첨부도면을 참조로 상세하게 설명하기로 한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

먼저, 본 발명의 이해를 돕기 위하여 관통 실리콘 비아 및 이를 이용한 칩 적층 방법을 설명하면 다음과 같다.First, the through silicon via and the chip stacking method using the same will be described in order to help the understanding of the present invention.

첨부한 도 3은 종래의 관통 실리콘 비아 형성 방법 및 칩 적층 방법을 설명하는 단면도이다.FIG. 3 is a cross-sectional view illustrating a conventional through silicon via forming method and a chip stacking method.

먼저, 웨이퍼 레벨에서 각 칩(10)의 본딩패드(23) 인접부분에 수직홀(12)을 형성하고, 이 수직홀(12)의 표면에 절연막(미도시됨)을 형성한다.First, a vertical hole 12 is formed in a portion adjacent to the bonding pad 23 of each chip 10 at the wafer level, and an insulating film (not shown) is formed on the surface of the vertical hole 12.

상기 절연막 상에 씨드 금속막을 형성한 상태로, 상기 수직홀(12) 내에 전해도금 공정을 통해 전해 물질, 즉 전도성 금속(14)을 매립해서 관통 실리콘 비아(16)를 형성한다.In the state in which the seed metal film is formed on the insulating layer, the through silicon via 16 is formed by filling an electrolytic material, that is, the conductive metal 14, through the electroplating process in the vertical hole 12.

다음으로, 웨이퍼의 후면을 백그라인딩(back grinding)하여 상기 관통 실리콘 비아(16)에 매립된 전도성 금속(14)을 노출시킨다.Next, the backside of the wafer is back ground to expose the conductive metal 14 embedded in the through silicon via 16.

이어서, 웨이퍼를 쏘잉하여 개별 칩들로 분리시킨 후, 기판 상에 적어도 둘 이상의 칩을 관통 실리콘 비아(16)의 전도성 금속(14)를 통해 신호 교환 가능하게 수직으로 쌓아올려 적층시킨다.Subsequently, the wafer is sawed and separated into individual chips, and then at least two or more chips are stacked on the substrate vertically so that they can be signal exchanged vertically through the conductive metal 14 of the through silicon vias 16.

보다 상세하게는, 서로 적층된 상부칩(10a)과 하부칩(10b)간의 전기적 연결 구조를 보면, 상부칩(10a)의 관통 실리콘 비아(16)를 통해 저부로 노출된 전도성 금속(14)과, 하부칩(10b)의 관통 실리콘 비아(16)를 통해 상부로 노출된 전도성 금속(14)간이 전도성 범프(18)에 의하여 서로 전기적으로 연결된다.More specifically, in the electrical connection structure between the upper chip 10a and the lower chip 10b stacked on each other, the conductive metal 14 exposed to the bottom through the through silicon via 16 of the upper chip 10a and The conductive metals 14 exposed upward through the through silicon vias 16 of the lower chip 10b are electrically connected to each other by the conductive bumps 18.

이후, 스택된 상부 및 하부칩들을 기판에 실장하여, 기판과 상부칩간의 와이어 본딩을 실시한 후, 몰딩 컴파운드 수지로 몰딩하고, 기판 하면에 솔더볼을 마운팅하여 스택 패키지를 완성하게 된다.Subsequently, the stacked upper and lower chips are mounted on a substrate, wire bonding between the substrate and the upper chip is performed, molded with a molding compound resin, and solder balls are mounted on the lower surface of the substrate to complete the stack package.

이러한 관통 실리콘 비아(TSV: Through silicon via)를 이용한 적층 칩 패키지는 여러개의 반도체 칩이 적층된 상태이므로, 그 구동시 상당히 많은 열이 발생된다.Since the stacked chip package using the through silicon via (TSV) is a state in which a plurality of semiconductor chips are stacked, a considerable amount of heat is generated during its driving.

여기서, 관통 실리콘 비아를 이용한 적층 칩 패키지의 반도체 칩에서 발생되는 열을 냉각 및 방출시킬 수 있도록 한 본 발명의 반도체 패키지에 대하여 살펴보면 다음과 같다.Herein, the semiconductor package according to the present invention may cool and release heat generated from the semiconductor chip of the multilayer chip package using through silicon vias.

첨부한 도 1은 본 발명에 따른 열전소자를 이용한 반도체 패키지를 나타내는 단면도이고, 도 2는 본 발명에 따른 반도체 패키지에 적용된 열전소자의 구조를 설명하는 단면도이다.1 is a cross-sectional view illustrating a semiconductor package using a thermoelectric device according to the present invention, and FIG. 2 is a cross-sectional view illustrating a structure of a thermoelectric device applied to a semiconductor package according to the present invention.

열전소자란, 전기저항의 온도 변화를 이용한 소자인 서미스터, 온도 차에 의해 기전력이 발생하는 현상인 제벡 효과를 이용한 소자, 전류에 의해 열의 흡수(또는 발생)가 생기는 현상인 펠티에 효과를 이용한 소자인 펠티에소자 등이 있지만, 본 발명에서는 펠티에 소자를 의미하는 것으로 전제한다.A thermoelectric element is a thermistor which is a device using a temperature change of an electrical resistance, a device using the Seebeck effect, which is a phenomenon in which electromotive force is generated by a temperature difference, and a device using a Peltier effect, which is a phenomenon in which heat is absorbed (or generated) by current. Although there are Peltier devices, the present invention is assumed to mean Peltier devices.

펠티에 효과는 2종류의 금속 끝을 접속시키고 여기에 전류를 흘려보내면, 전류 방향에 따라 한쪽 단자는 흡열하고, 다른 쪽 단자는 발열을 일으키는 현상으로서, 2종류의 금속 대신 전기전도 방식이 다른 비스무트(Bi), 텔루르(Te) 등 반도체를 사용하면, 효율성 높은 흡열 및 발열 작용을 하는 펠티에소자를 얻을 수 있다.The Peltier effect is a phenomenon in which two types of metal ends are connected and current is flowed to one terminal to absorb heat and the other terminal to generate heat depending on the current direction. By using a semiconductor such as Bi) or tellurium (Te), a Peltier device having an efficient endothermic and exothermic action can be obtained.

본 발명의 반도체 패키지에 적용되는 열전소자(20)는 다수의 N형 반도체소자(22) 및 P형 반도체소자(24)를 순차적으로 교번 배열시킨 상태에서, 서로 인접한 N형 반도체소자(22)와 P형 반도체소자(24)의 저면을 제1금속패턴(26)으로 연결하여 발열부(28)를 구성하고, 또한 서로 인접한 P형 반도체소자(24)와 N형 반도체소자(22)의 상면을 제2금속패턴(30)으로 연결하여 냉각부(32)를 구성한다.The thermoelectric element 20 applied to the semiconductor package according to the present invention includes a plurality of N-type semiconductor elements 22 and P-type semiconductor elements 24 in a state where the N-type semiconductor elements 22 are adjacent to each other. The bottom surface of the P-type semiconductor element 24 is connected to the first metal pattern 26 to form the heat generating unit 28, and the upper surfaces of the P-type semiconductor element 24 and the N-type semiconductor element 22 adjacent to each other are formed. The cooling unit 32 is formed by connecting with the second metal pattern 30.

또한, 상기 N형 반도체소자(22)와 P형 반도체소자(24)의 사이 공간 또는 상기 P형 반도체소자(24)와 N형 반도체소자(22)의 사이 공간에 절연체(34)가 채워지고, 특히 각 반도체 칩(10)과의 절연을 위하여 상기 제1 및 제2금속패턴(26,30)과, 상기 절연체(34)의 상하면에 절연필름(36)이 부착된다.Further, an insulator 34 is filled in the space between the N-type semiconductor element 22 and the P-type semiconductor element 24 or the space between the P-type semiconductor element 24 and the N-type semiconductor element 22, In particular, the insulating film 36 is attached to the first and second metal patterns 26 and 30 and the upper and lower surfaces of the insulator 34 to insulate the semiconductor chip 10.

이렇게 구성된 열전소자(20)를 관통 실리콘 비아(16)를 통해 서로 전기적 신호 교환 가능하게 적층된 각각의 반도체 칩(10) 사이에 내재시킨다.The thermoelectric element 20 configured as described above is embedded between each of the semiconductor chips 10 stacked so as to exchange electrical signals with each other through the through silicon vias 16.

이때, 각 반도체 칩(10) 사이에 존재하는 열전소자(20)들에 직류전원을 공급하기 위한 전원공급수단, 즉 하나의 전기적인 직류 회로를 구성하게 되는데, 이를 보다 상세하게 설명하면 다음과 같다.At this time, the power supply means for supplying the DC power to the thermoelectric elements 20 existing between each semiconductor chip 10, that is, constitute an electrical DC circuit, which will be described in more detail as follows. .

먼저, 상기 반도체 칩(10)들에 관통 실리콘 비아(16)를 형성할 때, 그 인접부위에 한 쌍의 전극삽입홀(38,40)을 관통 형성한다.First, when the through silicon vias 16 are formed in the semiconductor chips 10, a pair of electrode insertion holes 38 and 40 are formed through the adjacent portions thereof.

다음으로, 한 쌍의 전극삽입홀중 하나(38)에 (+)전극봉(42)을 삽입하는 바, 이 (+)전극봉(42)은 각 열전소자(20)의 일측단부 즉, N형 반도체소자(22)와 연결된 제2금속패턴(30)과 통전 가능하게 연결되고, (+)전극봉(42)의 하단끝은 기판(46)의 전도성패턴(48)에 연결되도록 한다.Next, the positive electrode 42 is inserted into one of the pair of electrode insertion holes, and the positive electrode 42 is formed at one end of each thermoelectric element 20, that is, an N-type semiconductor. The second metal pattern 30 connected to the element 22 is electrically connected to each other, and the lower end of the (+) electrode 42 is connected to the conductive pattern 48 of the substrate 46.

또한, 한 쌍의 전극삽입홀중 다른 하나(40)에 (-)전극봉(44)을 삽입하는 바, 이 (-)전극봉(44)은 각 열전소자(20)의 타측단부 즉, P형 반도체소자(24)와 연결된 제2금속패턴(30)과 통전 가능하게 연결시키고, (-)전극봉(44)의 하단끝을 기판(46)의 전도성패턴(48)에 연결시킨다.In addition, the (-) electrode rod 44 is inserted into the other one 40 of the pair of electrode insertion holes, and the (-) electrode rod 44 has the other end of each thermoelectric element 20, that is, a P-type semiconductor. The second metal pattern 30 connected to the element 24 is electrically connected to each other, and the lower end of the negative electrode 44 is connected to the conductive pattern 48 of the substrate 46.

여기서, 본 발명에 따른 반도체 패키지에서 열전소자에 의한 칩의 열방출 동작을 설명하면 다음과 같다.Here, the heat dissipation operation of the chip by the thermoelectric element in the semiconductor package according to the present invention will be described.

먼저, 마더보드(미도시됨)로부터의 시그널 신호 및 파워가 기판을 통하여 각 반도체 칩(10)에 전달되고, 동시에 기판에 제공된 파워(직류 전원)가 (+)전극봉(42)을 통해 열전소자(20)로 전달된다.First, a signal signal and power from a motherboard (not shown) are transmitted to each semiconductor chip 10 through the substrate, and at the same time, the power (direct current power) provided to the substrate is transferred through the positive electrode 42. Is passed to 20.

따라서, 열전소자(20)에 공급된 직류 전원이 N형 반도체소자(22)에서 P형 반도체소자(24)쪽으로 흐르게 되고, 펠티에(Peltier) 효과에 의해 상기 열전소자(20)의 상면 즉, 냉각부(32)에서는 냉각 현상이 발생하고, 상기 열전소자(10)의 하면 즉, 발열부(28)에서는 발열 반응이 일어난다.Accordingly, the DC power supplied to the thermoelectric element 20 flows from the N-type semiconductor element 22 to the P-type semiconductor element 24, and the upper surface of the thermoelectric element 20, that is, the cooling, is cooled by the Peltier effect. In the unit 32, a cooling phenomenon occurs, and an exothermic reaction occurs in the lower surface of the thermoelectric element 10, that is, the heat generating unit 28.

이에, 적층된 각 반도체 칩(10)들의 저면과 접촉된 열전소자(20)의 상면 즉, 냉각부(32)에서 냉각 반응이 일어나므로, 각 반도체 칩(10)에서 발생되는 열이 상쇄되어 상기 반도체 칩(10)을 저온 상태로 냉각시키게 된다.Accordingly, since a cooling reaction occurs on the upper surface of the thermoelectric element 20, that is, the cooling unit 32, which is in contact with the bottom surfaces of the stacked semiconductor chips 10, heat generated in each semiconductor chip 10 is canceled out. The semiconductor chip 10 is cooled to a low temperature state.

이와 동시에, 상기 열전소자(20)의 상면 즉, 발열부(28)에서 발생된 열은 열전소자(20)에 흐르는 전류를 제어하여 반도체 칩(10)에서 발생되는 열에 비하여 낮은 온도로 발열되도록 함으로써, 상기 발열부(28)도 반도체 칩(10)에서 발생된 열을 일부 냉각시키는 기능을 하게 된다.At the same time, the heat generated from the upper surface of the thermoelectric element 20, that is, the heat generator 28, controls the current flowing through the thermoelectric element 20 to generate heat at a lower temperature than the heat generated from the semiconductor chip 10. The heat generating unit 28 also functions to cool some of the heat generated by the semiconductor chip 10.

또한, 상기 반도체 칩(10)들에서 발생되는 열이 열전소자(20)의 냉각 작용에 의하여 대부분 냉각되지만, (+) 및 (-)전극봉(42,44)을 따라 전도되어 기판(46)을 통해 외부로 방출되는 효과도 함께 얻을 수 있으므로, 결국 적층된 반도체 칩들에서 발생되는 열을 효과적으로 방출시킬 수 있다.In addition, the heat generated from the semiconductor chips 10 is mostly cooled by the cooling action of the thermoelectric element 20, but is conducted along the (+) and (−) electrode rods 42 and 44 to conduct the substrate 46. In addition, since the effect of being released to the outside can be obtained together, the heat generated in the stacked semiconductor chips can be effectively released.

도 1은 본 발명에 따른 열전소자를 이용한 반도체 패키지를 나타내는 단면도,1 is a cross-sectional view showing a semiconductor package using a thermoelectric device according to the present invention;

도 2는 본 발명에 따른 반도체 패키지에 적용된 열전소자의 구조를 설명하는 단면도,2 is a cross-sectional view illustrating a structure of a thermoelectric element applied to a semiconductor package according to the present invention;

도 3은 관통 실리콘 비아를 이용한 칩 적층 방법을 설명하는 단면도.3 is a cross-sectional view illustrating a chip stacking method using through silicon vias.

<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>

10 : 반도체 칩 12 : 수직홀10 semiconductor chip 12 vertical hole

14 : 전도성금속 16 : 관통 실리콘 비아14 conductive metal 16 through silicon via

18 : 전도성범프 20 : 열전소자18: conductive bump 20: thermoelectric element

22 : N형 반도체소자 24 : P형 반도체소자22 N-type semiconductor device 24 P-type semiconductor device

26 : 제1금속패턴 28 : 발열부26: first metal pattern 28: heat generating portion

30 : 제2금속패턴 32 : 냉각부30: second metal pattern 32: cooling unit

34 : 절연체 36 : 절연필름34: insulator 36: insulating film

38,40 : 전극삽입홀 42 : (+)전극봉38, 40: electrode insertion hole 42: (+) electrode

44 : (-)전극봉 46 : 기판44: (-) electrode 46: substrate

48 : 전도성패턴48: conductive pattern

Claims (3)

관통 실리콘 비아를 통해 전기적 신호 교환 가능하게 적층된 복수개의 반도체 칩과;A plurality of semiconductor chips stacked such that electrical signals can be exchanged through the through silicon vias; 상기 복수개의 반도체 칩이 전기적 신호 교환 가능하게 탑재되는 기판과;A substrate on which the plurality of semiconductor chips are mounted to exchange electrical signals; 상기 기판상에 반도체 칩들을 감싸면서 몰딩된 몰딩 컴파운 수지와;A molding compound resin molded while wrapping the semiconductor chips on the substrate; 상기 각 반도체 칩 사이에 내재되는 복수개의 열전소자와;A plurality of thermoelectric elements embedded between the semiconductor chips; 상기 열전소자들에 직류전원를 공급하는 전원공급수단;Power supply means for supplying DC power to the thermoelectric elements; 을 포함하여 구성된 것을 특징으로 하는 열전소자를 이용한 반도체 패키지.Semiconductor package using a thermoelectric element, characterized in that configured to include. 청구항 1에 있어서, 상기 열전소자는:The method according to claim 1, wherein the thermoelectric element is: 순차적으로 교번 배열된 다수의 N형 반도체소자 및 P형 반도체소자와;A plurality of N-type semiconductor devices and P-type semiconductor devices sequentially arranged; 서로 인접한 N형 반도체소자와 P형 반도체소자의 저면이 제1금속패턴으로 연결된 발열부와;A heat generation unit having bottom surfaces of the N-type semiconductor element and the P-type semiconductor element adjacent to each other by a first metal pattern; 서로 인접한 P형 반도체소자와 N형 반도체소자의 상면이 제2금속패턴으로 연결된 냉각부와;A cooling unit having upper surfaces of adjacent P-type semiconductor elements and N-type semiconductor elements connected to each other by a second metal pattern; 상기 N형 반도체소자와 P형 반도체소자의 사이 공간 또는 상기 P형 반도체소자와 N형 반도체소자의 사이 공간에 채워지는 절연체와;An insulator filled in a space between the N-type semiconductor element and the P-type semiconductor element or a space between the P-type semiconductor element and the N-type semiconductor element; 상기 제1 및 제2금속패턴과, 절연체의 상하면에 부착되는 절연필름;Insulating films attached to upper and lower surfaces of the first and second metal patterns and an insulator; 으로 구성된 것을 특징으로 하는 열전소자를 이용한 반도체 패키지.Semiconductor package using a thermoelectric element, characterized in that consisting of. 청구항 1 또는 청구항 2에 있어서, 상기 전원공급수단은:The method according to claim 1 or 2, wherein the power supply means: 각 반도체 칩의 소정 위치에 관통 형성된 한 쌍의 전극삽입홀과;A pair of electrode insertion holes formed through the semiconductor chip at predetermined positions; 한 쌍의 전극삽입홀중 하나에 삽입되어 각 열전소자의 일측단부에 연결되는 동시에 그 하단끝은 기판에 전기적으로 연결되는 (+)전극봉과;(+) Electrode rods inserted into one of the pair of electrode insertion holes and connected to one end of each thermoelectric element, and the lower end thereof is electrically connected to the substrate; 한 쌍의 전극삽입홀중 다른 하나에 삽입되어 각 열전소자의 타측단부에 연결되는 동시에 그 하단끝은 기판에 전기적으로 연결되는 (-)전극봉;A negative electrode rod which is inserted into the other one of the pair of electrode insertion holes and connected to the other end of each thermoelectric element, and the lower end thereof is electrically connected to the substrate; 으로 구성된 것을 특징으로 하는 열전소자를 이용한 반도체 패키지.Semiconductor package using a thermoelectric element, characterized in that consisting of.
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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101132754B1 (en) * 2010-05-19 2012-04-06 윤인숙 Manufacturing method of led bare chip
KR101315525B1 (en) * 2011-10-27 2013-10-08 홍익대학교 산학협력단 Light emitting diode package having thermal via
US9228763B2 (en) 2011-12-01 2016-01-05 Samsung Electronics Co., Ltd. Thermoelectric cooling packages and thermal management methods thereof
WO2020075958A1 (en) * 2018-10-11 2020-04-16 코나아이 주식회사 Electronic card and electronic card manufacturing method

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101132754B1 (en) * 2010-05-19 2012-04-06 윤인숙 Manufacturing method of led bare chip
KR101315525B1 (en) * 2011-10-27 2013-10-08 홍익대학교 산학협력단 Light emitting diode package having thermal via
US9228763B2 (en) 2011-12-01 2016-01-05 Samsung Electronics Co., Ltd. Thermoelectric cooling packages and thermal management methods thereof
US9671141B2 (en) 2011-12-01 2017-06-06 Samsung Electronics Co., Ltd. Thermoelectric cooling packages and thermal management methods thereof
US10658266B2 (en) 2011-12-01 2020-05-19 Samsung Electronics Co., Ltd. Thermoelectric cooling packages and thermal management methods thereof
WO2020075958A1 (en) * 2018-10-11 2020-04-16 코나아이 주식회사 Electronic card and electronic card manufacturing method

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