KR20090132359A - Light emitting diode display device and method for driving the same - Google Patents

Abstract

PURPOSE: A light emitting display device and a manufacturing method thereof are provided to prevent degradation of image quality by uniformly keeping a level of common power in all parts of cathode electrode. CONSTITUTION: A lower and upper substrate(100,200) is faced with each other. A pixel definition layer(150) is formed in a non-emitting area of the lower substrate. A spacer(160) is formed on the pixel definition layer. One side of a cathode electrode is connected to a common power line.

Description

LIGHT EMITTING DIODE DISPLAY DEVICE AND METHOD FOR DRIVING THE SAME}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a light emitting display device, and more particularly, to a light emitting display device and a method of manufacturing the same, which can prevent deterioration of image quality by maintaining substantially the same size of common power in all parts of the cathode electrode.

Recently, researches on top emission display structures have been actively conducted to improve image quality and color characteristics of AMOLED (Active Matrix Organic Light Emitting Diode) panels. In order to implement a top emission display, an organic thin film layer is generally deposited on a substrate, and a cathode electrode is deposited on the front surface of the substrate including the organic thin film layer. In this case, since the cathode electrode requires high transmittance, a metal material having high transparency to light and excellent conductivity is used.

In order to increase the transparency of the cathode electrode, it is effective to make the thickness thereof as thin as possible. However, if the thickness is reduced, the resistance of the cathode electrode increases, resulting in a decrease in conductivity, resulting in a problem in that the size of the common power source in all parts of the cathode electrode varies in each position of the panel.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and forms a power compensation electrode on an upper substrate, electrically connects the power compensation electrode and a cathode electrode on a spacer formed on the lower substrate, and electrically connects the cathode. SUMMARY OF THE INVENTION An object of the present invention is to provide a light emitting display device and a method of manufacturing the same, by which one side is connected to a common power supply line so that the size of the common power supply is almost the same in all parts of the cathode electrode.

According to an aspect of the present invention, there is provided a light emitting display device including: a lower and an upper substrate including a non-light emitting area and a plurality of light emitting areas and facing each other; A pixel defining layer formed in the non-light emitting region of the lower substrate; A spacer formed on the pixel defining layer; An anode electrode formed in each light emitting region of the lower substrate; An organic thin film layer formed on each of the emission regions of the lower substrate and the front surface of the lower substrate; A cathode electrode formed on the front surface of the lower substrate including the spacer, the anode electrode, and the organic thin film layer, and connected to a common power line to which one side transmits common power; An auxiliary electrode formed in the non-light emitting region of the upper substrate to face the spacer of the lower substrate; And a power compensation electrode formed on the front surface of the upper substrate including the auxiliary electrode and in contact with the cathode electrode on the spacer.

In addition, a method of manufacturing a light emitting display device according to the present invention for achieving the above object comprises the steps of preparing a lower and an upper substrate comprising a non-light emitting region and a plurality of light emitting regions; Forming a plurality of thin film transistors in the non-light emitting region of the lower substrate and forming a common power wiring for transmitting common power to an outer portion of the lower substrate; Forming a protective film on the entire surface of the lower substrate including the thin film transistors and the common power wiring; Forming a source contact hole exposing the source electrode of the thin film transistor and a wiring contact hole exposing the common power line in the passivation layer; An anode electrode is formed in the light emitting region of the lower substrate to be connected to the source electrode through the source contact hole, and a pad electrode is formed at an outer portion of the lower substrate to be connected to the common power wiring through the wiring contact hole. Forming; Forming a pixel defining layer on a passivation layer in the non-light emitting region of the lower substrate; Forming a spacer on the pixel definition layer; Forming an organic thin film layer on an entire surface of the lower substrate including the spacers, and forming a light emitting layer in the organic thin film layer in a light emitting region of the lower substrate; Forming a cathode on a front surface of the lower substrate including the spacer, the anode electrode, and the organic thin film layer so that one side is connected to a common power line for transmitting common power; Forming an auxiliary electrode in a non-light emitting area of the upper substrate to face the spacer of the lower substrate; Forming a power compensation electrode on a front surface of the upper substrate including the auxiliary electrode; And bonding the upper substrate and the lower substrate to contact the cathode electrode and the power compensation electrode on the spacer with each other.

The light emitting display device according to the present invention has the following effects.

According to the present invention, a power compensation electrode is formed on an upper substrate, the power compensation electrode and a cathode electrode on a spacer formed on the lower substrate are electrically connected to each other, and one side of the cathode electrode is connected to a common power supply wiring. It is possible to keep the size of the common power supply almost the same in all parts.

1 is a view showing a light emitting display device according to a first embodiment of the present invention.

The light emitting display device according to the first exemplary embodiment of the present invention includes a panel including the lower and upper substrates 100 and 200 bonded together as shown in FIG. 1.

The lower and upper substrates 100 and 200 include an array portion having a plurality of light emitting regions for displaying an image, and an outer portion formed with circuits for providing various signals necessary for operating a light emitting element formed in the light emitting region of the array portion. do. Here, the array portion of the lower substrate 100 and the upper substrate 200 includes a non-light emitting area and a plurality of light emitting areas. The lower and upper substrates 100 and 200 are bonded to each other by a sealant. This sealant is formed at the periphery of the lower and upper substrates 100 and 200.

Here, the non-light emitting area has a lattice shape having a plurality of exposed areas exposing the light emitting areas. The light emitting area refers to a pixel area in which light from the light emitting device is emitted, and the non-light emitting area refers to an area in which a thin film transistor (TFT) or the like for operating the light emitting device is formed.

Meanwhile, in the top emission structure in which light from the light emitting device is emitted through the upper substrate 200, the thin film transistor TFT may be formed in the emission region of the lower substrate 100.

The thin film transistor TFT shown in FIG. 1 has a bottom gate structure using a-Si, and although not shown in the drawing, the thin film transistor TFT may have a top gate structure using polysilicon.

Here, the structure of the lower substrate 100 will be described in detail.

The lower substrate 100 may include a gate electrode GE formed in a light emitting region of the lower substrate 100, a gate insulating layer GI formed on an entire surface of the lower substrate 100 including the gate electrode GE, and the gate. The semiconductor layer SC formed on the gate insulating layer GI so as to overlap the electrode GE, the ohmic contact layer OM formed at both edges of the semiconductor layer SC, and the ohmic contact layer OM. Source / drain electrodes SE and DE formed in the substrate, and a passivation layer PAS formed on the entire surface of the lower substrate 100 including the source / drain electrodes SE and DE. The gate electrode GE, the source / drain electrodes SE and DE, the semiconductor layer SC, the ohmic contact layer OM, the gate insulating layer GI, and the passivation layer PAS may be formed of a thin film transistor TFT. Form.

The light emitting device including the anode electrode AE, the organic thin film layer EL, and the cathode electrode CE is formed on the passivation layer PAS, and the pixel defining layer 150 and the spacer 160 are formed.

The common power supply line COM is formed on the gate insulating layer GI positioned at the outer portion of the lower substrate 100. The common power line COM is a wire for transmitting a common power source, and the common power source is a power source commonly applied to each cathode electrode CE of the light emitting devices. The common power line COM is formed of the same material as the source / drain electrodes SE and DE. In other words, the common power supply line COM and the source / drain electrodes SE and DE are simultaneously manufactured through the same mask process. The common power supply line COM is electrically connected to the cathode electrode CE through the pad electrode PE.

A source contact hole SH and a wiring contact hole LH are formed in the passivation layer PAS. The source contact hole SH passes through the passivation layer PAS to expose a portion of the source electrode SE, and the interconnection contact hole LH passes through the passivation layer PAS to pass through the common power line COM. Part of the

The common power line COM is electrically connected to the pad electrode PE through the wiring contact hole LH, and the source electrode SE of the thin film transistor is connected to the anode through the source contact hole SH. It is electrically connected to the electrode AE.

The anode AE is selected from indium tin oxide (ITO), ITO / Ag, ITO / Ag / ITO, ITO / Ag / IZO (Indium Zinc Oxide), silver alloy (ITO / Ag alloy / ITO) and equivalents thereof It may be formed of at least one.

The ITO is a transparent conductive film having a uniform work function and a small hole injection barrier for the light emitting device, and the Ag is a film which reflects light from the light emitting device to the top surface in the top emission mode.

Although not shown, the anode AE may be formed in the non-light emitting area to maximize the aperture ratio of the light emitting area.

The pixel defining layer 150 may be formed on the passivation layer PAS and the anode electrode AE. In addition, the pixel defining layer 150 is formed in the non-light emitting area in order to increase the aperture ratio of the light emitting area. The pixel defining layer 150 makes the boundary between the light emitting elements located in each light emitting area clearly distinguished so that the light emitting boundary areas between the light emitting areas become clear.

The pixel defining layer 150 includes an inclined surface that is formed obliquely on the anode AE. The inclined surface may have an angle formed with the anode AE, that is, a taper angle of 10 degrees to 20 degrees.

The lower limit of the angle formed by the inclined surface with the anode AE is 10 degrees because the pixel defining layer 150 itself has a thickness. In addition, when the angle is lowered to 10 degrees or less and the pixel defining layer 150 is thinned, tunneling phenomenon may occur at the anode AE, and as a result, an insulation function may be damaged.

In addition, the upper limit of the angle between the inclined surface and the anode electrode AE is determined to be 20 degrees when the light emitting layer OEL is formed by using a laser thermal transfer method (LITI) when the angle is 20 degrees or more. This is because it is difficult for the light emitting layer OEL to be properly formed at a desired position, so that an open edge may occur.

In addition, the pixel defining layer 150 has its own thickness. The thickness of the pixel defining layer 150 may be defined by the thickness of the pixel defining layer 150 formed on the passivation layer PAS. That is, it may be referred to as the thickest part of the pixel defining layer 150. The pixel defining layer 150 may have a thickness of about 150 nm to about 200 nm.

The upper limit of the thickness of the pixel defining layer 150 is 200 nm because the taper angle is increased when the thickness is 200 nm or more, so that an open edge may occur.

The spacer 160 is formed on the pixel defining layer 150. In more detail, as shown in FIG. 1, the spacer 160 is formed to protrude on the pixel defining layer 150. The spacer 160 prevents the upper substrate 200 from bending when the lower substrate 100 and the upper substrate 200 are bonded to each other.

The organic thin film layer EL includes a hole injection layer HIL, a hole transport layer HTL, a light emitting layer OEL, an electron injection layer EIL, and an electron transport layer ETL. The hole injection layer HIL is formed on the entire surface of the lower substrate 100 including the anode electrode AE, the pixel defining layer 150, and the spacer 160, and the hole transport layer HTL is formed in the hole injection layer ( The light emitting layer OEL is formed on the entire surface of the lower substrate 100 including the HIL, and the light emitting layer OEL is formed on the hole transport layer HTL in the light emitting region, and the electron injection layer EIL is formed on the light emitting layer OEL and the hole transport layer. (HTL) is formed on the front surface of the lower substrate 100, and the electron transport layer (ETL) is formed on the front surface of the lower substrate 100 including the electron injection layer (EIL).

The light emitting layer OEL includes a red light emitting layer OEL for displaying red, a green light emitting layer OEL for displaying green, and a blue light emitting layer OEL for displaying blue. The light emitting layer OEL formed in each light emitting area is any one of the red light emitting layer OEL, the green light emitting layer OEL, and the blue light emitting layer OEL. The red light emitting layer OEL, the green light emitting layer OEL, and the blue light emitting layer OEL form one unit pixel. The unit pixel may further include a white light emitting layer, in which one unit pixel includes a red light emitting layer (OEL), a green light emitting layer (OEL), a blue light emitting layer (OEL), and a white light emitting layer.

The light emitting layer (OEL) is patterned to be selectively formed only in the light emitting region, a method for patterning the light emitting layer (OEL), when the light emitting layer (OEL) is a low molecular organic material method using a shadow mask (shadow mask) In the case where the light emitting layer OEL is a polymer material, there is inkjet printing or laser induced thermal imaging (hereinafter referred to as LITI). Among them, the laser thermal transfer method (LITI) has the advantage of being able to finely pattern the light emitting layer (OEL), use for a large area, and advantageous for high resolution, whereas the inkjet printing is a wet process. The advantage is a dry process.

The cathode electrode CE is formed on the entire surface of the lower substrate 100 including the electron transport layer ETL, and one side thereof is connected to the pad electrode PE. The cathode electrode CE may have a structure in which ITO and AgCa, which is a translucent material, are stacked. That is, a cathode electrode can be made by first forming a translucent material having a good work function with the organic thin film layer and forming ITO on the translucent material.

Next, the structure of the upper substrate 200 will be described in detail.

The upper substrate 200 includes an auxiliary electrode E2 and a power compensation electrode E1.

The auxiliary electrode E2 is formed in the non-light emitting area of the upper substrate 200 so as to face the spacer 160 of the lower substrate 100, and the power compensation electrode E1 includes the auxiliary electrode E2. It is formed on the front surface of the upper substrate 200. In this case, the power compensation electrode E1 contacts the cathode electrode CE on the spacer 160. That is, the power compensation electrode E1 is electrically connected to the cathode electrode CE on the spacer 160.

As described above, since one side of the cathode electrode CE is connected to the common power supply line COM through the pad electrode PE, the power compensation electrode E1 and the auxiliary electrode eventually connected to the cathode electrode CE. E2 receives a common power supply from the common power supply wiring COM. The power compensation electrode E1 is electrically connected to the cathode electrode CE to lower the resistance of the cathode electrode CE. Accordingly, the common power supplied from the common power supply line COM to the cathode electrode CE exhibits almost the same value without distortion in any part of the cathode electrode CE. In other words, the common power source from the common power supply line COM is connected to the cathode electrode CE of the lower substrate 100 as well as the electrode of the upper substrate 200 through the power compensation electrode E1 and the auxiliary electrode E2. It is stably supplied to the light emitting elements of all the light emitting regions in the array portion.

The power compensation electrode E1 is formed on the front surface of the upper substrate 200. The power compensation electrode E1 is formed of ITO (Indium) in order to minimize a decrease in light transmittance emitted from the light emitting device toward the power compensation electrode E1. Tin Oxide, IZO (Indium Zinc Oxide) and AZO (Al- dopped Zinc Oxide) are formed of any one of the materials. In addition, the auxiliary electrode E2 may be any one of a low resistance metal material, for example, silver (Ag), aluminum (Al), aluminum alloy (AlNd), and molybdenum (Mo) material to reinforce the voltage of the cathode electrode CE. It is formed as one. Since the auxiliary electrode E2 can reduce the light transmittance, it is selectively formed only in the non-light emitting area.

The light emitting display device according to the first embodiment of the present invention is a top light emitting display device, and the light from the light emitting layer OEL passes through the upper substrate 200 and is emitted to the outside.

2 is a plan view of the spacer 160 of FIG. 1.

The spacer 160 has a lattice shape with a plurality of exposed areas 222 exposing the light emitting areas, as shown in FIG. 2.

3 is another plan view of the spacer 160 of FIG. 1.

As shown in FIG. 3, the spacer 160 may be formed of a plurality of column spacers 160 formed in the non-light emitting region of the lower substrate 100.

Although not shown in the drawing, the auxiliary electrode E2 of the upper substrate 200 may have a lattice shape such as the spacer 160 shown in FIG. 2.

The method of manufacturing the light emitting display device according to the present invention configured as described above will be described in detail as follows.

4A to 4F are cross-sectional views illustrating a method of manufacturing the light emitting display device of the present invention.

First, as shown in FIG. 4A, a lower substrate 100 including a non-light emitting area and a plurality of light emitting areas is prepared.

In addition, a metal is deposited on the entire surface of the lower substrate 100, and patterned through a photo and etching process to form a gate electrode GE in a non-light emitting region of the lower substrate 100.

Thereafter, a gate insulating layer GI including an insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx) is deposited on the entire surface of the lower substrate 100 including the gate electrode GE.

Subsequently, a semiconductor material such as intrinsic amorphous silicon and an impurity semiconductor material such as amorphous silicon to which impurities are added are sequentially deposited on the gate insulating layer GI, and the patterns are patterned through a photo and etching process to thereby form the gate electrode GE. The semiconductor layer SC and the ohmic contact layer OM are sequentially formed on the gate insulating layer GI.

Next, a metal layer, such as chromium or molybdenum, is deposited on the entire surface of the lower substrate 100 including the semiconductor layer SC and the ohmic contact layer OM, and patterned through a photo and etching process to form the semiconductor layer SC. The thin film transistor is fabricated by forming source / drain electrodes SE and DE at both edges except for the channel region of. In this case, the portion of the ohmic contact layer OM formed on the channel region of the semiconductor layer SC is removed. At the same time, a common power supply line COM made of the same material as the source / drain electrodes SE and DE is manufactured on the gate insulating layer GI positioned at the outer portion of the lower substrate 100.

Subsequently, the passivation layer PAS is deposited on the entire surface of the lower substrate 100 including the source / drain electrodes SE and DE and the gate insulating layer GI using an organic insulating layer or the like.

Through this process, the thin film transistor and the common power supply line COM are formed on the lower substrate 100.

Next, as shown in FIG. 4B, a portion of the passivation layer PAS is removed through a photo and etching process to expose a portion of the source electrode SE, and the common power line. The wiring contact hole LH exposing a part of the COM is simultaneously formed.

In addition, ITO (Indium Tin Oxide), ITO / Ag, ITO / Ag / ITO, ITO / Ag / IZO (Indium) are formed on the entire surface of the lower substrate 100 on which the source contact hole SH and the wiring contact hole LH are formed. Zinc oxide, silver alloy (ITO / Ag alloy / ITO), and at least one selected from the equivalents thereof are deposited and patterned by photo and etching processes, so that the anode electrode AE is formed in the light emitting region of the lower substrate 100. To form. At the same time, the pad electrode PE is formed on the outer portion of the lower substrate 100. Here, one side of the anode electrode AE is connected to the source electrode SE through the source contact hole SH, and the pad electrode PE is connected to the common power line through the wiring contact hole LH. COM).

Thereafter, as shown in FIG. 4C, an insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx) is deposited on the entire surface of the lower substrate 100 including the anode AE, and the photo and etching process is performed. The pixel defining layer 150 is formed in the non-emission region of the lower substrate 100 by patterning the semiconductor substrate through the patterning process. In this case, the pixel defining layer 150 is formed to cover the edge of the anode AE.

Next, as shown in FIG. 4D, the photoresist is coated on the entire surface of the lower substrate 100 including the pixel defining layer 150, and patterned through a photo and etching process to thereby form the pixel defining layer ( Spacer 160 is formed on 150. Meanwhile, the spacer 160 may be formed by inkjet printing.

Subsequently, as shown in FIG. 4E, a hole injection layer HIL and a hole transport layer HTL are sequentially formed on the entire surface of the lower substrate 100 including the spacer 160. The light emitting layer OEL is formed on the hole transport layer HTL positioned on the light emitting region. The emission layer OEL may be formed using the above-described thermal transfer method. In this case, the light emitting layer OEL is divided into a red light emitting layer OEL, a green light emitting layer OEL, and a blue light emitting layer OEL, and each light emitting layer OEL is sequentially formed for each color.

Thereafter, the electron injection layer EIL and the electron transport layer ETL are sequentially formed on the entire surface of the lower substrate 100 on which the emission layer OEL is formed.

Subsequently, as shown in FIG. 4F, a portion of the hole injection layer HIL, the hole transport layer HTL, the electron injection layer EIL, and the electron transport layer ETL positioned at the outer portion may be removed by a photo and etching process. The pad contact hole PH exposing the pad electrode PE is formed.

Next, the cathode electrode CE is formed by depositing ITO or AgCa on the entire surface of the lower substrate 100 on which the pad contact hole PH is formed. In this case, one side of the cathode electrode CE is electrically connected to the pad electrode PE through the pad contact hole PH.

In this way, the process of the lower substrate 100 is completed.

Next, the manufacturing method of the upper substrate 200 will be described in detail.

First, an upper substrate 200 including a non-light emitting area and a plurality of light emitting areas is prepared.

The metal is deposited on the entire surface of the upper substrate 200 and patterned through photo and etching processes to form the auxiliary electrode E2 in the non-light emitting region of the upper substrate 200.

Thereafter, ITO is deposited on the entire surface of the upper substrate 200 on which the power compensation electrode E1 is formed to form the power compensation electrode E1.

In this way, the process of the upper substrate 200 is completed.

Next, the lower and upper substrates 100 and 200 are bonded to each other using a sealant. As the lower and upper substrates 100 and 200 are bonded to each other, the cathode electrode CE formed on the spacer 160 of the lower substrate 100 contacts the power compensation electrode E1 of the upper substrate 200. Are electrically connected to each other.

5 is a view showing a light emitting display device according to a second embodiment of the present invention.

The light emitting display device according to the second embodiment of the present invention is almost similar to the first embodiment, and the material of the light emitting layer OEL and the structure of the upper substrate 200 in the lower substrate 100 are different.

That is, all of the light emitting layers OEL of the lower substrate 100 are light emitting layers OEL emitting white light, and the upper substrate 200 includes white light from the light emitting layer OEL among red, green, and blue colors. It includes a plurality of red color filter layer (CF), green color filter layer (CF) and blue color filter layer (CF) to represent any one color. The color filter layers CF are formed in the emission area of the upper substrate 200. The reference numeral 500 is an insulating layer covering the color filter layers CF.

The light emitting layer OEL in the second embodiment may be formed on the entire surface of the lower substrate 100 without the patterning process.

Although not shown in the drawings, a black matrix layer may be further formed between the color filter layers CF to prevent light leakage.

The present invention described above is not limited to the above-described embodiment and the accompanying drawings, and it is common in the art that various substitutions, modifications, and changes can be made without departing from the technical spirit of the present invention. It will be evident to those who have knowledge of.

1 is a view showing a light emitting display device according to a first embodiment of the present invention;

2 is a plan view of the spacer of FIG.

3 is another plan view of the spacer of FIG.

4A through 4F are cross-sectional views illustrating a method of manufacturing a light emitting display device according to the present invention.

5 is a view showing a light emitting display device according to a second embodiment of the present invention;

Claims (10)

A lower and upper substrate including a non-light emitting area and a plurality of light emitting areas, and facing each other; A pixel defining layer formed in the non-light emitting region of the lower substrate; A spacer formed on the pixel defining layer; An anode electrode formed in each light emitting region of the lower substrate; An organic thin film layer formed on each of the emission regions of the lower substrate and the front surface of the lower substrate; A cathode electrode formed on the front surface of the lower substrate including the spacer, the anode electrode, and the organic thin film layer, and connected to a common power line to which one side transmits common power; An auxiliary electrode formed in the non-light emitting region of the upper substrate to face the spacer of the lower substrate; And, And a power compensation electrode formed on the front surface of the upper substrate including the auxiliary electrode and in contact with the cathode electrode on the spacer. The method of claim 1, The auxiliary electrode has a lower resistance than the power compensation electrode, and the power compensation electrode has a higher light transmittance than the auxiliary electrode. The method of claim 2, The power compensation electrode is made of any one of indium tin oxide (ITO), indium zinc oxide (IZO) and al- dopped zinc oxide (AZO) materials; And, The auxiliary electrode is made of any one of silver (Ag), aluminum (Al), aluminum alloy (AlNd) and molybdenum (Mo) material. The method of claim 1, And the spacers have a lattice shape having a plurality of exposed areas exposing the light emitting areas. The method of claim 1, And the spacers are a plurality of column spacers formed on the pixel defining layer. The method of claim 1, One side of the cathode electrode is connected to the common power line through a pad electrode. The method of claim 1, The organic thin film layer of each light emitting region of the lower substrate includes any one of a red light emitting layer for displaying red, a green light emitting layer for displaying green, and a blue light emitting layer for displaying blue. The method of claim 1, The organic thin film layers of all the light emitting regions of the lower substrate include a white light emitting layer representing white color; And, One of a red color filter, a green color filter, and a blue color filter is formed in the light emitting regions of the upper substrate; And an insulating layer covering the red color filter, the green color filter, and the blue color filter on the lower substrate. The method of claim 8, And a black matrix layer formed between the color filter layers to prevent light leakage. Preparing a lower and an upper substrate including a non-light emitting area and a plurality of light emitting areas; Forming a plurality of thin film transistors in the non-light emitting region of the lower substrate and forming a common power wiring for transmitting common power to an outer portion of the lower substrate; Forming a protective film on the entire surface of the lower substrate including the thin film transistors and the common power wiring; Forming a source contact hole exposing the source electrode of the thin film transistor and a wiring contact hole exposing the common power line in the passivation layer; An anode electrode is formed in the light emitting region of the lower substrate to be connected to the source electrode through the source contact hole, and a pad electrode is formed at an outer portion of the lower substrate to be connected to the common power wiring through the wiring contact hole. Forming; Forming a pixel defining layer on a passivation layer in the non-light emitting region of the lower substrate; Forming a spacer on the pixel definition layer; Forming an organic thin film layer on an entire surface of the lower substrate including the spacers, and forming a light emitting layer in the organic thin film layer in a light emitting region of the lower substrate; Forming a cathode on a front surface of the lower substrate including the spacer, the anode electrode, and the organic thin film layer so that one side is connected to a common power line for transmitting common power; Forming an auxiliary electrode in a non-light emitting area of the upper substrate to face the spacer of the lower substrate; Forming a power compensation electrode on a front surface of the upper substrate including the auxiliary electrode; And, And bonding the upper substrate and the lower substrate to contact the cathode electrode and the power compensation electrode on the spacer with each other.

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