KR20090132292A - Method for fabricating non volatile memory device having floating gate - Google Patents

Abstract

PURPOSE: A manufacturing method of a nonvolatile memory device is provided to independently store electric charge to one unit cell by separating floating gate electrodes through a buffer layer pattern. CONSTITUTION: An interlayer insulation layer pattern, a buffer layer pattern, a tunnel oxide layer pattern(110a), and a trench are formed by etching an interlayer insulation layer, a buffer layer, a tunnel oxide layer, and a substrate(100). An insulation film is filled inside the trench. A control gate electrode layer is formed on the interlayer insulation layer and the insulation film. The control gate electrode layer, the interlayer insulation layer pattern, and the buffer layer pattern are selectively patterned. Both sides of the buffer layer pattern are recessed inwardly. A floating gate electrode is formed to both ends of a recessed buffer layer pattern(121a).

Description

Method for fabricating a nonvolatile memory device having a floating gate electrode

The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a nonvolatile memory device having a floating gate electrode.

Non-volatile memory devices are electrically programmable and erased, and are widely used in electronic components that maintain information even when power is cut off. The nonvolatile memory device may be classified into a floating gate type memory device and a floating trap type memory device.

In the case of a floating gate type memory device, a unit cell includes a control gate and a floating gate including a polysilicon layer, and performs a function of writing and erasing information according to the presence or absence of charge in the floating gate. . On the other hand, in the case of a floating trap type memory device, the unit cell includes a charge trap layer including a control gate and silicon nitride, and performs information writing and erasing functions depending on the presence or absence of a charge in the charge trap layer.

At this time, in the case of the floating trap type memory device, the charge stored in the charge trap layer is trapped by the trap site in the charge trap layer and cannot be moved, whereas in the case of the floating gate type memory device, the charge stored in the floating gate depends on the field difference. It is possible to move by. Therefore, in the case of a floating gate type memory device, since there is only a classification according to the amount of charge stored in the floating gate, it has a limited effect on improving the integration degree of the memory device. Accordingly, research has been made to implement a dual bit memory device that doubles the storage capacity in one unit cell in the floating gate type.

A method of manufacturing a nonvolatile memory device according to the present invention may include forming a tunnel oxide layer, a buffer layer, an interlayer insulating layer, and a hard mask layer pattern on a substrate; The hard mask layer pattern is used as an etch mask, and the exposed interlayer insulating layer, the buffer layer, the tunnel oxide layer, and the substrate are etched by a predetermined thickness to form a trench while forming a line-shaped interlayer insulating layer pattern, a buffer layer pattern, and a tunnel oxide layer pattern. Making; Selectively removing the hard mask layer pattern; Filling an insulating film in the trench from which the hard mask layer pattern is removed; Forming a control gate electrode layer on a resultant in which the insulating film is formed; Selectively patterning the control gate layer, the interlayer insulating layer pattern, and the buffer layer pattern in cell units; Recessing both sides of the buffer layer pattern separated by the cell in an inward direction; And forming floating gate electrodes separated by the recessed buffer layer pattern at both ends of the recessed buffer layer pattern.

The buffer layer may be formed to include an insulating layer having an etching rate relatively higher than that of the tunnel oxide layer and the interlayer insulating layer.

The insulating film is preferably formed of a SOD film or a TEOS film deposited by a chemical vapor deposition method.

It is preferable that the hard mask layer pattern is formed by forming a polysilicon layer or a silicon nitride layer alone or by laminating them.

The hard mask layer pattern may selectively expose the interlayer insulating layer so that the tunnel oxide layer, the buffer layer, and the interlayer insulating layer are separated in the word line direction.

The patterning of the cell unit may be performed by patterning the interlayer insulating layer pattern, the buffer layer pattern, the tunnel oxide layer pattern and the trench in a direction orthogonal to the direction in which the trench is formed.

The forming of the floating gate electrode may include forming a floating gate electrode layer on the entire surface of the resultant buffer layer pattern; And performing an isotropic etching process so that the floating gate electrode layer remains at both ends of the recessed buffer layer pattern.

The floating gate electrode layer preferably forms a polysilicon layer using a chemical vapor deposition method or an atomic layer deposition method.

The method may further include forming a capping layer before forming the floating gate electrode.

The capping film is preferably formed including a nitride film.

After forming the floating gate electrode, the method may further include performing an oxidation process.

(Example)

Referring to FIG. 1, a tunnel oxide layer 110, a buffer layer 120, an interlayer insulating layer 130, and a hard mask layer 140 are formed on a semiconductor substrate 100. ) Are formed sequentially. The tunnel oxide layer 110 serves as a path through which charge is transferred between the semiconductor substrate and the floating gate layer subsequently formed. The buffer layer 120 may be formed of an oxide film having a faster wet etching rate than the tunnel oxide layer 110 and the interlayer insulating layer 120, for example, a spin on dielectric (SOD) film or a TEOS film deposited by a chemical vapor deposition method. have. The buffer layer 120 is a film to be used to separate the floating gate in one subsequent unit cell.

The interlayer insulating layer 130 may be formed of a high dielectric material such as silicon oxide (SiO ₂ ), silicon nitride (Si _x N _y ), or alumina (Al ₂ O ₃ ), hafnium oxide (HfO ₃ ), or zirconium oxide (ZrO ₂ ). It can be used alone or in combination of the group containing the material to form a thin film. For example, the interlayer insulating layer 130 may be formed in a triple structure such as an oxide-nitride-oxide (ONO) structure, an oxide-alumina-oxide (AOA) structure, and an oxide-high K-oxide (OKO) structure. have. The interlayer insulating layer 130 serves to prevent the charge stored in the subsequently formed floating gate from moving to the upper layer, for example, the subsequently formed control gate electrode. The hard mask layer 140 may be formed by including a polysilicon layer or a silicon nitride layer, or may be formed by stacking a polysilicon layer and a silicon nitride layer. The hard mask layer 140 is subsequently patterned to expose the isolation region.

Referring to FIG. 2, a hard mask film pattern 140a for setting an active region is formed by performing a photolithogrphy process. The hard mask layer pattern 140a serves as an etch mask for separating devices between the interlayer insulating layer, the buffer layer, and the turning layer in the X-axis direction of the semiconductor substrate, for example, in the word line direction. The interlayer insulating layer, the buffer layer, the tunneling layer, and the semiconductor substrate exposed by the hard mask layer pattern 140a are sequentially etched to form a line type interlayer insulating layer pattern 130a, a buffer layer pattern 120a, and a tunneling layer. While forming the pattern 130a, the trench 141 having a predetermined depth is formed in the semiconductor substrate. As the interlayer insulating layer pattern 130a, the buffer layer pattern 120a, and the tunneling layer pattern 110a are formed, the interlayer insulating layer, the buffer layer, and the turning layer are separated in the X-axis direction, for example, in the word line direction.

Referring to FIG. 3A, after the hard mask layer pattern 140a of FIG. 2 is selectively removed, the interlayer insulating layer pattern 130a, the buffer layer pattern 120a, and the tunneling layer pattern 110a are filled with the trench 141. The insulating film 150 which fills in the gap is formed. Specifically, after the insulating film 150 is formed on the entire surface of the resultant from which the hard mask film pattern is removed, the surface of the interlayer insulating layer pattern 130a is formed by planarizing, for example, chemical mechanical polishing (CMP) process. Expose The active region of the semiconductor substrate 100 is set by the insulating layer 150.

The control gate electrode layer 160 is formed on the insulating layer 150 and the interlayer insulating layer pattern 130a. The control gate electrode layer 160 may include a metal layer or, in some cases, a double layer of a metal layer and a polysilicon layer. The metal layer may include a material film such as titanium nitride (TiN), tantalum nitride (TaN), or tantalum carbon nitride (TaCN).

On the other hand, when the hard mask layer (140 of FIG. 1) for device isolation in the X-axis direction is formed of a silicon nitride film, the control gate electrode layer 160 is a polysilicon layer, tungsten silicide after removing the hard mask layer The layer and the tungsten layer may be laminated. On the other hand, when the hard mask layer 140 is formed of a polysilicon layer, the control gate layer 160 may stack the tungsten silicide layer and the tungsten layer without removing the hard mask layer. The control gate electrode layer 160 is a layer for applying a bias of a predetermined size so that the charges of the semiconductor substrate 100 pass through the tunneling layer 110 and are stored in a floating gate electrode to be subsequently formed, and to the control gate electrode layer. Program and erase operations may be performed according to an applied bias. Next, for convenience of description, the semiconductor substrate is presented in a y-axis direction, for example, in a bit line direction.

When the semiconductor substrate is twisted in the y-axis direction, for example, in the bit line direction, as shown in FIG. 3B, the tunnel oxide layer pattern 110a, the buffer layer pattern 120a, and the interlayer insulating layer pattern 130a are formed on the semiconductor substrate 100. The control gate electrode layer 160 is sequentially formed.

Referring to FIG. 4, the control gate electrode layer, the interlayer insulating layer pattern, and the buffer layer pattern are selectively patterned in the y-axis direction, for example, in units of cells. Then, the control gate electrode layer, the interlayer insulating layer pattern, and the buffer layer pattern are separated in the Y-axis direction, for example, in the bit line direction, and separated in the cell unit. The control gate electrode layer pattern 161, the interlayer insulating layer pattern 131, and the buffer layer pattern 121 A) is formed. For example, in the case of a memory device having a floating gate electrode, charges stored in the floating gate including a conductive material such as a polysilicon layer may be moved by field differences. Therefore, in the case of the floating gate electrode, it is separated in the word line direction and the bit line direction to prevent the charge from being transferred between the memory cells.

Referring to FIG. 5, both sides of the buffer layer pattern 121 separated in units of cells are recessed inward. Then, recess regions are formed at both ends of the buffer layer pattern 121a recessed between the active region of the semiconductor substrate 100 and the interlayer insulating layer pattern 131. In this case, the depth in which the buffer layer pattern 121 is recessed may be recessed to remain within 1/2 of the line width of the interlayer insulating layer pattern.

Referring to FIG. 6, the floating gate electrode layer 170 is formed on the entire surface of the resultant recessed region. The floating gate electrode layer 170 may include a polysilicon layer, and may be formed using chemical vapor deposition (CVD) or atomic layer deposition (ALD). When the floating gate electrode layer 170 is formed using a chemical vapor deposition method or an atomic layer deposition method, the recess regions at both ends of the recessed buffer layer pattern 121a may be uniformly filled without a buried defect like a key hole. Can be.

Before forming the floating gate electrode layer 170, a capping layer, for example, a silicon nitride layer may be formed. The capping layer may be used as a barrier layer to protect the control gate electrode layer pattern 161 and the interlayer insulating layer pattern 131 in an etching process for selectively etching subsequent floating gate electrodes.

On the other hand, the floating gate electrode layer 170 may be formed with a keyhole, etc. according to the deposition method, but when the deposition method having excellent step coverage is used or the recess region is extended, the keyhole may be suppressed. In addition, even if a key hole or the like is generated, it does not affect the role of the floating gate electrode.

Referring to FIG. 7, the floating gate electrode layer is selectively etched so that the floating gate electrode layer remains only at both ends of the recessed buffer layer pattern 121a. Then, floating gate electrodes 171 separated by the buffer layer pattern 121a are formed at both ends of the recessed buffer layer pattern 121a. The floating gate electrodes 171 may be formed by performing a wet etching process or an isotropic dry etching process. In addition, the floating gate electrodes 171 may be oxidized so that the floating gate electrode layer remains only in the recess region. The process may be performed to oxidize the floating gate electrode layer other than the recess region.

In this case, after selectively etching the floating gate electrode layer, a reoxidation process may be performed to completely remove the floating gate electrode layer remaining on the sidewalls of the control gate electrode layer pattern and the interlayer insulating layer pattern.

According to an embodiment of the present invention, by forming the floating gate electrodes separated by the buffer layer pattern, the charges may be stored independently in each unit cell. For example, in the case of a floating gate electrode, the charge stored in the floating gate electrode is moved by the field difference. At this time, since the floating gate electrodes are separated by the buffer layer pattern, it is possible to prevent the charge from moving to each floating gate electrode. Accordingly, one unit cell operation may store charges independently in both storage regions while changing a source / drain direction, thereby implementing a dual bit memory device that may be implemented in a SONOS device.

As mentioned above, although preferred embodiment of this invention was described in detail, this invention is not limited to this, It is clear that the deformation | transformation and improvement are possible by the person of ordinary skill in the art within the technical idea of this invention. .

1 to 3A are cross-sectional views of a nonvolatile memory device having a floating gate electrode according to the present invention in a word line direction.

3B to 7 are cross-sectional views of a nonvolatile memory device having a floating gate electrode according to the present invention in a bit line direction.

Claims (11)

Forming a tunnel oxide layer, a buffer layer, an interlayer dielectric layer, and a hard mask layer pattern on the substrate; The hard mask layer pattern is used as an etch mask, and the exposed interlayer insulating layer, the buffer layer, the tunnel oxide layer, and the substrate are etched by a predetermined thickness to form a trench while forming a line-shaped interlayer insulating layer pattern, a buffer layer pattern, and a tunnel oxide layer pattern. Making; Selectively removing the hard mask layer pattern; Filling an insulating film in the trench from which the hard mask layer pattern is removed; Forming a control gate electrode layer on a resultant in which the insulating film is formed; Selectively patterning the control gate layer, the interlayer insulating layer pattern, and the buffer layer pattern in cell units; Recessing both sides of the buffer layer pattern separated by the cell in an inward direction; And Forming floating gate electrodes separated by the recessed buffer layer pattern on both sides of the recessed buffer layer pattern. The method of claim 1, The buffer layer is a method of manufacturing a nonvolatile memory device including an insulating film having a faster etching rate than the tunnel oxide layer and the insulating interlayer. The method of claim 2, And the insulating film is formed of a SOD film or a TEOS film deposited by a chemical vapor deposition method. The method of claim 1, The hard mask layer pattern is a method of manufacturing a nonvolatile memory device, which is formed by forming a polysilicon layer or a silicon nitride layer alone or by laminating them. The method of claim 1, The hard mask layer pattern may selectively expose the interlayer dielectric layer so that the tunnel oxide layer, the buffer layer, and the interlayer dielectric layer are separated in a word line direction. The method of claim 1, The patterning of the cell unit may be performed by patterning the cell in a direction orthogonal to a direction in which the interlayer insulating layer pattern, the buffer layer pattern, the tunnel oxide layer pattern, and the trench are formed. The method of claim 1, Forming the floating gate electrode, Forming a floating gate electrode layer on an entire surface of the resultant substrate on which the recessed buffer layer pattern is formed; And And performing an isotropic etching process so that the floating gate electrode layer remains on both sides of the recessed buffer layer pattern. The method of claim 7, wherein The floating gate electrode layer is a method of manufacturing a nonvolatile memory device to form a polysilicon layer using a chemical vapor deposition method or an atomic layer deposition method.  The method of claim 1, And forming a capping layer prior to forming the floating gate electrode.  The method of claim 9, The capping film is a manufacturing method of a nonvolatile memory device including a nitride film. The method of claim 1, And after the floating gate electrode layer is formed, performing an oxidation process.

Images