KR20090129626A - Memory-based storage device and block managin technique thereof - Google Patents

Abstract

PURPOSE: A memory-based storage device capable of enhancing reliability and a block management method thereof are provided to manage memory blocks of a flash memory based on a read history of the flash memory. CONSTITUTION: A memory controller fetchs a read history from a read history control table of a buffer memory(S300). The memory controller determines whether a refreshed memory block is found based the read history(S310). It is determined whether an error of the memory block is a physical defect or a defect caused from stress based on the read history of the flash memory(S320). The memory block is managed by processing the memory block into a bad block or using the memory block for a restricted purpose depending on a determination result(S330).

Description

MEMORY-BASED STORAGE DEVICE AND BLOCK MANAGIN TECHNIQUE THEREOF

The present invention relates to a storage device, and more particularly to a storage device based on a memory.

Error detection and correction techniques provide for efficient recovery of data that is corrupted due to various causes. For example, in the process of storing data in memory, data may be damaged due to various causes, and data may be damaged by perturbations of the data transmission channel through which data is transmitted from a source to a destination. Various methods have been proposed to detect and correct damaged data. Well-known error detection techniques include RS code (Reed-Solomon code), Hemming code (Hmming code), Bose-Chaudhuri-Hocquenghem (BCH) code, Cyclic Redundancy Code (CRC) code, and the like. Using these codes it is possible to find and correct corrupted data. In most applications where nonvolatile memory devices are used, data is stored in a flash memory device along with a value called error correcting code (ECC) (hereinafter referred to as ECC data). The ECC data is for correcting an error occurring during a read operation of the flash memory device, and the number of error bits that can be corrected using the ECC data is limited. Bit errors that occur during read operations can be corrected through error detection and correction techniques without additional remedies such as well known block replacement. In contrast, if a bit error occurring during a read operation is not correctable, data stored in the memory block including the bit error will be lost.

It is an object of the present invention to provide a memory based storage device and a block management technique thereof that can improve reliability.

Exemplary embodiments of the present invention provide a block management method of a memory-based storage device including a flash memory, in which the error of the memory block is caused by a physical defect based on a read history of the flash memory. Determining whether it is due to a defect due to knowledge or stress; And managing the memory block to be treated as a bad block or to be used for a limited purpose according to the determination result.

Other exemplary embodiments of the present invention include a flash memory; And a memory controller configured to manage the flash memory, wherein the memory controller provides a memory-based storage device that manages memory blocks of the flash memory based on a read history of the flash memory.

According to the present invention, the reliability of the memory-based storage device will be improved.

It is to be understood that both the foregoing general description and the following detailed description are exemplary, and that additional explanations of the claimed invention are provided.

Reference numerals are shown in detail in preferred embodiments of the invention, examples of which are shown in the reference figures. In any case, like reference numerals are used in the description and the drawings to refer to the same or like parts.

In the following, a memory system is used as an example for explaining the features and functions of the present invention. However, one of ordinary skill in the art will readily appreciate the other advantages and performances of the present invention in accordance with the teachings herein. The present invention may be implemented or applied through other embodiments as well. In addition, the detailed description may be modified or changed according to aspects and applications without departing from the scope, technical spirit and other objects of the present invention.

1 is a block diagram schematically illustrating a computing system according to example embodiments of the present invention, and FIG. 2 is a block diagram schematically illustrating the memory controller shown in FIG. 1 according to example embodiments of the present invention. .

Referring to FIG. 1, a computing system in accordance with example embodiments of the present invention will include a host 100 and a memory-based storage device 200. The memory-based storage device 200 may store data or output stored data according to a request of the host 100. The memory-based storage device 200 may be connected to a host through a serial AT attachment (SATA) interface, parallel AT attachment (PATA) interface, USB interface, SCSI interface, ESDI interface, IDE interface, MMC interface, SD interface, or the like. 100). However, it is apparent to those skilled in the art that the interface between the host 100 and the memory-based storage device 200 is not limited to those disclosed herein. For example, the host 100 and the memory-based storage device 200 may include a serial AT attachment (SATA) interface, a parallel AT attachment (PATA) interface, a USB interface, a SCSI interface, an ESDI interface, an IDE interface, an MMC interface, and an SD interface. And may communicate over at least two of the same.

The memory based storage device 200 may include a memory controller 220 and a storage medium 240. In an exemplary embodiment of the invention, the storage medium 240 will be comprised of flash memories. However, the storage medium 240 is not limited to the flash memory, it will be apparent to those of ordinary skill in the art. For example, nonvolatile memories such as phase change memory, magnetoresistive memory, and the like may be used as the storage medium 240. For convenience of description, an embodiment in which the storage medium 240 is implemented with only one flash memory is shown in FIG. 1. The memory controller 220 includes a host interface 222, a flash interface 223, a processing unit 224, a buffer memory 225, and an error check correction (ECC) circuit 226, as shown in FIG. 2. These configurations are well known to those who have acquired common knowledge in this area.

In the memory based storage device 200, the memory controller 220 may be configured to manage the flash memory 240. For example, the memory controller 220 may manage the read history of the flash memory 240 to improve the reliability of the memory-based storage device 200. The read history may include the number of error bits, error bit position, plane information, die information, refresh information, and the like. The memory controller 220 may manage memory blocks of the flash memory 240 based on the read history. For example, the memory controller 220 may manage the memory blocks of the flash memory 240 to be treated as a bad block or a limited purpose memory block based on the read history.

The memory-based storage device 200 according to the present invention has a read history of characteristics (eg, error bit number, error bit position, plane information, die information, refresh information, etc.) observed when a read operation is performed. It is possible to record information, determine memory blocks that are more likely to cause problems in the future as dangerous blocks based on the read history information, and manage risk blocks in a different group from general blocks, so that the risks of future operation of the memory-based storage device 200 are maintained. It will limit the use of blocks. Through such a management technique, it is possible to improve the reliability of the memory-based storage device 200.

According to a general memory management technique, a method of determining a block of a requested operation as a bad block based on whether the requested operation is successful through a result of a program or erase operation has been used. That is, whether to process the memory block as a bad block will be determined according to the result of the program or erase operation. As the miniaturization of circuit features (minimum feature sizes) of memory devices and miniaturization, the reliability of memory devices is deteriorated. Accordingly, there is a growing concern that data errors may occur during a read operation on a memory block in which a program or erase result is successful. Moreover, due to the continued use of memory devices, circuit defects (ie, physical defects) will increase as the memory devices age. That is, progressive defects will increase. In such a case, the probability that the data read from such a circuit defect, i.e., a memory block having a physical defect (e.g., called a 'danger block'), is impossible to correct an error may also be increased.

Therefore, the memory-based storage device 200 according to the exemplary embodiments of the present invention may prevent the degradation of reliability due to the dangerous block by managing the read history of the memory blocks, which will be described in detail below.

3 is a flowchart illustrating a read procedure of a memory-based storage device according to example embodiments. Hereinafter, a read procedure of a memory-based storage device according to exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

When a read operation is requested from the host 100, the memory controller 220 reads data from the flash memory 240 as a storage medium (S100). As is well known, the read data will be temporarily stored in the buffer memory 225 of the memory controller 220. At the same time, the memory controller 220 will check whether an error has occurred from the data read through the error checking and correction circuit 226 (S110). If it is determined that no error has occurred from the read data, the procedure goes to step S130. In contrast, if it is determined that an error has occurred from the read data, the procedure will proceed to step S120. In operation S120, the memory controller 220 may correct an error of data read through the error checking and correction circuit 226. In addition, the memory controller 220 may update the error history, that is, the read history, for the memory block from which data is read. Thereafter, the procedure will proceed to step S130. In operation S130, the read data may be transmitted to the external device, that is, the host 100 in operation S130.

Here, the memory controller 220 of the memory-based storage device 200 according to the present invention, as shown in Figure 1, a table for managing the read history information (hereinafter referred to as "read history table") 221 Will include. The read history table 221 may store error histories such as the number of error bits, error bit positions, plane information, and the like. Such read history table 221 will be stored in buffer memory 225. The read history table 221 is loaded from the flash memory 240 to the buffer memory 225 at power-up and will be backed up / restored to the flash memory 240 as needed.

4 is a flowchart illustrating a block management scheme of a memory-based storage device 200 according to exemplary embodiments of the present invention, and FIG. 5 conceptually illustrates a refresh operation according to exemplary embodiments of the present invention. Drawing.

Prior to the description, the memory-based storage device 200 according to exemplary embodiments of the present invention will be configured to refresh the memory block based on the read history. For example, the memory controller 220 may analyze the read history information (for example, the number of error bits) of the table 221 to control the refresh operation of the memory block. More specifically, in operation S200, the memory controller 220 may bring a read history of the read history table 221. Next, in step S210, the memory controller 220 may determine whether the number of error bits generated in any memory block exceeds a specific error bit number (or reference error bit number) based on the read history read. . That is, the memory controller 220 will determine whether there is a memory block (s) to be refreshed according to the test result. If it is determined that there is no memory block (s) to be refreshed, the procedure will end. If it is determined that there is a memory block (s) to be refreshed, the procedure will proceed to step S220.

In operation S220, the memory controller 220 may control the flash memory 240 to refresh the checked memory blocks. A more detailed description will be made with reference to FIG. 5. First, as shown in FIG. 5, the data of the memory block to be refreshed will be copied to the free block (1001). The memory block to be refreshed will then be erased (1002). Finally, the data stored in the free block will be copied to the memory block (1003). The memory block will be refreshed through the above-described processes. The free block will then be erased.

The gradual increase in the number of error bits means that read errors are more likely to occur. If a read error occurs, the data will be lost. Therefore, the loss of data can be prevented by refreshing the memory block depending on whether the number of error bits of the memory block exceeds the reference error bit number. Since the memory cells are stressed by the repetitive read process, the number of error bits can be increased. In other words, read / program / erase stresses can cause read errors. Hereinafter, the reading error due to stress is referred to as a 'stress-based defect'. Thus, a defect due to stress can be solved by refreshing the memory block. As a result, it is possible to improve the reliability of the memory-based storage device 200 by reducing read errors due to defects caused by stress.

FIG. 6 is a flowchart for describing a block management scheme of a memory-based storage device, according to another exemplary embodiment. Referring to FIG. Hereinafter, a block management scheme of a memory-based storage device according to other exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

The memory controller 220 may obtain a read history from the read history table 221 of the buffer memory 225 (S300). The memory controller 220 may determine whether there is a refreshed memory block based on the read read history (S310). If it is determined that there is no refreshed memory block, the procedure will end. If it is determined that there is a refreshed memory block, the procedure will proceed to step S320.

In operation S320, the memory controller 220 determines whether a previously generated error of the memory block is due to a physical defect or a defect due to stress based on a read history of the refreshed memory block. Will be determined. Defects due to stress can be resolved through the refresh operation, as described above. In contrast, if it is determined that the previously generated error of the refreshed memory block is due to a physical defect (eg, a progressive defect), the procedure will proceed to step S330. In operation S330, the memory controller 220 manages the mapping of the memory block (s) such that the use of the memory block (s) having a physical defect is limited. The procedure will then end.

In an exemplary embodiment, whether the refreshed memory block is a memory block having a physical defect may be determined based on the number of refreshes. For example, a memory block refreshed one or more times may be determined as a memory block having a physical defect.

As mentioned above, the memory blocks are refreshed under the assumption that errors continue to occur due to defects due to stress. However, in consideration of the error history of the read history information, the error may continue to occur due to the progressive defect rather than the defect due to the stress. If a memory block is refreshed even though the error is due to a progressive defect rather than a stress caused defect, all data stored in such a memory block may be lost in the future. That is, it is impossible to recover data stored in the memory block. Therefore, according to the block management scheme according to the present invention, the memory block (s) determined to have a physical defect is classified as a dangerous block in advance. Such dangerous blocks may be treated as bad blocks or to be used for purposes other than normal blocks. For example, assuming that the memory-based storage device 200 according to the present invention stores M-bit data, such dangerous blocks can be used to store N-bit data M <N. Or, read, erase, and program operations on such dangerous blocks will be limited. Depending on the error history, memory blocks that are circuitally and physically related to a particular block may also be treated as dangerous blocks.

7 is a flowchart illustrating a block management scheme of a memory-based storage device according to another exemplary embodiment of the present invention. The block management scheme shown in FIG. 7 is substantially the same as that shown in FIG. 6 except that the determination operation (step S310) of FIG. 6 is eliminated, and a description thereof will therefore be omitted. The removal of the determination operation (step S310) means that the dangerous block is not classified based on the refreshed memory block. In other words, classifying risk blocks based on read / error histories is based on whether a previously encountered error in the memory block is due to a progressive defect (i.e., a physical defect) or a defect due to stress. It is possible.

In exemplary embodiments of the present invention, a progressive defect (or a physical defect) may be determined based on error patterns prepared based on a test result of a flash memory. Alternatively, the progressive defect (or the physical defect) may be determined based on an error history including, for example, a phenomenon in which an error is repeatedly generated from the refreshed memory block.

In exemplary embodiments of the present invention, it is possible to determine a memory block as a dangerous block, that is, a memory block having a physical defect, based on the read history. For example, referring to the flowchart of FIG. 7, the memory controller 220 obtains a read history from the read history table 221 of the buffer memory 225 (S400), and the memory block is physically defective based on the read history. In step S410, the memory block having the physical defect is treated as a dangerous block according to the determination result (S420).

In the block management scheme of the present invention, a refresh operation on a memory block may not be preceded.

Flash memory devices are nonvolatile memory devices capable of retaining stored data even when power is cut off. With the growing use of mobile devices such as cellular phones, PDA digital cameras, portable game consoles, and MP3Ps, flash memory devices are becoming more widely used as code storage as well as data storage. Flash memory devices can also be used for home applications such as HDTV, DVD, routers, and GPS. A computing system including a memory system according to the present invention is schematically illustrated in FIG. 8. The computing system according to the present invention includes a microprocessor 2100 electrically connected to a bus 2001, a user interface 2200, a modem 2300 such as a baseband chipset, a memory controller 2400, and a flash memory. Device 2500. The memory controller 2400 corresponds to the memory controller shown in FIG. 1, and the flash memory device 2500 may be configured substantially the same as that shown in FIG. 1. The flash memory device 2500 may store, via the memory controller 2400, N-bit data (N is an integer greater than or equal to 1) to be processed / processed by the microprocessor 2100. When the computing system according to the present invention is a mobile device, a battery 2600 for supplying an operating voltage of the computing system will be further provided. Although not shown in the drawings, the computing system according to the present invention may further be provided with an application chipset, a camera image processor (CIS), a mobile DRAM, and the like. Self-explanatory to those who have learned. The memory controller 2400 and the flash memory device 2500 may configure, for example, an SSD (Solid State Drive / Disk) that uses a nonvolatile memory to store data. Exemplary SSDs are disclosed in US Patent Publication No. 2006-0152981, incorporated by reference in this field. Alternatively, the memory controller 2400 and the flash memory device 2500 may configure a memory card as a nonvolatile memory for storing data.

9 is a block diagram illustrating a memory based storage device according to other example embodiments of the inventive concepts.

The memory-based storage device illustrated in FIG. 9 is implemented such that the memory 3510 and the memory controller 3520 constitute a card 3530. For example, the card 3530 may be a memory card such as a flash memory card. That is, the card 3530 may be a card that meets certain industry standards for using electronic devices such as digital devices, cameras, personal computers, and the like. It will be appreciated that the memory controller 3520 may control the memory 3510 based on control signals received from another (eg, external) device by the card 3530.

10 is a block diagram illustrating a memory system including a memory based storage device according to other example embodiments of the inventive concepts.

The system shown in FIG. 10 represents a portable device 4000. The portable device 4000 may be an MP3 player, a video player, a combination video and audio player, and the like. As shown, portable device 4000 includes a memory 3510 and a memory controller 3520. Portable device 4000 may also include encoder and decoder 4610, presentation components 4620, and interface 4630.

Data processed by the encoder and decoder (EDC) 4610 (video, audio, etc.) may be input to and output from the memory 3510 through the memory controller 3520. As shown by the dashed lines in FIG. 9, data may be input directly from the EDC 4610 into the memory 3510 and / or output directly from the memory 3510 to the EDC 4610.

EDC 4610 may encode data for storage in memory 3510. For example, the EDC 4610 may perform MP3 encoding on the audio data for storage in the memory 3510. Alternatively, the EDC 4610 may perform MPEG encoding (eg, MPEG2, MPEG4, etc.) on the video data for storage in the memory 3510. In addition, the EDC 4610 may include a plurality of encoders for encoding different types of data according to different data formats. For example, the EDC 4610 may include an MP3 encoder for audio data and an MPEG encoder for video data.

EDC 4610 may decode the output from memory 3510. For example, the EDC 4610 may perform MP3 decoding on audio data output from the memory 3510. Alternatively, the EDC 4610 may perform MPEG decoding (eg, MPEG2, MPEG4, etc.) on the video data output from the memory 3510. In addition, the EDC 4610 may include a plurality of decoders for decoding different types of data according to different data formats. For example, the EDC 4610 may include an MP3 decoder for audio data and an MPEG decoder for video data.

It will also be appreciated that the EDC 4610 may include only decoders. For example, data that has already been encoded may be received by EDC 4610 and may be passed to memory controller 3520 and / or memory 3510.

The EDC 4610 may receive data for encoding or receive data that has already been encoded via the interface 4630. The interface 4630 can be in accordance with known standards (eg, firmware, USB, etc.). The interface 4630 may also include one or more interfaces. For example, the interface 4630 may include a firmware interface, a USB interface, and the like. Data from the memory 3510 may be output via the interface 4630.

Presentation components 4620 may present data to the user that is output from memory and / or decoded by EDC 4610. For example, presentation components 4620 may include a speaker jack for outputting audio data, a display screen for outputting video data, and the like.

The flash memory device and / or the memory controller according to the present invention may be mounted using various types of packages. For example, the flash memory device and / or the memory controller according to the present invention may be a package on package (PoP), ball grid arrays (BGAs), chip scale packages (CSPs), plastic leaded chip carrier (PLCC), plastic dual in- Line Package (PDIP), Die in Waffle Pack, Die in Wafer Form, Chip On Board (COB), Ceramic Dual In-Line Package (CERDIP), Plastic Metric Quad Flat Pack (MQFP), Thin Quad Flatpack (TQFP), Small Outline (SOIC), Shrink Small Outline Package (SSOP), Thin Small Outline (TSOP), Thin Quad Flatpack (TQFP), System In Package (SIP), Multi Chip Package (MCP), Wafer-level Fabricated Package (WFP), It can be implemented using packages such as Wafer-Level Processed Stack Package (WSP), or the like.

It will be apparent to those skilled in the art that the structure of the present invention may be variously modified or changed without departing from the scope or spirit of the present invention. In view of the foregoing, it is believed that the present invention includes modifications and variations of this invention provided they come within the scope of the following claims and their equivalents.

1 is a block diagram schematically illustrating a computing system in accordance with exemplary embodiments of the present invention.

FIG. 2 is a block diagram schematically illustrating a memory controller shown in FIG. 1 in accordance with exemplary embodiments of the present invention.

3 is a flowchart illustrating a read procedure of a memory-based storage device according to example embodiments.

4 is a flowchart for describing a block management scheme of a memory-based storage device according to example embodiments.

5 conceptually illustrates a refresh operation according to exemplary embodiments of the present invention.

FIG. 6 is a flowchart for describing a block management scheme of a memory-based storage device, according to another exemplary embodiment. Referring to FIG.

7 is a flowchart illustrating a block management scheme of a memory-based storage device according to another exemplary embodiment of the present invention.

8 is a block diagram schematically illustrating a computing system according to other exemplary embodiments of the present invention.

9 is a block diagram illustrating a memory based storage device according to other example embodiments of the inventive concepts.

10 is a block diagram illustrating a memory system including a memory based storage device according to other example embodiments of the inventive concepts.

Claims (17)

In a block management method of a memory-based storage device including flash memory: Determining whether an error of a memory block is due to a physical defect or a defect due to stress based on a read history of the flash memory; And And managing the memory block to be treated as a bad block or to be used for a limited purpose according to the determination result. The method of claim 1, And when it is determined that the error of the memory block is due to a physical defect, the memory block is treated as a bad block or used for a limited purpose. The method of claim 2, If the memory-based storage device stores M-bit data, the purpose of the memory block is limited to be used to store N-bit data. The method of claim 1, And when it is determined that the error of the memory block is due to a defect due to stress, the memory block is refreshed according to an error history. The method of claim 4, wherein And if the number of error bits of the memory block exceeds a reference error bit number, the memory block is refreshed. The method of claim 1, And the read history includes an error bit number, an error bit position, plane information, and refresh information for the memory block. The method of claim 1, The memory block is a block management method of a memory-based storage device, characterized in that the refreshed memory block. The method of claim 1, The method of claim 1, wherein the error of the memory block is determined by a physical defect based on the number of refreshes of the memory block. Flash memory; And A memory controller configured to manage the flash memory; And the memory controller manages memory blocks of the flash memory based on a read history of the flash memory. The method of claim 9, And the memory controller determines whether an error of each memory block is caused by a physical defect or a defect due to stress based on a read history of the flash memory. The method of claim 10, The memory controller is configured to process each memory block as a bad block or to be used for a limited purpose according to the determination result. The method of claim 11, And when the memory-based storage device stores M-bit data, the purpose of each memory block is restricted to be used to store N-bit data according to the determination result. The method of claim 10, And when it is determined that an error of each memory block is due to a defect due to stress, the memory controller refreshes the memory blocks according to an error history. The method of claim 9, And the read history comprises an error bit number, an error bit position, plane information, and refresh information for the memory blocks. The method of claim 9, The memory-based storage device is any one of a memory card, a portable storage device, and the SD. The method of claim 10, The operation of determining whether an error in each of the memory blocks is due to a physical defect or a defect due to stress is performed on the reclaimed memory blocks among the memory blocks. . The method of claim 10, Whether the error of the memory block is due to a physical defect is determined based on the number of refreshes of each memory block.

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