KR20090125969A - Semiconductor memory device having transistors of stacked structure - Google Patents

Abstract

PURPOSE: A semiconductor memory device having a laminating structure is provided to reduce a layout area additionally by supplying various connection structures between a driver and a sub word line and the suitable laminating structure of the sub word line or the drivers. CONSTITUTION: Sub word lines(SWL11~SWLin) of a memory cell array block(10) are arranged in one layer among at least two layers. Drivers(D) of a sub word line decoder(20) are arranged in one or more layers among at least two layers. The sub word lines of the memory cell array block are arranged in a first layer. The drivers of the sub word line driver are arranged in a second layer. The sub word lines of the memory cells are arranged in the second layer. The drivers of the sub word line driver are arranged in the first floor.

Description

Semiconductor memory device having transistors of stacked structure

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having transistors in a stacked structure.

In the case of manufacturing a semiconductor memory device with transistors having a horizontal structure, there is a limit in reducing the layout area. Accordingly, a technique of reducing layout area by stacking transistors having a horizontal structure has emerged.

Also, due to such efforts, techniques for stacking static memory cells, techniques for stacking peripheral circuits, and techniques for stacking flash memory cells have been introduced.

Techniques for laminating SRAM cells and techniques for laminating peripheral circuits are disclosed in Korean Patent Application Nos. 2004-61527 and 2005-38512, and a technique for laminating flash memory cells is disclosed in Korean Patent Application No. 2005-121779. It is published in the issue.

However, the above-mentioned documents do not disclose a connection structure between decoders for selecting and driving word lines.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor memory device having transistors in a stacked structure that discloses a connection structure between a word line to which memory cells are connected and a decoder in the stacked structure.

A first aspect of a semiconductor memory device having transistors having a stacked structure of the present invention for achieving the above object is a plurality of word lines, each having a plurality of at least one first transistor connected to each of the plurality of word lines And a word line decoder having a plurality of drivers for driving each of the plurality of word lines, wherein the plurality of word lines are disposed in a first layer, and the plurality of word lines are disposed in a first layer. Drivers are disposed on at least one second layer different from the first layer.

A second aspect of the semiconductor memory device having a stacked structure transistor of the present invention for achieving the above object is a plurality of memory having a plurality of word lines, at least one first transistor connected to each of the plurality of word lines And a word line decoder having a memory cell array block having cells, and a plurality of drivers for driving each of the plurality of word lines, wherein the plurality of word lines are disposed in a first layer, and the plurality of drivers Are dispersed in at least two or more second layers.

A third aspect of the semiconductor memory device having a stacked structure transistor of the present invention for achieving the above object is a plurality of memory having a plurality of word lines, at least one first transistor connected to each of the plurality of word lines A memory cell array block having cells, and a word line decoder having a plurality of drivers for driving each of the plurality of word lines, wherein the plurality of drivers are disposed in a first layer, and the plurality of word lines They are arranged in at least one second layer different from the first layer.

A fourth aspect of the semiconductor memory device having a stacked structure transistor of the present invention for achieving the above object is a plurality of memory having a plurality of word lines, at least one first transistor connected to each of the plurality of word lines A memory cell array block having cells, and a word line decoder having a plurality of drivers for driving each of the plurality of word lines, wherein the plurality of drivers are disposed in a first layer, and the plurality of word lines Are dispersed in at least two or more second layers.

A fifth aspect of the semiconductor memory device having a stacked structure transistor of the present invention for achieving the above object is a plurality of memory having a plurality of word lines, at least one first transistor connected to each of the plurality of word lines A memory cell array block having cells, and a word line decoder having a plurality of drivers for driving each of the plurality of word lines, wherein the plurality of word lines are distributed and stacked in at least two layers; The plurality of drivers connected to the plurality of word lines may be disposed in corresponding layers of the at least two layers.

Each of the plurality of drivers has at least two second transistors.

The plurality of memory cells are static memory cells, wherein the first transistor is disposed in the first layer, or the plurality of memory cells are nonvolatile memory cells, the first transistor is in the first layer It is characterized in that the arrangement.

Accordingly, the semiconductor memory device including the transistors of the stacked structure of the present invention can further reduce the layout area by presenting a suitable stacked structure of sub word lines (word lines) or drivers and various connection structures between the sub word lines and the drivers. Done.

Hereinafter, a semiconductor memory device including transistors having a stacked structure according to the present invention will be described with reference to the accompanying drawings.

FIG. 1 shows a configuration of an embodiment of a semiconductor memory device having transistors having a stacked structure of the present invention, and is comprised of a memory cell array block 10 and a sub word line decoder 20. As shown in FIG. The memory cell array block 10 includes sub memory cell array blocks SMCA1 to SMCAi including memory cells MC, and the memory cell array block 10 includes a plurality of memory cell array blocks (not shown). May be one block. The sub word line decoder 20 includes sub decoders SD1 to SDi including the drivers D, and the sub word line decoder 20 includes one sub word of a plurality of sub word line decoders (not shown). The sub word line decoder 20 may be disposed between each of the plurality of memory cell array blocks. In FIG. 1, MC may be a static memory cell, and D may be a decoder and / or a driver. Also, (BL1, BL1B) to (BLm, BLmB) select bit line pairs, MWL1 to MWLi select main word lines, (SWL11 to SWL1n) to (SWLi1 to SWLin) select sub word lines, and PXL1 to PXLn select Represent each signal line. In FIG. 1, the word line decoder 20 may be disposed in a memory cell array rather than a peripheral circuit.

In FIG. 1, each of the sub memory cell array blocks SMCA1 to SMCAi includes memory cells MC, and each of the sub decoders SD1 to SDi includes drivers D. In FIG. Each of the sub decoders SD1 to SDi may correspond to the corresponding sub word lines SWL11 to SDW in response to each of the selection signals applied to the corresponding main word lines MWL1 to MWLi and the selection signal lines PXL1 to PXLn. SWL1n) to (SWLi1 to SWLin) respectively. For example, the sub memory cell array block SMCA1 may correspond to the corresponding sub word lines SWL11 ˜ in response to each of the selection signals applied to the corresponding main word line MWL1 and the selection signal lines PXL1 to PXLn. SWL1n) is driven respectively.

In FIG. 1, transistors constituting the memory cell array 10 and / or the word line decoder 20 of the semiconductor memory device of the present invention may be disposed in at least two layers or more.

2A and 2B illustrate a configuration of each embodiment of a static memory cell and a driver of the semiconductor memory device of the present invention. The static memory cell MC of FIG. 2A includes pull-up transistors PU1 and PU2 and pull-down transistors PD1. , PD2, and transfer transistors T1 and T2, and the driver D of FIG. 2B includes a PMOS transistor P and an NMOS transistor N. In FIG. In FIG. 2B, PX represents a selection signal transmitted to the selection signal line, a is connected to the main word line MWL, and b is connected to the sub word line SWL.

The static memory cell MC of FIG. 2A has a latch configured by an inverter composed of transistors PU1 and PD1 and an inverter composed of transistors PU2 and PD2 to transmit data through the transfer transistors T1 and T2. Latch. The transfer transistors T1 and T2 are turned on in response to a signal applied to the sub word line SWL to transfer data between the node x and the bit line BL and between the node y and the inverting bit line BLB. Send it.

In response to the selection signal PX of the "high" level, the driver D of FIG. 2B turns on the NMOS transistor N to output a signal of the "low" level to the sub word line, and the selection signal of the "low" level. In response to (PX), the PMOS transistor P is turned on to output a signal transmitted to the main word line to the sub word line. The level of the "high" level signal transmitted to the main word line and the voltage Vpx applied to the substrate of the PMOS transistor P may be a high voltage level higher than the power supply voltage. That is, the driver D drives the sub word line by combining the selection signal PX and the signal transmitted to the main word line.

3A to 3C illustrate an arrangement of one embodiment of static memory cells and drivers of a semiconductor memory device of the present invention, in which the sub word lines SWL11 to SWLin of the memory cell array block 10 are arranged in at least one of two layers. It can be arranged in four layers, and shows the arrangement in the case where the drivers D of the sub word line decoder 20 are arranged in one or more layers of at least two layers. 3A and 3B, A represents a semiconductor memory device having transistors stacked on two layers, and B represents a semiconductor memory device having transistors stacked on three layers.

In FIG. 3A, in the case of the device of A, the sub word lines SWL11 to SWLin of the memory cell array block 10 are disposed on the first layer 1F, and the driver D of the sub word line driver 20 is shown. Are placed on the second floor 2F. Although not shown, the sub word lines SWL11 to SWLin of the memory cells MC are disposed on the second layer 2F, and the drivers D of the sub word line driver 20 are disposed on the first layer 1F. It may be.

In the case of the device of B, the sub word lines SWL11 to SWLin of the memory cell array block 10 are arranged on the first layer 1F, and the drivers D of the sub word line driver 20 are divided into two layers ( 2F) or 2F 3F. Although not shown, the sub word lines SWL11 to SWLin of the memory cells MC are disposed in one layer of the second layer 2F or the third layer 3F, and the drivers D are the sub word lines SWL11. ~ SWLin) may be disposed in a layer different from the layer disposed.

In FIG. 3B, in the case of the device of A, the sub word lines SWL11 to SWLin of the memory cell array block 10 are arranged on the first layer 1F, and the driver D of the sub word line driver 20 is shown. Are distributed on the first layer 1F and the second layer 2F, and each of the drivers D disposed on the first layer 1F and the second layer 2F corresponds to the sub word lines SWL11 to SWLin. Is connected to. Although not illustrated, the sub word lines SWL11 to SWLin may be disposed on the second layer 2F.

In the case of the device of B, the sub word lines SWL11 to SWLin of the memory cell array block 10 are arranged on the first layer 1F, and the drivers D of the sub word line driver 20 are arranged on the first layer ( 1F and 2F (or 1F and 3F) are distributed and arranged on 1F and 2F (2F) (or 1F and 3F) Each of the drivers D disposed at)) is connected to the corresponding sub word lines SWL11 to SWLin. Although not shown, the sub word lines SWL11 to SWLin may be disposed on the second layer 2F (or the third layer 3F).

In FIGS. 3A and 3B, for example, drivers D connected to odd-numbered sub word lines and drivers D connected to even-numbered sub word lines may be distributed in different layers.

In FIG. 3C, the sub word lines SWL11 to SWLin of the memory cell array block 10 are disposed on the first layer 1F, and the drivers 20 of the sub word line driver 20 are disposed on the first layer 1F and 2. The drivers D disposed on the layers 2F and 3F 3F and disposed on the first layer 1F, the second layer 2F, and the third layer 3F each correspond to a corresponding sub word line ( SWL11 ~ SWLin). For example, drivers D connected to 2n-1 (n is natural numbers) sub word lines are disposed on the first layer 1F, and drivers D connected to 2n th sub word lines are second layer. The drivers D disposed at 2F and connected to the 2n + 1th sub word lines may be disposed at the third layer 3F. Although not shown, the sub word lines SWL11 to SWLin may be disposed on the second layer 2F (or the third layer 3F).

4A to 4B show an arrangement of another embodiment of static memory cells and drivers of the semiconductor memory device of the present invention, in which the sub word lines SWL11 to SWLin of the memory cell array block 10 are arranged in at least two layers. The arrangement is shown in the case where the drivers D of the sub word line decoder 20 are arranged in one of at least two layers. In FIG. 4A, A represents a semiconductor memory device having transistors stacked in two layers, and B represents a semiconductor memory device including transistors stacked in three layers.

In FIG. 4A, in the case of the apparatus of A, the sub word lines SWL11, SWL12, ..., SWLin are distributed in one layer 1F and two layers 2F, and the drivers D are one. It is arrange | positioned at the layer 1F. Then, each of the sub word lines arranged in the first layer 1F is connected to the corresponding driver D arranged in the first layer 1F, and each of the sub word lines arranged in the second layer 2F is 1. It is connected to the corresponding driver D arranged in the layer 1F. Although not shown, the drivers D of the sub word line driver 20 may be disposed on the second layer 2F instead of the first layer 1F.

In the case of the apparatus of B, the sub word lines SWL11, SWL12, ..., SWLin are distributed in one layer 1F and three layers 3F, and the drivers D are disposed in the first layer 1F. Is placed on. Then, each of the sub word lines arranged in the first layer 1F is connected to the corresponding drivers D arranged in the first layer 1F, and each of the sub word lines arranged in the third layer 3F is 1. It is connected to the corresponding driver D arranged in the layer 1F. Although not shown, the drivers D of the sub word line driver 20 may be disposed on the second layer 2F instead of the first layer 1F, the third layer 3F, or the sub word lines. (SWL11, SWL12, ..., SWLin) may be disposed in two layers 2F and three layers 3F, or may be disposed in one layer 1F and two layers 2F.

In FIG. 4A, for example, odd sub word lines and even sub word lines may be distributed in different layers.

In FIG. 4B, the sub word lines SWL11, SWL12,..., SWLin are distributed in one layer 1F, two layers 2F, and three layers 3F, and the drivers D are 1. It is arrange | positioned at the layer 1F. Each of the sub word lines arranged in the first layer 1F is connected to the corresponding driver D arranged in the first layer 1F, and each of the sub word lines arranged in the second layer is connected to the first layer 1F. The sub-word lines arranged on the third layer 3F are connected to the corresponding drivers D arranged on the first layer 1F, respectively. For example, 2n-1 (n is a natural number) sub word lines are disposed on the first layer 1F, 2n sub word lines are disposed on the second layer 2F, and 2n + 1 sub word lines It may be disposed on the third layer 3F. Although not shown, the drivers D may be disposed not on the first floor 1F but on the second floor 2F, or on the third floor 3F.

FIG. 5 shows a layout of another embodiment of static memory cells and drivers of the semiconductor memory device of the present invention, wherein the memory cells MC of the memory cell array block 10 and the driver of the sub word line decoder 20 ( D) shows the arrangement in the case where they are arranged in two or more layers. In FIG. 5, A denotes a semiconductor memory device having transistors stacked on two layers, and B denotes a semiconductor memory device having transistors stacked on three layers.

In the case of the device of A, about half of the sub word lines SWL11 to SWLin are arranged in the first layer 1F, the remaining sub word lines are arranged in the second layer 2F, Drivers D connected to the sub word lines arranged on the first layer 1F are disposed on the first layer 1F, and drivers D connected to the sub word lines arranged on the second layer 2F are two. It is arrange | positioned at the layer 2F. For example, the odd-numbered sub word lines and the drivers D connected thereto are disposed on the first layer 1F, and the even-numbered sub word lines and the drivers D connected thereto are disposed on the second layer 2F. Can be.

In the case of the apparatus of B, it is shown that the sub word lines SWL11 to SWLin and the drivers D of the sub word line decoder 20 are arranged in three layers 1F, 2F, and 3F. For example, 2n-1 (n is a natural number) sub word lines and drivers D connected thereto are disposed on the first layer 1F, and 2n th sub word lines and drivers D connected thereto are provided. The 2n + 1th sub word lines and the drivers D connected thereto may be disposed on the second layer 2F and disposed on the third layer 3F.

In the above-described embodiments, the sub word lines of the memory cell array block 10 are formed by connecting the gate electrodes of the transfer transistors of the static memory cells with each other. In the case where one memory cell of the memory cell array block 10 is formed in two or more layers, it is preferable that a sub word line is formed in a layer in which the transfer transistors T1 and T2 are disposed. The PU1 and PU2 and the pull-down transistors PD1 and PD2 may be formed on the same layer and / or on a different layer from the transfer transistors T1 and T2.

In addition, when the sub word line decoder 20 of the semiconductor memory device of the above-described embodiments has an additional configuration other than the illustrated drivers D, other than the transistors P and N constituting the drivers D may be used. Transistors (not shown) for further configuration may be formed on the same layer and / or on a different layer from the layer in which the drivers D are disposed.

FIG. 6 illustrates a configuration of another embodiment of a semiconductor memory device having transistors having a stacked structure of the present invention, in which the memory cell array block 10 of FIG. 1 is a static memory cell array block composed of static memory cells MC. Alternatively, it is different from a nonvolatile memory cell array block composed of nonvolatile memory cells FMC. As shown in FIG. 1, the memory cell array block 10 includes sub memory cell array blocks SMCA1 to SMCAi, and the memory cell array block 10 includes one of a plurality of memory cell array blocks (not shown). It may be a block. The sub word line decoder 20 includes sub decoders SD1 to SDi, and may be one sub word line decoder among a plurality of sub word line decoders (not shown), and the sub word line decoder 20 includes a plurality of sub word line decoders 20. It may be disposed between each of the four memory cell array blocks. In FIG. 1, MC may be a static memory cell, and D may be a decoder and / or a driver. In addition, BL1 to BLm are bit lines, MWL1 to MWLi are main word lines, PXL1 to PXLn are select signal lines, SSL1 to SSLi are source select lines, and GSL1 to GSLi are drain select lines, and CSL1 to CSLi are Common source lines are shown. In FIG. 1, the word line decoder 20 may be disposed in a memory cell array rather than a peripheral circuit.

FIG. 7 shows the configuration of the embodiment of the driver shown in FIG. 6 and is composed of a PMOS transistor P and an NMOS transistor N. As shown in FIG. In FIG. 7, MWE represents a main word line signal transmitted to a main word line MWL, A is connected to a selection signal line, B is connected to a sub word line, and C is connected to a voltage line.

In Fig. 7, the NMOS transistor N is turned on in response to the "high" level main word line signal MWE to output a voltage transmitted through the node C to the sub word line, and the main at the "low" level. In response to the word signal MWE, the PMOS transistor P is turned on and outputs a signal having a level transmitted to the main word line to the sub word line. The level of the voltage Vpx applied to the substrate of the PMOS transistor P may be a high voltage level much higher than the power supply voltage. That is, the driver D drives the sub word line by combining the selection signal PX and the signal transmitted to the main word line.

Since the program operation, the erase operation, and the read operation of the nonvolatile memory cell shown in FIG. 6 are performed by a generally known operation method, description thereof will be omitted here.

Similarly to the semiconductor memory device of FIG. 1, the semiconductor memory device of FIG. 6 may have an arrangement between the memory cells and the drivers.

The transistors formed in the first layer of the semiconductor memory device of the above-described embodiments may be bulk transistors, and the transistors formed in the second and third layers may be thin film transistors.

In addition, the semiconductor memory device having the stacked structure of the above-described embodiments may be implemented by forming epitaxial layers using epitaxial growth techniques for transistors disposed in two and three layers, or using wafer bonding techniques. It can also be implemented by forming a.

In addition, the above-described embodiments have been described with an example in which the transistors constituting one driver D are disposed on the same layer when the sub word line decoder 20 is disposed on two or more layers. You may arrange | position to.

Although the above-described embodiments illustrate a semiconductor memory device having two or three transistors stacked, the present invention is also applicable to a semiconductor memory device having four or more stacked transistors.

1 is a block diagram of one embodiment of a semiconductor memory device of the present invention.

2A and 2B illustrate the configuration of each embodiment of a static memory cell and a driver of a semiconductor memory device having transistors having a stacked structure of the present invention.

3A-3C illustrate an arrangement of one embodiment of static memory cells and drivers of a semiconductor memory device of the present invention.

4A-4B show an arrangement of another embodiment of static memory cells and drivers of the semiconductor memory device of the present invention.

Fig. 5 shows the arrangement of another embodiment of static memory cells and drivers of the semiconductor memory device of the present invention.

Fig. 6 shows a configuration of another embodiment of a semiconductor memory device having transistors of the stacked structure of the present invention.

FIG. 7 shows a configuration of an embodiment of a driver shown in FIG.

Claims (20)

A memory cell array block including a plurality of word lines and a plurality of memory cells each having at least one first transistor connected to each of the plurality of word lines; And A word line decoder having a plurality of drivers for driving each of the plurality of word lines, And the plurality of word lines are disposed in a first layer, and the plurality of drivers are disposed in at least one second layer different from the first layer. The semiconductor memory device of claim 1, wherein each of the plurality of drivers includes at least two second transistors. The method of claim 1, wherein the plurality of memory cells A static memory cell, said static memory cell further comprising at least two second transistors, And the first transistor is disposed on the first layer, and the second transistors are disposed on at least one of the first layer and the second layer. The method of claim 1, wherein the plurality of memory cells A nonvolatile memory cell, And the first transistor is disposed in the first layer. A memory cell array block having a plurality of word lines and a plurality of memory cells having at least one first transistor connected to each of the plurality of word lines; And A word line decoder having a plurality of drivers for driving each of the plurality of word lines, And the plurality of word lines are disposed in a first layer, and the plurality of drivers are distributed in at least two or more second layers. 6. The method of claim 5, wherein each of the plurality of drivers has at least two second transistors, and wherein the at least two second transistors of each of the plurality of drivers are in the same layer of the at least two second layers. And a transistor having a stacked structure, wherein the semiconductor memory device is disposed. The method of claim 5, wherein the plurality of memory cells A static memory cell, said static memory cell further comprising at least two second transistors, And the first transistor is disposed on the first layer, and the second transistors are disposed on at least one of the first layer and the second layers. The method of claim 5, wherein the plurality of memory cells A nonvolatile memory cell, And the first transistor is disposed in the first layer. A memory cell array block having a plurality of word lines and a plurality of memory cells having at least one first transistor connected to each of the plurality of word lines; And A word line decoder having a plurality of drivers for driving each of the plurality of word lines, And the plurality of drivers are disposed in a first layer, and the plurality of word lines are disposed in at least one second layer different from the first layer. 10. The semiconductor memory device of claim 9, wherein each of the plurality of drivers includes at least two second transistors. The method of claim 9, wherein the plurality of memory cells A static memory cell, said static memory cell further comprising at least two second transistors, And the first transistor is disposed on the first layer, and the second transistors are disposed on at least one of the first layer and the second layer. The method of claim 9, wherein the plurality of memory cells A nonvolatile memory cell, And the first transistor is disposed in the first layer. A memory cell array block comprising a plurality of word lines and a plurality of memory cells having at least one first transistor connected to each of the plurality of word lines; And A word line decoder having a plurality of drivers for driving each of the plurality of word lines, And the plurality of drivers are disposed in a first layer, and the plurality of word lines are distributed in at least two or more second layers. The semiconductor memory device of claim 13, wherein each of the plurality of drivers includes at least two second transistors. The memory device of claim 13, wherein the plurality of memory cells A static memory cell, said static memory cell further comprising at least two second transistors, And the first transistor is disposed in the first layer, and the second transistors are disposed in at least one layer of the first layer and the second layers. The memory device of claim 13, wherein the plurality of memory cells A nonvolatile memory cell, And the first transistor is disposed in the first layer. A memory cell array block having a plurality of word lines and a plurality of memory cells having at least one first transistor connected to each of the plurality of word lines; And A word line decoder having a plurality of drivers for driving each of the plurality of word lines, Wherein the plurality of word lines are distributed and stacked in at least two layers, and the plurality of drivers connected to the plurality of word lines are disposed in corresponding layers of the at least two layers. A semiconductor memory device having transistors. 18. The semiconductor memory device of claim 17, wherein each of the plurality of drivers includes at least two second transistors. 18. The method of claim 17, wherein the plurality of memory cells A static memory cell, said static memory cell further comprising at least two second transistors, And the first transistor and the second transistor are disposed on at least one of the at least two layers. 18. The method of claim 17, wherein the plurality of memory cells A nonvolatile memory cell, And the first transistor is disposed in the first layer.

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