JP2009043414A - Semiconductor memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor memory device in which high speed operation can be performed by reducing load applied to a sub-word selection line when a sub-word driver arranged for each memory mat is driven. <P>SOLUTION: In a drive method of the sub-word driver operated by receiving a sub-word selection signal given through the sub-word selection line, the sub-word selection line is divided in accordance with the memory mat; polarization of the sub-word selection signal to a divided position and polarization from each divided position to each sub-word driver are reversed. The reversed sub-word selection signal is operated by each sub-word driver with a main word signal, and output as a sub-word drive signal. Circuit constitution can be simplified by providing commonly an inverter circuit reversing the main word signal for a plurality of sub-word drivers at a sub-word driver side. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor memory device having a configuration including a plurality of memory mats formed by dividing a memory array or a memory block, and a sub word driver (SWD) connected to each memory mat, and a sub word driver The present invention relates to a (SWD) drive system.

  Conventionally, as this type of semiconductor memory device, there is a dynamic RAM (hereinafter referred to as DRAM) as described in JP-A-9-36328. This DRAM has a configuration in which a storage area on a chip is divided into a plurality of memory blocks, and each memory block is divided into a plurality of memory mats. In this case, a plurality of memory cells are arranged in each memory mat. In such a DRAM, a sense amplifier section and a sub word driver (SWD) section are arranged around each memory mat. Among these, the sense amplifier section is arranged at a position where it can be connected to the column selection line and the bit line arranged in the column direction, while the SWD section is a position where it can be connected to the main word line and the sub word line arranged in the row direction. And is composed of a plurality of sub-word drivers. As described above, by providing the SWD portion, the storage area to be operated can be kept in as small a block as possible, power consumption can be reduced, and high-speed operation is also possible.

  Further, each SWD includes a plurality of sub word driver circuits, and each sub word driver circuit is connected to the main word line and the sub word line arranged in the row direction as described above, and extends from the sub word selection decoder. It is also connected to a selection line (hereinafter sometimes abbreviated as FX line). By selecting the main word line and the sub word selection line, the sub word line is selectively activated, and the memory corresponding to the sub word line is selected. The cell is activated.

  On the other hand, it has also been proposed to share a plurality of subword selection lines with a plurality of memory mats in this type of DRAM. In this case, sub word selection lines are arranged between two memory mat columns arranged at intervals in the column direction, and these sub word selection lines are divided in the column direction and arranged on both sides of the sub word selection lines. There is a case in which a driving method is adopted in which a driver is connected to a sub word driver corresponding to the memory mat and driven by a sub word selection signal on a sub word selection line. In this case, a sub word selection signal (FX signal) is sent from the sub word selection decoder to the sub word selection line.

  As described above, when the FX division driving method is employed, the number of memory mats selected by a single subword selection line increases as the capacity of the DRAM increases. Thus, as the number of memory mats increases, the number of subword driver circuits selected by the same subword selection line tends to increase dramatically.

  Conventionally, a driving method in which a sub-word selection signal (FXT) having a single polarity is sent from a sub-word selection decoder to each sub-word selection line is usually adopted. However, when such a driving method is adopted, when the memory mat increases, a delay occurs in operation between the sub word driver circuit near the sub word selection decoder and the sub word driver circuit located away from the sub word selection decoder. It was confirmed.

  On the other hand, a single polarity subword selection signal from the subword selection decoder is inverted every time it branches to each subword driver circuit, and both subword selection signals (FXT and FXB) having two positive and negative polarities are used, A split driving method for driving a sub word driver circuit has also been proposed.

  However, even if this divided drive method is adopted, the influence of wiring resistance and load capacitance cannot be ignored with an increase in storage capacity. According to the experiments by the present inventors, it has been found that the increase in the wiring resistance and the like is caused by an increase in the load on the FXB among the subword selection signals.

  An object of the present invention is to provide a semiconductor memory device capable of reducing the influence of an increase in wiring resistance and load capacitance caused by a sub word selection line even when the number of memory mats increases due to an increase in chip size and storage capacity. is there.

  Another object of the present invention is to provide a sub word driver circuit driving system capable of reducing a delay caused by a sub word line by reducing a load applied to the sub word selection line.

According to the first aspect of the present invention, a main word decoder that activates a predetermined main word selection signal based on a first address signal inputted from the outside, and a predetermined word based on a second address signal inputted from the outside. A sub word decoder for activating a sub word selection signal;
A sub word driver circuit that activates a corresponding sub word line; and the main word selection signal output from the main word decoder is inverted, and the main word is applied to a first sub word driver circuit group including a plurality of sub word driver circuits. A first inverter circuit for supplying an inverted signal of the selection signal, and the sub word driver circuit is configured to detect the main word selection signal when the supplied main word selection signal and the sub word selection signal are activated. A semiconductor memory device is obtained which is activated by the two-way logic level transition and the one-way logic level transition of the subword selection signal to activate the subword line.

According to the second aspect of the present invention, a main word decoder that activates a predetermined main word selection signal based on a first address signal inputted from the outside, and a predetermined word based on a second address signal inputted from the outside. A sub word decoder for activating a sub word selection signal;
A plurality of sub word driver circuits for activating the corresponding sub word lines respectively, and the main word selection signal output from the main word decoder is inverted, and the first sub word driver circuit group including the plurality of sub word driver circuits is A first inverter circuit that supplies an inverted signal of a main word selection signal and a second sub word driver circuit group including a plurality of sub word driver circuits by inverting the logic level of the sub word selection signal output by the sub word decoder. A second inverter circuit for supplying an inverted signal of the sub word decoder signal, and the sub word driver circuit is configured to activate the main word when the supplied main word selection signal and the sub word selection signal are activated. Two-way logic level transition of select signal Serial semiconductor memory device is obtained which is characterized by activating the word line direction of which is controlled by a logic level transition of the sub-word selection signal.

According to a third aspect of the present invention, a main word decoder that activates a predetermined main word selection signal based on a first address signal input from the outside;
A subword decoder for activating a predetermined subword selection signal based on a second address signal input from the outside, a subword driver circuit for activating a corresponding subword line,
A first inverter circuit that inverts the main word selection signal output from the main word decoder and supplies an inverted signal of the main word selection signal to a first subword driver circuit group including a plurality of subword driver circuits; The sub word driver circuit is controlled by the main word selection signal, an inverted signal of the main word selection signal, and one signal based on the sub word selection signal. .

  In the present invention, the subword selection signal is divided into FXB and FXT signals, and the circuit portion that is energized in the form of the FXB signal and the circuit portion that is energized in the form of the FXT signal are separated, and the load applied to each signal is distributed. Thus, a sub-word driver driving method capable of operating at high speed can be obtained by reducing the total load capacity and resistance. In addition, since the increase in load can be reduced according to the present invention, a semiconductor memory device that can cope with an increase in memory capacity and an increase in the number of divided arrays can be obtained.

  A semiconductor memory device to which the present invention can be applied will be described with reference to FIGS. In FIG. 1, a part of a DRAM including memory mats MM1 to MM28 arranged in two columns is shown as a semiconductor memory device. In the illustrated semiconductor memory device, 14 similar memory mats MM (that is, MM1 to MM14) are arranged in the arrangement direction of the illustrated memory mats MM1 to MM3. Another row of memory mats MM15 to MM28 are arranged in parallel. In FIG. 1, only the memory mats MM1 to MM3 are shown among these memory mats MM1 to MM28. Each of the memory mats MM1 to MM28 has a storage capacity of 256K bits. In this relation, each of the memory mats MM11 to MM28 has 512 sub word lines (SWL) extending in the row direction and 512 bit pair lines extending in the column direction. Each of the memory mats MM1 to MM28 is individually activated by a memory mat selection signal (not shown).

  Here, the illustrated semiconductor memory device includes an input / output circuit 51 connected to an input / output terminal DQ (4 bits), and a main amplifier 52 connected to the input / output circuit 51 via a global IO line. The amplifier 52 is connected to the sub-amplifier 53 via the main IO line. Further, column decoders (DEC1-3) are provided around the memory mats MM1 to MM3 so as to correspond to the memory mats MM1 to MM3, and column address signals Y0 to Y6 are provided to the columns DEC1-3. Is given. Further, each column DEC1-3 is connected to a sense amplifier unit SA1-3.

  In the illustrated example, each column DEC1-3 can select 128 YS lines. When one YS line is selected, four sense amplifiers are selected from each sense amplifier unit SA1-3. It will be in the state. As a result, of the 512 bit pair lines, four bit pair lines BL are connected to the main amplifier 53 via the sub amplifier 53. The sub-amplifiers connected to the sense amplifier units SA1, 2, 3 are also connected to the sub-amplifiers of the memory mat MM15 and the memory mats 16, 17 belonging to other columns not shown.

  On the other hand, in order to select 512 sub word lines (SWL) of each of the memory mats MM1 to MM14 and MM15 to 28, the illustrated semiconductor memory device includes a main word decoder (MWD) and two sub word decoders (SWDEC1 and SWDEC1). SWDEC2) is provided. The illustrated MWD is provided with 6 bits of X3 to X8 bits of the X address signal, while SWDEC1 and 2 are provided with 3 bits of X0 to X2 bits. In this configuration, the MWD is connected to the sub word drivers (SWD1 to SWD64) of each memory mat MM via 64 main word lines (MWL).

  In this case, each SWD 1 to 64 includes four sub word driver circuits, and each sub word driver circuit is selected by the output of the sub word decoder (SWD 1 or 2). That is, when one of the 64 MWLs is selected and activated by the MWD, one of the SWDs 1 to 64 is activated. At this time, SWDEC 1 or 2 activates one subword driver circuit in SWD 1 to 64 by X 0 to X 2.

  Specifically, SWDEC1 shown in the figure is connected to SWD1 to SWD1 of memory mat MM1 through four subword selection lines and four inverters. In this example, the four sub-word selection lines and the four inverters are also connected to SWD 1 to 64 of the corresponding memory mat MM15 (not shown) among the memory mats arranged in parallel with the memory mat MM1. Subword selection signals FXB0, FXB1, FXB2, FXB3 are output from SWDEC1 to the four subword selection lines, and these subword selection signals FXB0, FXB1, FXB2, FXB3 are in SWD in memory mat MM1 (or MM15). One of the four sub word driver circuits is activated. Subword selection signals FXB0, FXB1, FXB2, and FXB3 are also supplied to SWD1 to SWD1 provided between memory mats MM2 and MM3 and between memory mats MM16 and MM17 (not shown) via inverters, respectively. It is done.

  On the other hand, SWDEC2, which receives X0 to X2 and operates similarly to SWDEC1, is connected to SWD1 to 64 provided between memory mats MM1 and MM2 via a sub-word selection line and an inverter, and to memory mat MM3. It is also connected to SWD1 to SWD64 provided between MM4 (not shown). Subword selection signals FXB4 to FXB7 are output from SWDEC2 to the subword selection line, and supplied to SWD1 to SWD1 arranged alternately between the memory mats MM via an inverter.

  In other words, the sub-word selection line from SWDEC1 (or 2) is connected via an inverter to SWD1 to 64 arranged in every memory mat MM among SWD1 to 64 arranged between the memory mats. I understand that.

  In this configuration, eight subword driver circuits in two SWDs can be selected and driven by subword selection signals FX0 to FX7 generated by three bits of X0 to X2.

  Referring also to FIG. 2, the connection relationship between the SWD of FIG. 1 and the memory mat MM is shown in more detail. As shown in FIG. 2, the SWD1 arranged on the left side of the memory mat MM1 is supplied with the subword selection signals FXB0 to FXB3 inverted by the inverter as FXT0 to FXT3. On the other hand, the right side of the memory mat MM1, that is, SWD1 provided between the memory mats MM1 and MM2, is provided with FXT4 to FXT7 from the SWDEC2, and this SWD1 also provides the sub word line ( SWL) is selected. As a result, in response to the above-described FXT0-7, one of the sub word drive signals SWLT0-7 is activated by SWD1 arranged on both sides of the memory mat MM1.

  Referring to FIG. 3, a sub word driver (SWD) that can be used in the present invention will be described by taking SWD 1 shown in FIGS. 1 and 2 as an example. 3 includes four sub-word driver circuits 20a, 20b, 20c, and 20d arranged in the column direction of FIG. 1 and connected to the main word line 15 in common. In the illustrated example, a main word line selection signal MWLB is given on the main word line, and this main word line selection signal MWLB is supplied in common to the four sub word driver circuits 20a, b, c, d. This is supplied to an inverter circuit 25 provided in common to the four sub word driver circuits 20a, b, c, d. Therefore, the inverter circuit 25 has an input terminal to which the main word line selection signal MWLB is applied and an inverter output terminal connected to the sub word driver circuits 20a, b, c, and d.

  Here, each of the sub word driver circuits 20a, 20b, 20c, 20d receives the main word line selection signal MWLB and the sub word selection signals FXT0 to 3 and performs an operation of outputting the sub word drive signals SWLT0 to 3 on the sub word lines. Since each sub word driver circuit 20a, b, c, d has the same configuration and operation, the sub word driver circuit 20a will be described as an example here.

  As is apparent from the figure, the sub-word driver circuit 20a receives the main word line selection signal MWLB, the true main word line selection signal (MWLT) inverted by the inverter circuit 25, and the true sub-word selection signal FTX0. The sub-word drive signal SWLT0 is output to. Further, the sub-word driver circuit 20a has an internal inverter circuit section composed of an NMOS transistor 26 and a PMOS transistor 28, and a drive NMOS transistor 30 connected to the output terminal of the internal inverter circuit section.

  The internal inverter circuit is composed of CMOS transistors, that is, NMOS and PMOS transistors 26 and 28, and the gates and drains of both transistors are connected in common. Furthermore, the drain connected in common is connected to the output terminal of the sub word driver circuit 20a. Further, the true subword selection signal FXT0 is given to the source of the PMOS transistor 28, and the source of the NMOS transistor 26 is connected to the power supply terminal of Vss (ground potential).

  On the other hand, a true main word line selection signal MWLT is supplied to the gate of the drive NMOS transistor 30 from the output terminal of the inverter circuit 25, and its source is connected to the output terminal of the sub word driver circuit 20a. On the other hand, the drain of the drive NMOS transistor 30 is connected to the sub word selection line, and in this relation, the true sub word selection signal FXT0 is supplied to the drain of the drive NMOS transistor 30.

  Thus, each of the illustrated sub word driver circuits 20a to 20d is composed of three transistors, and the inverter circuit 25 is composed of two transistors similarly to the internal inverter circuit. The four sub word driver circuits 20a to 20d are provided in common. This is equivalent to the fact that each of the sub word driver circuits 20a to 20d is configured by 3.5 transistors. Therefore, the illustrated sub word driver circuits 20a to 20d are 3.5 transistor type sub word driver circuits. May be called.

  Next, the operation of the sub word driver circuit 20a shown in FIG. 3 will be described with reference to FIG. 4 as well. The main word line (SWDEC 1 or 2) shown in FIG. MWL) 15 is selected, and a low-level subword selection signal FXB0 is output from SWDEC1. In this state, as shown in FIG. 4, the main word line selection signal MWLB is at a low level, and the subword selection signal FXT0 that is the inverter output of FXB0 shown in FIG. 1 is at a high level. The same applies to the other subword selection signals FXB1 to FXB7. At this time, since the load applied to each of the sub word selection signals FXB0 to FXB7 is relatively small, the state transition of the subword selection signals FXB0 to FXB7 is performed at high speed.

  In accordance with the state transition of these subword selection signals FXB0 to FXB7, the inverters (see FIGS. 1 and 2) provided at the branch positions of the subword selection signals FXB0 to FXB7 also perform state transition at high speed, and are indicated by FXT0 in FIG. Thus, a high level true subword selection signal FXT0 is output.

  When the main word line selection signal MWLB becomes low level as shown in FIG. 4, the output of the inverter circuit 25 shown in FIG. 3 becomes high level, and the drive NMOS transistor 30 is turned on. On the other hand, since the low-level main word line selection signal MWLB is applied to the gates of the NMOS and PMOS transistors 26 and 28 constituting the internal inverter circuit, the PMOS transistor 28 is turned on. As described above, when the PMOS transistor 28 and the drive NMOS transistor 30 are turned on, a high-level sub-word drive signal SWLT0 is output on the sub-word line as shown in FIG.

  On the other hand, when the main word line selection signal MWLB is at the low level and the sub word selection signal FXT0 is at the low level, the drive NMOS transistor 30 is maintained in the off state, so that the sub word line is maintained at the low level.

  Further, when the main word line selection signal MWLB is at a high level and the sub word selection signal FXT0 is at a high level, the NMOS transistor 26 is turned on, and the output of the sub word driver circuit 20a is set to the ground potential (Vss). Become. Even if the main word line selection signal MWLB is at a high level and the sub word selection signal FXT0 is at a low level, the NMOS transistor 26 is turned on and the output of the sub word driver circuit 20a is maintained at the ground potential.

  As described above, the sub-word driver circuit 20a shown in FIG. 3 outputs the high-level sub-word drive signal SWLT0 only when the main word selection line and the sub-word selection line are selected. In the example described above, only FXT0 has been described. However, similar operations are performed for the other subword selection signals FXT1, FXT2, and FXT3, and the subword driver circuits 20a to 20d of SWD1 are selected and selectively driven by subwords. The signals SWLT1, 2, and 3 can be output onto the sub word selection line (SWL) of the memory mat.

  In the illustrated example, the inverter circuit is provided in common to the four sub word driver circuits, but may be provided in common to more sub word driver circuits.

  With reference to FIG. 5, an overall configuration of a semiconductor memory device including an SWD according to the present invention will be schematically described. In FIG. 5, for the sake of simplicity, the main word line selection signal MWL0 is shown, and only the portion related to the single subword selection signal FXB0 is shown in the subword selection signal. In this relation, the overall configuration of the memory mat related to the subword selection signal FXB0 is shown. Here, the direction of the main word line to which MWLB0 is applied is called the row direction, and along the main word line 15, one row (row) and 14 memory mats MM are arranged at intervals over two rows. ing. Numbers 1 to 28 are attached to the memory mat MM illustrated in this relation.

  As is apparent from a comparison of FIG. 5 with FIG. 1, the main word line selection signal MWLB0 is applied from the MWD to the memory mats MM1 to MM14 as shown in FIG. On the other hand, the subword selection signal FXB0 is output from the SWDEC1 and supplied to the subword drivers (SWD1a and SWD1b) of the memory mats MM1 and MM15 on both sides via the inverter 261, as in FIG. Similarly, the sub word selection signal FXB0 is supplied via the inverter 262 to the SWD 1c provided between the memory mats MM2 and MM3 and the SWD 1d provided between the memory mats MM16 and MM17. Similarly, sub word drivers SWD1e to SWD1p are provided between the memory mats or at the end of the memory mat, and the SWD1e to SWD1p are supplied with the sub word selection signal FXB0 in the form of FXT0 via the inverters 263 to 268. Have been supplied. Here, each of the sub word drivers SWD1a to SWD1p shown in FIG. 5 has the circuit configuration shown in FIG.

  In FIG. 5, only a single SWD1 of each memory mat MM is shown with a single subword selection line and a selection signal FXB0, but as shown in FIG. 1, the other subword selection signals FXB1 to FXB7 are shown. Since the SWD related to 1 has a similar connection relation, it is omitted here for the sake of simplification of the drawing.

  As shown in the figure, the subword selection line is connected to each SWD from SWDEC1 through inverters 261 to 268. That is, the sub-word selection line has a portion extending in parallel to the main word line (portion extending in the row direction) and a portion extending between each of the inverters 261 to 268 and the memory mat MM (column direction portion). ing. Further, the column direction portion of the sub word selection line is branched to both sides at the branch position with respect to SWD1. Thus, it can be seen that the illustrated sub word selection line 21 is divided in the extending direction of the main word line 15 (that is, the row direction) and further extends in the column direction.

  In the illustrated example, when the sub word selection signal FXB0 is supplied to the sub word selection line, the sub word selection signal FXB0 is inverted by the inverters 261 to 268 provided at the branch positions and is supplied to SWD1 as FXT0. As a result, the sub word selection signal represented by FXT0 is supplied to the two SWDs 1 in the memory mat MM pair.

  A subword selection signal represented by FXB0 flows in the row direction portion other than the division position of the subword selection line, while only an inverted subword selection signal represented by FXT0 is supplied to each SWD1 from the division position to the column direction. Has been. Therefore, in this example, only SWT1 is given FXT0, and FXB0 is not given. This means that only the FXB0 or FXT0 can share the load applied to each signal line as compared with the case where all the SWD1 are driven, and high-speed operation becomes possible.

  On the other hand, it is conceivable to drive each SWD 1a to 1p using both FXT0 and FXB0. However, supplying subword selection signals complementary to each SWD 1a to 1p complicates the wiring of these SWDs 1a to 1p. There is a drawback that it will. Further, when both FXT0 and FXB0 are used, one of the subword selection signals is supplied to each subword driver circuit via a wiring extending not only in the row direction but also in the column direction. As a result, the wiring for transmitting the subword selection signal becomes long, and the wiring resistance and load capacitance increase. This tendency becomes conspicuous as the memory size increases, so that it is expected to be a major factor that limits the chip size and the number of memory array divisions.

  In consideration of this, the sub word driver driving method according to the embodiment of the present invention shown in FIG. 5 uses both FXT0 and FXB0 as the sub word selection signals, and divides the driving portion by each signal. Yes. As a result, the load applied to FXT0 and FXB0 can be reduced.

  In the above description, only FXT0 and FXB0 have been described. However, the effect of the present invention is very great considering that the same circuit configuration is necessary for the other subword selection signals shown in FIG.

  Actually, in the example shown in FIG. 5, the capacitance value is less than half compared to the case where both FXT0 and FXB0 are used as subword selection signals in the semiconductor memory device having the same layout, specifically, It was found that the size can be reduced from about 3000 fF to about 1400 fF.

  Summarizing the characteristics of the above configuration, a plurality of sub word driver circuits (SWD) are arranged so as to divide the sub word selection lines. By connecting an inverter to each division position on the sub word selection line, the FXB sub word selection signal is converted into an FXT true sub word selection signal, and the true sub word selection signal is provided on both sides of the division position of the sub word line. Thus, the load applied to FXB and FXT can be reduced by dividing the subword selection line into a portion driven by the FXB subword selection signal and a portion driven by FXT.

It is a figure which shows partially the semiconductor memory device which can apply this invention. It is a figure for demonstrating a part of FIG. 1 in detail. FIG. 3 is a circuit diagram of a sub word driver (SWD) according to an embodiment of the present invention. FIG. 4 is a waveform diagram for explaining an operation of the sub word driver shown in FIG. 3. It is a figure which shows a part of layout of the semiconductor memory device which can apply the subword driver drive system based on one Embodiment of this invention.

Explanation of symbols

MWD Main word decoder SWDEC1, SWDEC2 Subword selection line decoder SWD1 to SWD64, SWD1a, SWD1p Subword driver MM1 to MM28 Memory mat 261 to 268 Inverter FXB0 to FXB7, FXT0 to FXT7 Subword selection signal MWLB Main wordline selection signal 26 NMOS transistor 28 PMOS Transistor 30 NMOS transistor

Claims (9)

A sub word driver circuit for activating the corresponding sub word line;
A first inverter circuit that inverts the main word selection signal output from the main word decoder and supplies an inverted signal of the main word selection signal to a first sub word driver circuit group including a plurality of sub word driver circuits. And comprising
When the supplied main word selection signal and the sub word selection signal are activated, the sub word driver circuit performs a two-way logic level transition of the main word selection signal and a one-way logic level transition of the sub word selection signal. To activate the sub-word line. A main word decoder for activating a predetermined main word selection signal based on a first address signal input from the outside;
A subword decoder for activating a predetermined subword selection signal based on a second address signal input from the outside;
A plurality of sub word driver circuits each activating a corresponding sub word line;
A first inverter circuit that inverts the main word selection signal output from the main word decoder and supplies an inverted signal of the main word selection signal to a first subword driver circuit group including a plurality of subword driver circuits; ,
A second inverter circuit that inverts a logic level of the subword selection signal output from the subword decoder and supplies an inverted signal of the subword decoder signal to a second subword driver circuit group including a plurality of the subword driver circuits; With
When the supplied main word selection signal and the sub word selection signal are activated, the sub word driver circuit performs a two-way logic level transition of the main word selection signal and a one-way logic level transition of the sub word selection signal. To activate the sub-word line. The sub word driver circuit includes:
A P-conductivity type MOS transistor and a first N-conductivity type MOS transistor that are connected in series between a supply line of an inverted signal of the sub-word selection signal and a reference potential line, and that receive the main word selection signal as a control electrode;
The main word selection signal is connected between a first connection portion to which the P conductivity type MOS transistor and the first N conductivity type MOS transistor are connected and a supply line of the inverted sub word selection signal. A second N-conductivity type MOS transistor having an inverted signal as a control electrode input,
The semiconductor memory device according to claim 2, wherein the sub word line is connected to the first connection portion. As a supply line for supplying an inverted signal of the subword selection signal from the subword decoder to the subword driver circuit via the second inverter circuit, a first supply line and a second supply line are provided.
The first supply line extends in a first direction;
The second supply line extends in a second direction orthogonal to the first supply line;
The semiconductor memory device according to claim 2, wherein the second inverter circuit is disposed on the second supply line.   The semiconductor memory device according to claim 4, wherein the first supply line extends in a row direction. 6. The method according to claim 4, further comprising a plurality of memory mats each including a plurality of memory cells and a plurality of the sub word lines.
Each of the memory mats includes a plurality of the sub word driver circuits,
The plurality of memory mats are arranged in two rows in the row direction,
The first supply line is disposed between the memory mat columns disposed in the two columns;
The semiconductor memory, wherein the second supply line is configured to supply an inverted signal of the subword selection signal to the plurality of subword driver circuits provided in the memory mats on both sides of the first supply line. apparatus.   The semiconductor memory device according to claim 1, wherein the first sub-word driver circuit group includes four sub-word circuits. A main word decoder for activating a predetermined main word selection signal based on a first address signal input from the outside;
A subword decoder for activating a predetermined subword selection signal based on a second address signal input from the outside;
A sub word driver circuit for activating the corresponding sub word line;
A first inverter circuit that inverts the main word selection signal output from the main word decoder and supplies an inverted signal of the main word selection signal to a first subword driver circuit group including a plurality of subword driver circuits; With
The semiconductor memory device, wherein the sub word driver circuit is controlled by the main word selection signal, an inverted signal of the main word selection signal, and one signal based on the sub word selection signal.   9. The semiconductor memory device according to claim 8, wherein one signal based on the subword selection signal is an inverted signal of the subword selection signal.

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