KR100403344B1 - Semiconductor memory device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device for inputting and outputting a large number of data, and more particularly, to a semiconductor memory device configured to be easily connected to the outside without increasing an area in a memory cell array. The semiconductor memory device according to the present invention has a memory including a plurality of sense amplifier columns arranged in a vertical direction, a plurality of sub word driver rows arranged in a horizontal direction, and a cross area portion in a portion where the sense amplifier columns and the sub word driver rows overlap. A cell array unit, a plurality of main word driver units horizontally disposed at a lower end of the memory cell array unit, and a plurality of column decoder units disposed in a vertical direction on one side of the memory cell array unit, and in the memory cell array unit A column select signal line for controlling a switching transistor connecting a sense amplifier to a local input / output line is connected to the column decoder in the row direction, and a word line boosting signal line for enabling a word line; Supply power to the sense amplifier. The sense amplifier enable signal line is the column select sinhogwa are arranged in the same direction, the plurality of main one by one enables the word driver, and the remaining 2 ^m-bit address to the column decoder section with the sense amplifier enable signal lines and the In order to select a word line boosting signal line, a sense amplifier region of one column decoder in one address state is enabled at the same time so that input / output signals of each sense amplifier column are simultaneously connected to the outside of the array.

Description

Semiconductor Memory Device {SEMICONDUCTOR MEMORY DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a semiconductor memory device that inputs and outputs a large number of data, and more particularly, to a semiconductor memory device in which a plurality of data can be easily connected to the outside without increasing an area in a memory cell array.

1A and 1B are a configuration and a detailed view of a semiconductor memory device according to the prior art.

In FIG. 1A, a main word driver (MWD) 2 is disposed in a horizontal direction at the bottom of the cell array block 1, and m column decoders YDEC 3 are cell array blocks. It is a structure arrange | positioned at the right side of (1) in a vertical direction.

The cell array block 1 is divided into a plurality of sense amplifier (SA) columns 4 in the vertical direction and sub word driver (SWD) rows 5 in the horizontal direction.

A portion where the sense amplifier column 4 and the sub word driver row 5 overlap is a cross area 6. In each sense amplifier row 4, a local input / output line (LIO line) 7 of m x n bits is wired.

First, the operation of FIG. 1A is as follows. In general DRAM operation, one of a plurality of word lines is enabled by decoding of a row address, and then both sense amplifier columns of a block to which the enabled word lines belong are Able to be. When multiple word lines are enabled, so many sense amplifiers must be enabled, resulting in high power consumption.

Therefore, it is common to enable one or a few word lines. The above operation will be described with reference to FIG. 1B. In the main word driver 2, one main word line MWLBi of the plurality of main word lines MWLB is transitioned from 'high' to 'low'. At this time, the other main word lines MWLB remain 'high'. The selected main word line MWLBi is connected to the sub word drivers SWD. At this time, one of the word line boosting (FXBi <0: 7>) signals connected to the block having the selected main word line (MWLBi) is enabled 'low' by address decoding and the remaining 7 bits remain 'high'. . Therefore, one of the sub word lines SWL of the sub word driver SWD is enabled from 'low' to 'high' by the combination of the main word line MWLB and the word line boosting signal FXBi. When the sub word line SWL is selected and enabled, pull-down signals SANi and SANj for enabling the sense amplifier column are enabled from 'low' to 'high', and the pull-up signals SAPi and SAPj are also ' Enabled from 'low' to 'high'. At this time, the pull-up signals SAPi and SAPj are enabled with a voltage higher than the power supply voltage Vdd. The above signals are only enabled for those whose word lines are connected to both sense amplifier columns of the selected block and the signals connected to the other columns remain disabled. This block selection is made possible by block decoding of row addresses. At this time, the control signals SHRi and SHLj connected to the selected sense amplifier column are also enabled from 'low' to 'high' so that the switch connecting the sense amplifier and the bit line pair is turned on. do. The applied pull-down signals SANi and SANj and the pull-up signals SAPi and SAPj are connected to the gates of the NMOS transistors in the respective cross area parts C1 to C4 to be turned on. At this time, the pull-down power supply nodes CSNi and CSNj of each sense amplifier are driven to the ground voltage Vss, and the pull-up power supply nodes CSPi and CSPj are driven to the power supply voltage Vdd.

Meanwhile, since the control signals SHLi and SHLRj operate when another block is selected, the control signals SHLi and SHLRj remain 'low'. When one sub word line SWL is selected and enabled, data of a memory cell is transferred to one line of a bit line pair, causing a slight voltage difference in the bit line pair. At this time, when the pull-down power node (CSNi, CSNj) and the pull-up power node (CSPi, CSPj) begins to charge to the ground voltage (Vss) and the power supply voltage (Vdd), respectively, the slight voltage difference caused by the bit line pair by the sense amplifier It is amplified to charge the ground voltage (Vss) or the supply voltage (Vdd) level to each bit line. The same happens for all bit lines in the selected block.

After this operation, a plurality of column select (Y select) lines are selected by the decoding operation of the column address. The reason for selecting a plurality of column select lines is to connect a large number of input / output (I / O) to the outside at the same time. One column line in the plurality of column decoder blocks is enabled. FIG. 1B shows that the column select line YS0 is selected in the column decoder 0 block.

As described above, after the sub word line SWL and the sense amplifier SA are operated, if the column select line YS0 is enabled from 'low' to 'high', four of the sense amplifiers of the selected sense amplifier column block are enabled. Connected to the sense amplifier. Each sense amplifier has a column switch consisting of two NMOS transistors that connect a bit line pair and a local input / output (LIO) pair. That is, the column select line YSO is connected to the gates of the column switches, and the column select line YS0 is enabled from 'low' to 'high' to turn on the column switches. Thus, the data amplified by the sense amplifier can be connected to the local input / output 0,1,2,3 pairs for read operation, or externally driven data can be sensed with the local input / output pairs. The column switches of the amplifier allow write operations to invert the data of the bitline pair.

As shown in FIG. 1B, in the structure of inputting and outputting four data per column selection (YS) line, if only one column selection (YS) line is enabled in the entire block of FIG. 1A, only four data may be connected to the outside of the array. It becomes impossible. Therefore, by enabling a plurality of column selection (YS) lines in a plurality of column decoder blocks, the local input / output lines selected by each column selection (YS) line are wired in the sense amplifier column as shown in FIGS. 1A and 1B. do. Therefore, the number of local input / output lines that should be wired to every sense amplifier column is as follows.

Bit pair of local input / output (LIO) = m × (n / 2) bit pair

Here, m is the number of column decoder blocks (the number of column selections (YS) enabled), and n is the number of bits of data selected by one sub word line (SWL) and one column selection (YS). .

2A and 2B illustrate a configuration and a detailed view of another semiconductor memory device according to the related art.

In the configuration of FIG. 2A, m column decoders (YDECs) 13 are disposed in the horizontal direction at the lower end of the array 11, and a main word driver (MWD) 12 is disposed in the vertical direction at the right end of the array 11. . The array 11 is divided into a sense amplifier (SA) row 14 and a sub word driver unit (SWD) column 15 arranged in a horizontal direction, and the sense amplifier row 14 and the sub word driver unit column 15 This intersecting area becomes the cross area portion 16. In each sense amplifier row 14, n / 2-bit local input / output (LIO) lines are arranged, and in each sub-word driver column 15, n / 2-bit main input / output (Main input) / output: MIO) line is placed.

In each cross area portion 16, an input / output switch (IO SW) for connecting a local input / output (LIO) line and a main input / output (MIO) line is disposed.

As shown in Figs. 2A and 2B, a plurality of column decoders YDEC are horizontally arranged at the bottom and the main word driver MWD is vertically arranged at the left end. The operation of the main word driver MWD and the column selection YS are the same as those of FIGS. 1A and 1B. However, the structure of the array is rotated 90 degrees. A difference from FIGS. 1A and 1B is that a local input / output (LIO) line is divided into an area that each column decoder block is responsible for in a sense amplifier (SA) row.

In FIG. 2A, when the column decoder YDECi is in charge of two blocks, the local input / output (LIO) line is also separated and wired to a sense amplifier SA row across the two blocks. The separated local input / output line pairs are then connected to an IO switch pair in the cross area as shown in FIG. 2B. In addition, the input / output switches connect the main input / output (MIO) lines which are wired to the sub word driver unit (SWD) columns so that data is connected to the outside of the array in the vertical direction.

The input / output switch is controlled by the bit line equalizing signal BLEQi, j and the bit line equalizing signal BLEQBi, j. The bit line equalizing signal BLEQi, j, which is connected to both sense amplifier columns of the selected block of the word line WL, is enabled from 'low' to 'high', and the bit line equalizing signal BLEQBi, j is 'high'. Enabled to Low. The bit line equalizing signal BLEQ and the bit line equalizing signal BLEQB connected to the other sense amplifier columns remain disabled. Therefore, the input / output switches of the cross area portion of the enabled area are all turned on to connect the local input / output line pairs and the main input / output line pairs.

As shown in FIG. 2B, four main inputs / outputs per column decoder block when one column selection YS selects four data and one column selection YS is enabled in each column decoder block. MIO) can finally be connected outside the array.

The difference between FIG. 1B and FIG. 2B is that in FIG. 1B, many local input / output (LIO) wirings are required for the sense amplifier column, but in FIG. 2B, only the number of data selected by one column selection (YS) is required. However, in FIG. 2B, an input / output switch must be disposed in the cross area portion.

The conventional semiconductor memory device having the above configuration has the following problems.

First, a semiconductor memory device having an array structure as shown in FIGS. 1A and 1B requires a large number of local input / output wires in a sense amplifier column. In particular, when a large number of inputs / outputs are connected to the outside of the array, a large number of local inputs / outputs must be wired to each sense amplifier row, thereby increasing the area of the sense amplifier row and adversely affecting chip size. In addition, such a structure has a problem in that when the plurality of word lines are selected to configure the input / output IO, the number of sense amplifier columns that are enabled at the same time increases, thereby greatly increasing power consumption.

On the other hand, in the semiconductor memory device having the array structure as shown in Figs. 2A and 2B, since the input / output switch must be disposed in the cross area, the transistors driving the sense amplifier power supply are relatively small, so that the sense amplifier SA is reduced. The delay of the amplification operation (delay) can cause a degradation of the chip performance. When the transistors for driving the sense amplifier (SA) power supply are the same as those of FIG. 1B, the area of the cross area is increased, thereby increasing the chip size.

Accordingly, the present invention has been made to solve the above problems, and an object of the present invention is to provide a semiconductor memory device configured to be easily connected to the outside without increasing the area of a plurality of data in the memory cell array.

1A and 1B illustrate a configuration and a detailed view of a semiconductor memory device according to the related art.

2A and 2B show a configuration and a detailed view of another semiconductor memory device according to the related art.

3A and 3B show a configuration and a detailed view of a semiconductor memory device according to the present invention.

Explanation of symbols on the main parts of the drawings

21: memory cell array portion 22: main word driver portion

23: column decoder unit 24: sense amplifier unit

25: sub word driver portion 26: cross area portion

In order to achieve the above object, a semiconductor memory device according to the present invention has a plurality of sense amplifier columns arranged in a vertical direction and a plurality of sub word driver rows arranged in a horizontal direction, and a portion where the sense amplifier columns and the sub word driver rows overlap. A memory cell array unit including a cross area unit, a plurality of main word driver units horizontally disposed at a lower end of the memory cell array unit, and a plurality of column decoder units disposed in a vertical direction on one side of the memory cell array unit, and In the memory cell array unit, a column select signal line for controlling a switching transistor that connects a sense amplifier and a local input / output line is connected to the column decoder unit in the row direction, and the word line enables the word line. Boost signal line and the sense amplifier A is the enable signal line sense amplifiers arranged in the same direction as the column select sinhogwa that is supplied, and the plurality of main enabled the word driver, one and the remaining 2 ^m-bit address to enable the column decoder and the sense amplifier Used to select the signal line and the word line boosting signal line, the sense amplifier area of one column decoder in one address state is enabled at the same time so that input / output signals of each sense amplifier column are simultaneously connected to the outside of the array. It features.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

In addition, in all the drawings for demonstrating an embodiment, the thing with the same function uses the same code | symbol, and the repeated description is abbreviate | omitted.

3A and 3B show a configuration and a detailed view of a semiconductor memory device according to the present invention.

In FIG. 3A, m main word driver units (MWD) 22 are horizontally disposed at the lower end of the memory cell array unit 21, and m column decoder units (YDEC) 23 are arranged in the vertical direction. It is arrange | positioned at the right side of the part 21.

In the memory cell array unit 21, a plurality of sense amplifier columns 24 are disposed in a vertical direction, and a plurality of sub word driver rows 25 are disposed in a horizontal direction, and the sense amplifier columns 24 and the sub words are arranged in the memory cell array unit 21. The cross area portion 26 is formed at the portion where the driver rows 25 overlap.

In the memory cell array unit 21, as shown in FIG. 3B, a column select (YS) signal line for controlling a switching transistor connecting a sense amplifier and a local input / output (LIO) line is provided in the row. Is connected to the column decoder 23 in a direction, and a word line boosting (FXB) signal line for enabling a word line and a sense amplifier enable signal line (SAN, SAP) for supplying power to the sense amplifier. The column select signal YS is arranged in the same direction.

The semiconductor memory device of the present invention having the above structure is operated as follows.

First, one main word line MWLB is selected and enabled by row address decoding in the main word driver MWDi. When each main word driver MWD covers two or more columns as shown in FIG. 3A, the control signals SHL / Ri of the block in which the main word line MWLB is enabled are enabled. In Fig. 3B, for example, control signals SHRi and SHLj for separating the bit lines are enabled, and control signals SHLi and SHRj remain disabled. The above operation is performed in the same manner in each main word driver MWD.

In addition, since m main word lines MWD are divided into m and m main word lines MWLB are simultaneously enabled, a row address of 2 ^m bits remains. This extra address is used to select the m column decoders 23. In FIG. 3B, the word line boosting signal lines FXB0 and 1 and the sense amplifier enable signal lines SAN0 and SAP0 are selected by row addresses.

Accordingly, only one column decoder YDEC and the word line boosting signal line FXB, the sense amplifier pull-down signal SAN, and the pull-up signal SAP disposed in the column decoder YDEC are enabled in one address state. do. The word line boosting signal line FXB enables the even-numbered sub-word driver or the odd-bit is enabled when the sub-word driver SWD enables the odd bits (1, 3, 5 or 7). will be. In the cross area portion, the CSN / CSP driving driver, which is a sense amplifier power supply node, is arranged as in the prior art. The CSN and CSP wiring of each sense amplifier row is separated by the area covered by the column decoder block.

It is shown by CSN0 and CSP0 wiring of FIG. 3B. This separation enables the word lines to prevent both sense amplifier rows from being enabled. In addition, since only one column line is selected in one state, there is no need for local input / output (LIO) wiring selected by another column select line as shown in FIG. 1 in the sense amplifier column. 3b shows that only two bits of local input / output (LIO) are wired to each sense amplifier column. Other read and write operations are the same as in the prior art.

As described above, according to the semiconductor memory device according to the present invention, a large number of local input / output lines wired to a sense amplifier row can be reduced by 1 / m, and an IO switch is disposed in the cross area compared to the prior art. Since it is not necessary, the driving transistor of the sense amplifier power node can be made large. While maintaining this advantage, the same number of inputs / outputs (IO) as in the prior art can be connected outside the array.

In addition, preferred embodiments of the present invention are disclosed for the purpose of illustration, those skilled in the art will be able to various modifications, changes, additions, etc. within the spirit and scope of the present invention, these modifications and changes should be seen as belonging to the following claims. something to do.

Claims (8)

In a semiconductor memory device, A memory cell array unit including a plurality of sub-word driver rows arranged in a vertical direction and a plurality of sub-word driver rows arranged in a horizontal direction, and a cross-area unit at a portion where the sense-amplifier columns and the sub-word driver rows overlap; A plurality of main word driver units horizontally disposed at a lower end of the memory cell array unit; A plurality of column decoders disposed in a vertical direction on one side of the memory cell array unit, In the memory cell array unit, a column select signal line for controlling a switching transistor connecting a sense amplifier and a local input / output line is connected to the column decoder unit in the row direction, and a word for enabling a word line. A line boosting signal line and a sense amplifier enable signal line for supplying power to the sense amplifier are arranged in the same direction as the column selection signal. By enabling the plurality of main word drivers one by one, the remaining 2 ^m bits of addresses are used to select the column decoder unit, the sense amplifier enable signal line, and the word line boosting signal line. And a sense amplifier region which is in charge of a decoder is simultaneously enabled so that input / output signals of each sense amplifier string are simultaneously connected to the outside of the array. The method of claim 1, wherein the sense amplifier string, A sense amplifier for sensing the potential of the bit line pair, A switching transistor connecting the sense amplifier with a local input / output line; First and second isolation transistors, each configured on both sides of the sense amplifier, for separating the pair of bit lines; And a precharge transistor for precharging the pair of bit lines. The method of claim 2, And the sense amplifier is a sense amplifier configured in a cross-coupled latch type. The method of claim 2, And the switching transistor is composed of an NMOS transistor controlled by the column select signal line. The method of claim 2, And the first and second isolation transistors each comprise an NMOS transistor. The method of claim 2, And the precharge transistor comprises an NMOS transistor controlled by a bit line equalizing signal. The method of claim 1, And the cross-area portion includes pull-up and pull-down transistors for respectively supplying a power supply voltage and a ground voltage to the sense amplifier by the sense amplifier enable signal line. The method of claim 7, wherein And the pull-up and pull-down transistors each comprise an NMOS transistor.