KR20090124426A - Method for formating of semiconductor device - Google Patents
Method for formating of semiconductor device Download PDFInfo
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- KR20090124426A KR20090124426A KR1020080050641A KR20080050641A KR20090124426A KR 20090124426 A KR20090124426 A KR 20090124426A KR 1020080050641 A KR1020080050641 A KR 1020080050641A KR 20080050641 A KR20080050641 A KR 20080050641A KR 20090124426 A KR20090124426 A KR 20090124426A
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- 238000000034 method Methods 0.000 title claims abstract description 41
- 239000004065 semiconductor Substances 0.000 title claims abstract description 19
- 238000005468 ion implantation Methods 0.000 claims abstract description 30
- 230000008569 process Effects 0.000 claims abstract description 28
- 239000012535 impurity Substances 0.000 claims abstract description 22
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 19
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 19
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 14
- 229920005591 polysilicon Polymers 0.000 claims abstract description 13
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 238000005530 etching Methods 0.000 claims abstract description 4
- 238000009792 diffusion process Methods 0.000 claims description 17
- 238000002156 mixing Methods 0.000 abstract description 4
- 238000002347 injection Methods 0.000 abstract 1
- 239000007924 injection Substances 0.000 abstract 1
- 230000003647 oxidation Effects 0.000 abstract 1
- 238000007254 oxidation reaction Methods 0.000 abstract 1
- 229920002120 photoresistant polymer Polymers 0.000 description 7
- 235000012431 wafers Nutrition 0.000 description 5
- 230000007547 defect Effects 0.000 description 3
- 238000010884 ion-beam technique Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229920000307 polymer substrate Polymers 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000010561 standard procedure Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
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Abstract
Description
본 발명은 불순물 확산과 이온 주입을 혼합하는 공정으로 소자를 형성하여 이온 주입에 의한 누설 전류를 감소시킬 수 있는 방법에 관한 것이다. The present invention relates to a method capable of reducing the leakage current by ion implantation by forming a device in a process of mixing impurity diffusion and ion implantation.
주지된 바와 같이 이온 주입은 반도체 웨이퍼에 불순물을 유입시키기 위한 표준 기술이다. 불순물 주입 정도는 불순물이 주입된 영역의 도전성을 결정하며, 이러한 불순물은 반도체 재질의 결정격자에 불순물을 주입하기 위한 수단으로서 이온 에너지의 모멘트를 이용하여 반도체 웨이퍼에 주입된다. As is well known, ion implantation is a standard technique for introducing impurities into semiconductor wafers. The degree of impurity implantation determines the conductivity of the region in which the impurity is implanted, and the impurity is implanted into the semiconductor wafer using a moment of ion energy as a means for injecting the impurity into the crystal lattice of the semiconductor material.
전형적으로 이온 주입은 이온 종류, 이온 에너지 평방센티당 이온 주입량으로 규정될 수 있다. 이온 소스는 정확하고 일정한 이온 빔 흐름을 전달하지 않기 때문에 이온 주입량을 연속적으로 측정할 필요가 있다. Typically, ion implantation can be defined as ion implantation, ion implantation per square centimeter of ion energy. Since ion sources do not deliver accurate and consistent ion beam flow, ion implantation needs to be measured continuously.
또한, 이온 주입은 불순물 확산 공정 보다 ULSI 산업에 측면 확산의 제어, 웨이퍼 전면의 균일도 및 웨이퍼 간의 재현성 증가, 생산량의 증가 그리고 정확한 불순물 프로파일의 제어 등 많은 이점을 제공한다.In addition, ion implantation provides the ULSI industry with many advantages over the impurity diffusion process, including control of lateral diffusion, increased wafer front uniformity and reproducibility between wafers, increased yield and control of accurate impurity profiles.
그러나, 상기한 바와 같이 동작되는 종래 기술에 의한 이온 주입은 높은 에너지에 따른 격자 손상과 이에 따른 추가적인 어닐링 공정을 필요로 한다는 단점이 있다. 즉 이러한 높은 에너지에 의한 격자 손상과 결함의 생성은 게이트 산화막 주변에서 웰 이온주입과 높은 농도(High Dose or High Concentration)로 수행되는 소오스/드레인 이온주입에 의한 누설 전류의 원인이 되어 반도체 수율을 떨어뜨리게 하는 문제점이 있다. However, the ion implantation according to the prior art operating as described above has the disadvantage that it requires lattice damage due to high energy and thus an additional annealing process. In other words, the lattice damage and defect generation due to the high energy cause the leakage current by source / drain ion implantation which is performed by well ion implantation and high concentration (High Dose or High Concentration) around the gate oxide, resulting in lower semiconductor yield. There is a problem that causes it.
이에, 본 발명의 기술적 과제는 상술한 바와 같은 문제점을 해결하기 위해 안출한 것으로, 웰 이온주입 공정을 분순물 확산 공정으로 대체하는 공정으로 소자를 형성함으로써, 이온 주입에 의한 누설 전류를 감소시킬 수 있는 반도체 소자의 형성 방법을 제공한다. Accordingly, the technical problem of the present invention is to solve the problems described above, by forming a device in the process of replacing the well ion implantation process with the impurities diffusion process, it is possible to reduce the leakage current by ion implantation A method of forming a semiconductor device is provided.
본 발명에서 반도체 소자의 형성 방법은 활성 영역 및 STI 영역이 형성된 기판 상부에 게이트 희생 산화막과 실리콘 질화막을 순차적으로 형성하는 단계와, 상기 형성된 실리콘 질화막의 일부를 제거하여 실리콘 질화막 패턴을 형성하는 단계와, 상기 실리콘 질화막 패턴을 마스크로 불순물 확산 공정을 실시하여 상기 기판내에 웰을 형성하는 단계와, 상기 게이트 희생 산화막 상부에 게이트 산화막 패턴을 형성하는 단계와, 상기 게이트 산화막 패턴 상부에 폴리 실리콘을 형성하고 식 각공정으로 소스/드레인이 형성될 폴리 실리콘 패턴을 형성하며, 상기 형성된 폴리 실리콘 패턴을 마스크로 이온 주입 공정을 실시하여 소스/드레인을 형성하는 단계와, 이온 주입 공정을 실시하여 LDD 접합층을 형성하는 단계를 포함한다. In the present invention, a method of forming a semiconductor device may include sequentially forming a gate sacrificial oxide layer and a silicon nitride layer on a substrate on which an active region and an STI region are formed, and removing a portion of the formed silicon nitride layer to form a silicon nitride layer pattern; Forming a well in the substrate by performing an impurity diffusion process using the silicon nitride pattern as a mask, forming a gate oxide pattern on the gate sacrificial oxide layer, and forming polysilicon on the gate oxide pattern Forming a polysilicon pattern in which the source / drain is to be formed by an etching process; forming a source / drain by performing an ion implantation process using the formed polysilicon pattern as a mask; and performing an ion implantation process to form an LDD bonding layer Forming a step.
상기 게이트 희생 산화막은, 30∼60Å 이내의 두께로 형성하는 것을 특징으로 한다. The gate sacrificial oxide film is formed to have a thickness within 30 to 60 kPa.
상기 불순물 확산 공정은, 900∼1000℃이내의 온도와 25분∼35분 이내의 시간으로 진행하는 것을 특징으로 한다. The impurity diffusion step is characterized in that it proceeds with a temperature within 900 ~ 1000 ℃ and a time within 25 minutes to 35 minutes.
상기 LDD 접합층은, 경사 각을 사용하는 것을 특징으로 한다. The said LDD bonding layer uses the inclination-angle, It is characterized by the above-mentioned.
본 발명은 웰 이온주입 공정을 분순물 확산 공정으로 대체하는 혼합 공정으로 소자를 형성함으로써, 기존에서와 같이 이온 주입에 의한 누설 전류의 원인을 감소시킬 수 있다. The present invention can reduce the cause of the leakage current by the ion implantation, as the conventional device by forming a device in a mixing process that replaces the well ion implantation process with a impurities diffusion process.
또한, 본 발명은 웰 이온주입 공정을 분순물 확산 공정으로 대체함으로써, 결함의 생성을 줄일 수 있어 반도체 수율을 향상시킬 수 있는 효과가 있다. In addition, the present invention has the effect of reducing the generation of defects by replacing the well ion implantation process with the impurities diffusion process, thereby improving the semiconductor yield.
또한, 본 발명은 소자 최적화를 위한 기존 이온 주입 공정을 그대로 유지함으로써, 소자의 성능을 유지할 수 있으며, 낮은 이온 빔 에너지와 농도를 가지고 있기 때문에 결함의 발생이 크지 않다.In addition, the present invention can maintain the performance of the device by maintaining the existing ion implantation process for device optimization as it is, and because of the low ion beam energy and concentration is not a large generation of defects.
또한, 본 발명은 소오스/드레인 이온 주입 과정중에 게이트 폴리실리콘으로 동시에 도핑이 가능하며, 이온 주입에 의한 폴리실리콘 데미지를 감소시킬 수 있으 며, 비용적인 측면에서 이온 주입 장비의 사용이 적어지기 때문에 웨이퍼당 제조 단가가 줄어들게 되는 효과가 있다. In addition, the present invention can be simultaneously doped with gate polysilicon during the source / drain ion implantation process, can reduce the polysilicon damage caused by ion implantation, and the use of ion implantation equipment in terms of cost is reduced, so that the wafer Sugar production costs are reduced.
이하 첨부된 도면을 참조하여 본 발명의 동작 원리를 상세히 설명한다. 하기에서 본 발명을 설명함에 있어서 공지 기능 또는 구성에 대한 구체적인 설명이 본 발명의 요지를 불필요하게 흐릴 수 있다고 판단되는 경우에는 그 상세한 설명을 생략할 것이다. 그리고 후술되는 용어들은 본 발명에서의 기능을 고려하여 정의된 용어들로서 이는 사용자, 운용자의 의도 또는 관례 등에 따라 달라질 수 있다. 그러므로 그 정의는 본 명세서 전반에 걸친 내용을 토대로 내려져야 할 것이다. Hereinafter, the operating principle of the present invention will be described in detail with reference to the accompanying drawings. In the following description of the present invention, when it is determined that a detailed description of a known function or configuration may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted. Terms to be described later are terms defined in consideration of functions in the present invention, and may be changed according to intentions or customs of users or operators. Therefore, the definition should be made based on the contents throughout the specification.
도 1a 내지 도 1i는 본 발명의 바람직한 실시예에 따른 반도체 소자의 형성 방법에 대한 각 공정별 수직 단면도이다.1A to 1I are vertical cross-sectional views of respective processes of a method of forming a semiconductor device in accordance with a preferred embodiment of the present invention.
즉, 도 1a를 참조하면, 반도체 공정을 실시하여 반도체 기판(예컨대, 실리콘 기판, 세라믹 기판, 고분자 기판 등)(101)의 활성(Active) 영역과 소자 분리를 위한 영역인 STI(103)를 형성한다.That is, referring to FIG. 1A, a semiconductor process is performed to form an active region of a semiconductor substrate (eg, a silicon substrate, a ceramic substrate, a polymer substrate, etc.) 101 and an
다음에, 활성 영역과 STI(103) 영역이 형성된 반도체 기판(101) 상부에 게이트 희생 산화막(Gate Sacrificial Oxide)(105)을 일 예로, 도 1b에 도시된 바와 같이 형성한다. 여기서, 게이트 희생 산화막(105)은 30∼60Å 이내의 두께로 형성하 는 것이 바람직하다. Next, a gate
다음으로, 게이트 희생 산화막(105) 상부에 불순물 확산 공정의 확산 배리어로 사용되는 실리콘 질화막(Silicon Nitride)(107)을 일 예로, 도 1c에 도시된 바와 같이 형성한다. Next, a
이어서, 실리콘 질화막(107) 상부 전면에 감광막(Photo Resist, PR)을 형성(예컨대, 도포)하고, 노광 및 현상 공정을 실시하여 도포된 PR을 선택적으로 패터닝하여 일 예로, 도 1d에 도시된 바와 같이 PR 패턴(109)을 형성한다. Subsequently, a photoresist (PR) is formed on the entire upper surface of the silicon nitride film 107 (eg, applied), and the exposed PR is selectively patterned to selectively pattern the applied PR, for example, as shown in FIG. 1D. The
다음으로, PR 패턴(109)을 마스크로 식각 공정을 실시하여 불순물 확산 웰(Well)을 형성하기 위해 웰 부분의 실리콘 질화막(107)의 일부를 제거하여 일 예로, 도 1e에 도시된 바와 같이 실리콘 질화막 패턴(107a)을 형성한다. Next, a portion of the
다음에, 실리콘 질화막 패턴(107a)을 마스크로 확산 웰 도핑(Diffusion Well Doping) 방식의 불순물 확산 공정을 실시하여 일 예로, 도 1f에 도시된 바와 같이 반도체 기판(101)내에 웰(111)을 형성한다. 여기서, 불순물 확산 공정은 900∼1000℃이내의 온도와 25분∼35분 이내의 시간으로 진행하는 것이 바람직하다. Next, an impurity diffusion process of a diffusion well doping method is performed using the silicon
다음으로, 웰(111)이 형성된 게이트 희생 산화막(105) 상부에 게이트 산화막(Gate Oxide) 패턴(113)을 일 예로, 도 1g에 도시된 바와 같이 형성한다.Next, a
이어서, 실리콘 질화막 패턴(107a)과 게이트 산화막 패턴(113)이 형성된 게이트 희생 산화막(105) 상부에 폴리실리콘(PolySilicon)을 형성하고, 사진 식각 공정을 실시하여 폴리 실리콘 패턴(115)을 형성시킨 후, 이 형성된 폴리 실리콘 패턴(115)을 마스크로 소오스/드레인 이온 주입 공정을 실시하여 일 예로, 도 1h에 도시된 바와 같이 소스(Source)(117)/드레인(Drain)(119) 접합층을 형성한다. Subsequently, a polysilicon is formed on the gate
마지막으로, 소스(117)/드레인(119) 접합층이 형성된 상태에서 소자의 성능을 최적화를 위해 높은 경사 각(Tilt Angle)을 사용하는 LDD(Lightly Doped Drain) 이온 주입 공정(121)을 실시하여 소스(117)/드레인(119) 양쪽 기판내에 일 예로, 도 1i에 도시된 바와 같이 불순물이 주입된 LDD 접합층(123)을 형성한다.Finally, LDD (Lightly Doped Drain)
이상 설명한 바와 같이, 본 발명은 웰 이온주입 공정을 분순물 확산 공정으로 대체하는 혼합 공정으로 소자를 형성함으로써, 기존에서와 같이 이온 주입에 의한 누설 전류의 원인을 감소시켜 반도체 수율을 향상시킬 수 있다. As described above, the present invention can improve the semiconductor yield by reducing the cause of leakage current by ion implantation, as the device is formed by a mixing process that replaces the well ion implantation process with the impurities diffusion process. .
한편 본 발명의 상세한 설명에서는 구체적인 실시예에 관해 설명하였으나, 본 발명의 범위에서 벗어나지 않는 한도 내에서 여러 가지 변형이 가능함은 물론이다. 그러므로 본 발명의 범위는 설명된 실시예에 국한되지 않으며, 후술되는 특허청구의 범위뿐만 아니라 이 특허청구의 범위와 균등한 것들에 의해 정해져야 한다. Meanwhile, in the detailed description of the present invention, specific embodiments have been described, but various modifications are possible without departing from the scope of the present invention. Therefore, the scope of the present invention should not be limited to the described embodiments, but should be defined not only by the scope of the following claims, but also by those equivalent to the scope of the claims.
도 1a 내지 도 1i는 본 발명의 바람직한 실시예에 따른 반도체 소자의 형성 방법에 대한 각 공정별 수직 단면도.1A to 1I are vertical cross-sectional views of respective processes of a method of forming a semiconductor device in accordance with a preferred embodiment of the present invention.
<도면의 주요부분에 대한 부호의 설명><Description of the symbols for the main parts of the drawings>
101 : 반도체 기판 103 : STI101: semiconductor substrate 103: STI
105 : 게이트 희생 산화막 107 : 실리콘 질화막105 gate
107a : 실리콘 질화막 패턴 109 : PR 패턴107a: Silicon nitride film pattern 109: PR pattern
111 : 웰 113 : 게이트 산화막 패턴111 well 113 gate oxide film pattern
115 : 폴리 실리콘 패턴 117 : 소스(Source)115: polysilicon pattern 117: source
119 : 드레인(Drain) 121 : 이온 주입 공정119: drain 121: ion implantation process
123 : LDD 접합층123: LDD bonding layer
Claims (4)
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103390546A (en) * | 2012-05-08 | 2013-11-13 | 无锡华润上华科技有限公司 | Ion implantation method of polysilicon gate electrode |
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