KR20090123385A - Board for mounting semiconductor package - Google Patents

Board for mounting semiconductor package Download PDF

Info

Publication number
KR20090123385A
KR20090123385A KR1020080049434A KR20080049434A KR20090123385A KR 20090123385 A KR20090123385 A KR 20090123385A KR 1020080049434 A KR1020080049434 A KR 1020080049434A KR 20080049434 A KR20080049434 A KR 20080049434A KR 20090123385 A KR20090123385 A KR 20090123385A
Authority
KR
South Korea
Prior art keywords
board
mounting
package
vent line
thermal
Prior art date
Application number
KR1020080049434A
Other languages
Korean (ko)
Inventor
손은숙
강원준
황태경
Original Assignee
앰코 테크놀로지 코리아 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 앰코 테크놀로지 코리아 주식회사 filed Critical 앰코 테크놀로지 코리아 주식회사
Priority to KR1020080049434A priority Critical patent/KR20090123385A/en
Publication of KR20090123385A publication Critical patent/KR20090123385A/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

PURPOSE: A board for mounting a semiconductor package is provided to prevent a void phenomenon by forming an air vent line in a mounting area for mounting the package with a cross structure. CONSTITUTION: A package exposing a lower side of a chip mounting plate is mounted in a board(10). An additional air vent line(22) is formed in a mounting area(12) of the board adhered by a solder paste. The air vent line is formed in an adjacent part of a plurality of thermal through vias(14) formed in the mounting area. The air vent line is formed with the cross structure of a width vent line(22a) and a length vent line(22b) which cross the plurality of thermal throw vias in the mounting area.

Description

반도체 패키지 실장용 보드{Board for mounting semiconductor package}Board for mounting semiconductor package

본 발명은 반도체 패키지 실장용 보드에 관한 것으로서, 더욱 상세하게는 리드프레임의 칩 탑재판 저면이 외부로 노출된 구조의 반도체 패키지를 보이드(void) 현상의 발생없이 용이하게 실장시킬 수 있도록 한 반도체 패키지 실장용 보드에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a board for mounting a semiconductor package, and more particularly, a semiconductor package in which a semiconductor package having a structure in which a bottom surface of a chip mounting plate of a lead frame is exposed to the outside can be easily mounted without the occurrence of voids. It relates to a mounting board.

일반적으로 리드프레임을 이용한 반도체 패키지중 열방출 효과를 극대화하기 위한 구조로서, 칩탑재판 및 리드의 저면이 외부로 노출되는 EP(Exposed Pad)패키지가 알려져 있으며, 이러한 EP 패키지중 대표적인 것으로 MLF(Micro LeadFrame) 타입의 패키지를 들 수 있다.In general, as a structure for maximizing the heat dissipation effect of the semiconductor package using the lead frame, an EP (Exposed Pad) package is known that the bottom surface of the chip mounting plate and the lead is exposed to the outside, MLF (Micro LeadFrame) package.

상기 MLF 타입의 패키지는 휴대폰, 셀룰러 폰, 노트북 등과 같은 전자기기의 소형화 및 그 내부에 장착되는 마더보드의 소형화 추세에 따라, 대략 1×1mm ~ 10×10mm 내외로 제조되는 소형 패키지이다.The MLF type package is a compact package manufactured to about 1 × 1 mm to 10 × 10 mm according to the miniaturization of electronic devices such as mobile phones, cellular phones, laptops, and the like, and the miniaturization of the motherboard mounted therein.

여기서 MLF형 패키지에 대한 구조 및 그 제조 방법을 간략하게 살펴보면 다 음과 같다.Here is a brief look at the structure of the MLF package and its manufacturing method.

첨부한 도 3a 내지 도 3c는 MLF 패키지를 나타내는 단면도 및 저면도이다.3A to 3C are sectional views and a bottom view of the MLF package.

먼저, 리드프레임(40)이 구비된다.First, the lead frame 40 is provided.

상기 리드프레임(40)은 골격 역할을 하는 사이드프레임(미도시됨)과, 반도체 칩(34)이 탑재되는 칩탑재판(32)과, 상기 사이드프레임으로부터 연장되어 칩탑재판(32)의 테두리 부분에 인접 배열되는 다수의 리드(36)와, 상기 칩탑재판(32)을 지지하기 위하여 칩탑재판(32)의 각 모서리와 상기 사이드프레임간을 일체로 연결하는 타이바(38)로 구성된다.The lead frame 40 includes a side frame (not shown) serving as a skeleton, a chip mounting plate 32 on which the semiconductor chip 34 is mounted, and an edge of the chip mounting plate 32 extending from the side frame. A plurality of leads 36 arranged adjacent to the portion, and tie bars 38 integrally connecting the corners of the chip mounting plate 32 and the side frames to support the chip mounting plate 32. do.

이때, 상기 사이드프레임은 개개의 반도체 패키지로 싱귤레이션하는 공정에서 제거되므로, 도면에는 도시하지 않았다.At this time, since the side frame is removed in the process of singulating into individual semiconductor packages, it is not shown in the drawings.

다음으로, 상기 칩탑재판(32)의 상면에 접착수단에 의하여 반도체 칩(34)이 부착되고, 상기 각 리드(36)와 상기 반도체 칩(34)의 본딩패드가 와이어(42)로 연결된다.Next, the semiconductor chip 34 is attached to the upper surface of the chip mounting plate 32 by adhesive means, and the leads 36 and the bonding pads of the semiconductor chip 34 are connected by wires 42. .

이어서, 몰딩 공정이 진행됨에 따라, 상기 반도체 칩(34)과 와이어(42), 상기 리드(36)의 내측면, 상기 칩탑재판(32)의 상면 및 측면 등이 몰딩 컴파운드 수지(44)로 둘러싸이게 된다.Subsequently, as the molding process proceeds, the semiconductor chip 34, the wire 42, the inner surface of the lead 36, the upper surface and the side surface of the chip mounting plate 32, and the like are formed into the molding compound resin 44. Is surrounded.

이때, 상기 칩탑재판(32)의 저면 및 각 리드(36)의 저면와 외측면이 외부로 노출되는 상태가 된다.At this time, the bottom surface of the chip mounting plate 32 and the bottom surface and the outer surface of each lead 36 are exposed to the outside.

한편, 상기 리드프레임 구비 단계에서, 상기 칩탑재판(32)의 측면과, 상기 각 리드(36)의 내측면은 미리 하프 에칭된 상태이며, 이러한 하프 에칭부는 몰딩 컴파운드 수지(44)와의 결합력을 향상시키기 위하여 형성된 것이다.Meanwhile, in the lead frame providing step, the side surface of the chip mounting plate 32 and the inner surface of each lead 36 are half etched in advance, and the half etching portion is provided with a bonding force with the molding compound resin 44. It is formed to improve.

이와 같이 하여, 외부로 노출된 칩탑재판(32)과 각 리드(36)를 통하여, 반도체 칩(34)에서 발생되는 열이 용이하게 방출될 수 있는 구조의 MLF 패키지(30)로 완성된다.In this way, through the chip mounting plate 32 and the leads 36 exposed to the outside, the heat generated from the semiconductor chip 34 is completed with the MLF package 30 of the structure that can be easily released.

이렇게 제조된 MLF 패키지(30)는 전자기기의 마더보드(10)에 솔더링(soldering)에 의하여 마운팅된다.The manufactured MLF package 30 is mounted by soldering to the motherboard 10 of the electronic device.

여기서 MLF 패키지가 마운팅되는 보드의 구조 및 이 보드에 MLF 패키지를 마운팅하는 방법을 설명하면 다음과 같다.Here, the structure of the board on which the MLF package is mounted and the method of mounting the MLF package on the board are as follows.

첨부한 4는 MLF 패키지 마운팅용 보드를 나타내는 평면도이다.Attached 4 is a plan view showing a board for mounting an MLF package.

상기 보드(10)에는 MLF 패키지(30)의 칩탑재판(32)이 안착되는 마운팅 영역(12)이 구획되어 있고, 이 마운팅 영역(12)의 사방에는 MLF 패키지의 각 리드(36)가 전기적으로 연결될 수 있는 다수의 입출력단자(46)가 형성되어 있다.The board 10 has a mounting area 12 in which the chip mounting plate 32 of the MLF package 30 is seated, and each lead 36 of the MLF package is electrically connected to four sides of the mounting area 12. A plurality of input and output terminals 46 that can be connected to are formed.

특히, 상기 마운팅 영역(12)에는 다수의 써멀 쓰루 비아(14: thermal through via)가 형성되어 있다.In particular, a plurality of thermal through vias 14 are formed in the mounting region 12.

따라서, 상기 보드(10)의 마운팅 영역(12)에 솔더 페이스트(solder paste)를 스텐실 프린팅(stencil printing)하는 솔더링 공정후, 상기 패키지(30)의 칩 탑재판(32)의 저면을 솔더링 완료된 마운팅 영역(12)상에 실장하게 된다.Accordingly, after the soldering process of stencil printing solder paste on the mounting area 12 of the board 10, the bottom surface of the chip mounting plate 32 of the package 30 is soldered. It will be mounted on the area 12.

이에, 상기 반도체 칩(34)에서 발생된 열은 칩탑재판(32)을 경유하여 보드(10)의 써멀 쓰루 비아(14)를 통해 분산되며 방출되어진다.Accordingly, heat generated in the semiconductor chip 34 is dispersed and discharged through the thermal through vias 14 of the board 10 via the chip mounting plate 32.

이때, MLF 패키지의 열방출 성능을 극대화하기 위해서, 외부로 노출된 칩탑 재판 밑에 존재하는 솔더 페이스트 품질, 즉 솔더링 품질이 중요하며, 이 솔더링 품질과 관계있는 인자는 적당한 솔더 페이스트 두께와 최소의 보이드(칩 탑재판과 솔더 페이스트 사이의 기포 형성 공간) 면적을 들 수 있다.At this time, in order to maximize the heat dissipation performance of the MLF package, the solder paste quality, i.e., soldering quality, existing under the exposed chip top trial is important, and the factors related to the soldering quality are appropriate solder paste thickness and minimum void ( Bubble-forming space between the chip mounting plate and the solder paste).

그러나, 상기 MLF 패키지를 보드의 마운팅 영역에 실장하는 공정시 다음과 같은 문제점이 있었다.However, there was a problem in the process of mounting the MLF package in the mounting area of the board.

솔더 페이스트를 보드의 마운팅 영역상에 솔더링하는 공정시, 잔존하던 에어(air)가 다수의 써멀 쓰루 비아를 통하여 빠져나가 보이드 현상을 줄여주는 효과가 있지만, 첨부한 도 6의 현미경 사진에서 보는 바와 같이 솔더 페이스트(24)가 써멀 쓰루 비아(14)를 통하여 함께 빠져나가는 현상이 발생되고 있다.In the process of soldering the solder paste onto the mounting area of the board, the remaining air escapes through the plurality of thermal through vias, thereby reducing the void phenomenon, as shown in the attached micrograph of FIG. 6. A phenomenon in which the solder paste 24 is pulled out together through the thermal through via 14 is generated.

이렇게 솔더 페이스트가 써멀 쓰루 비아로 빠져나가게 되면, 솔더 페이스트를 균일한 두께로 조절하는데 어려움이 따르게 되고, 결국 칩 탑재판과 보드간의 결합력이 약화될 수 있다.As the solder paste escapes into the thermal through via, it is difficult to adjust the solder paste to a uniform thickness, which may weaken the bond between the chip mounting plate and the board.

이러한 점을 감안하여, 첨부한 도 5의 (a) 및 (b) 에 도시된 바와 같이 써멀 쓰루 비아(14)의 상단 개방부 또는 하단 개방부를 솔더 마스크(18)로 막아주거나, (c)에 도시된 바와 같이 써멀 쓰루 비아(14)의 하단 내부에 구리(20) 또는 솔더 마스크를 끼워주거나, (e)에 도시된 바와 같이 써멀 쓰루 비아(14)의 하단 내부에 구리(20) 또는 솔더 마스크를 끼워준 다음 그 상하부분에 다시 구리를 도금하는 등의 방법을 통해, 솔더 페이스트가 써멀 쓰루 비아를 통해 빠져나가지 않도록 하고 있다.In view of this, as shown in (a) and (b) of FIG. 5, the upper or lower openings of the thermal through vias 14 are covered with the solder mask 18, or (c) is provided. Insert copper 20 or solder mask into the bottom of the thermal through via 14 as shown, or copper 20 or solder mask into the bottom of the thermal through via 14 as shown in (e). The solder paste is prevented from escaping through the thermal through vias by inserting and then plating the copper back and forth.

그러나, 써멀 쓰루 비아를 막아줌으로써, 솔더 페이스트가 빠져나가는 것을 차단할 수 있으나, 이로 인해 솔더링 공정시 에어가 써멀 쓰루 비아를 통해 빠져나가지 못하게 되어, 보드와 솔더 페이스트 사이 또는 칩탑재판의 저면과 솔더 페이스트 사이에 보이드 현상이 발생되는 문제점이 있었다.However, by blocking the thermal through vias, the solder paste can be prevented from escaping, but this prevents air from escaping through the thermal through vias during the soldering process, so that between the board and the solder paste or between the bottom of the chipboard and the solder paste There was a problem that voids occur between.

이러한 보이드 발생으로 인해, 칩탑재판을 통해 보드의 써멀 쓰루 비아로 전달되는 반도체 칩의 열이 효과적으로 배출되지 못하게 되고, 과도한 솔더 페이스트 높이를 형성하여 칩탑재판과 보드간의 결합력이 떨어지는 단점을 초래하게 된다.Due to this void generation, the heat of the semiconductor chip transferred through the chipboard to the thermal through via of the board is not effectively discharged, and an excessive solder paste height is formed, which causes a disadvantage that the bonding force between the chipboard and the board falls. do.

본 발명은 상기와 같은 점을 감안하여 안출한 것으로서, MLF 패키지와 같이 칩탑재판의 저면이 노출된 타입의 패키지를 보드에 솔더링을 통해 실장할 때, 그 계면부에 잔존하는 공기가 빠져나갈 수 있는 통로를 보드에 직접 더 형성하여, 보이드 현상을 방지할 수 있도록 한 반도체 패키지 실장용 보드를 제공하는데 그 목적이 있다.The present invention has been made in view of the above, and when mounting a package of the bottom surface of the chip mounting plate, such as MLF package through the soldering on the board, the air remaining in the interface portion can escape It is an object of the present invention to provide a board for semiconductor package mounting in which a passage is formed directly on the board to prevent voiding.

상기한 목적을 달성하기 위한 본 발명은: 칩탑재판의 저면이 노출된 타입의 패키지가 실장되는 보드에 있어서, 상기 칩탑재판이 솔더 페이스트에 의하여 접착되는 상기 보드의 마운팅 영역에 별도의 에어벤트라인을 형성하되, 상기 마운팅 영역내에 형성된 다수의 써멀 쓰루 비아의 인접 부위에 요홈 구조로 형성된 것을 특 징으로 하는 반도체 패키지 실장용 보드를 제공한다.In order to achieve the above object, the present invention provides a board on which a package of a type having an exposed bottom surface of a chip mounting board is mounted, wherein a separate air vent line is provided in a mounting area of the board to which the chip mounting board is bonded by solder paste. To provide a semiconductor package mounting board, characterized in that formed in the groove structure in the adjacent portions of the plurality of thermal through vias formed in the mounting region.

바람직한 구현예로서, 상기 에어벤트라인은 상기 마운팅 영역내에 형성된 다수의 써멀 쓰루 비아 사이를 가로방향으로 지나는 가로방향 벤트라인과, 세로방향으로 지나는 세로방향 벤트라인이 서로 교차되는 구조로 형성된 것을 특징으로 한다.In a preferred embodiment, the air vent line is formed in a structure in which a transverse vent line transversely between the plurality of thermal through vias formed in the mounting region and a longitudinal vent line transversely cross each other. do.

상기한 과제 해결 수단을 통하여, 본 발명은 다음과 같은 효과를 제공할 수 있다.Through the above problem solving means, the present invention can provide the following effects.

보드의 패키지 실장을 위한 마운팅 영역에 별도의 에어벤트라인을 형성하되, 마운팅 영역내에 형성된 다수의 써멀 쓰루 비아의 인접 부위을 따라, 가로 및 세로 방향으로 교차된 구조의 에어벤트라인을 형성해줌으로써, 칩탑재판의 저면이 노출된 타입의 패키지를 전자기기의 보드에 실장할 때, 그 경계부에 잔존하는 공기가 보드에 미리 형성된 써멀 쓰루 비아가 아닌 에어벤트라인으로 용이하게 배출되어, 보이드 현상을 방지할 수 있다.By forming a separate air vent line in the mounting area for package mounting of the board, along the adjacent portion of the plurality of thermal through vias formed in the mounting area, by forming the air vent line of the horizontal and vertical intersecting structure, chip mounting When mounting a package of an exposed type on a board of an electronic device on a board of an electronic device, air remaining at the boundary of the board is easily discharged to the air vent line instead of the thermal through vias formed on the board to prevent voiding. have.

이하, 본 발명의 바람직한 실시예를 첨부도면을 참조로 상세하게 설명하기로 한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

첨부한 도 1은 본 발명에 따른 반도체 패키지 실장용 보드에 대한 일 실시예 와, 종래의 보드를 대비하여 도시한 평면도 및 단면도이고, 첨부한 도 2는 본 발명에 따른 반도체 패키지 실장용 보드에 대한 다른 실시예와, 종래의 보드를 대비하여 도시한 평면도 및 단면도이다.1 is a plan view and a cross-sectional view of an embodiment of a semiconductor package mounting board according to the present invention and a conventional board, and FIG. 2 is a diagram of a semiconductor package mounting board according to the present invention. Another embodiment is a plan view and a cross-sectional view of a conventional board.

상기 보드(10)에는 MLF 패키지와 같이 칩탑재판의 저면에 외부로 노출된 패키지(30)가 실장되는 면적, 즉 마운팅 영역(12)이 구획되어 있으며, 이 마운팅 영역내에는 다수의 써멀 쓰루 비아(14)가 가로 및 세로 방향으로 등간격으로 이루며 형성되어 있다.The board 10 is divided into an area in which the package 30 exposed to the outside of the chip mounting plate, such as an MLF package, is mounted, that is, a mounting area 12, and a plurality of thermal through vias are mounted in the mounting area. (14) is formed at equal intervals in the horizontal and vertical directions.

이때, 도 1에 도시된 바와 같이 상기 마운팅 영역(12)의 상하면은 열전도도가 좋은 구리 도금층(16)이 형성되어 있으며, 각 써멀 쓰루 비아(14)의 상부 개방부가 솔더 마스크(18)에 의하여 막힌 상태이거나, 도 2에 도시된 바와 같이 상기 마운팅 영역(12)의 상하면이 구리 도금층(16)으로 형성되면서 각 써멀 쓰루 비아(14)내에 솔더 또는 구리(20)가 채워진 구조로 되어 있다.At this time, as shown in FIG. 1, the upper and lower surfaces of the mounting region 12 are formed with a copper plated layer 16 having good thermal conductivity, and the upper openings of the respective thermal through vias 14 are formed by the solder mask 18. As shown in FIG. 2, the upper and lower surfaces of the mounting region 12 are formed of the copper plating layer 16, and the thermal through vias 14 are filled with solder or copper 20.

여기서, 본 발명에 따르면 상기 보드(10)의 마운팅 영역(12)내에 형성된 다수의 써멀 쓰루 비아(14)의 인접 부위에 별도의 에어벤트라인(22)이 에칭 공정에 의하여 요홈 구조로 형성된다.Here, according to the present invention, a separate air vent line 22 is formed in a groove structure by an etching process at adjacent portions of the plurality of thermal through vias 14 formed in the mounting region 12 of the board 10.

보다 상세하게는, 상기 에어벤트라인(22)은 상기 마운팅 영역(12)내에 형성된 다수의 써멀 쓰루 비아(14) 사이를 가로방향으로 지나는 가로방향 벤트라인(22a)과, 세로방향으로 지나는 세로방향 벤트라인(22b)이 서로 교차되는 구조로 형성된다.More specifically, the air vent line 22 includes a transverse vent line 22a transversely between a plurality of thermal through vias 14 formed in the mounting region 12 and a longitudinal transverse direction. The vent lines 22b are formed to cross each other.

따라서, 첨부한 도 3에 도시된 MLF 패키지와 같이 칩탑재판 저면이 노출된 패키지(30)를 상기 보드(10)에 실장하고자 할 경우, 상기 보드(10)의 마운팅 영역(12)에 솔더 페이스트(도 6에 24지로 지시됨)를 스텐실 프린팅(stencil printing)하는 솔더링 공정을 진행하고, 이어서 칩 탑재판(32)의 저면을 솔더링 완료된 마운팅 영역(12)상에 밀착시켜 실장하게 된다.Accordingly, when the package 30 exposed on the bottom surface of the chip mounting plate, such as the MLF package shown in FIG. 3, is to be mounted on the board 10, solder paste may be attached to the mounting area 12 of the board 10. A soldering process of stencil printing (indicated by 24 points in FIG. 6) is performed, and then the bottom surface of the chip mounting plate 32 is brought into close contact with and mounted on the soldered mounting region 12.

이때, 상기 솔더 페이스트(24)와 상기 보드(10)의 마운팅 영역(12)간에 존재하던 에어가 요홈 구조인 가로방향 벤트라인(22a) 및 세로방향 벤트라인(22b)으로 구성된 에어벤트라인(22)을 통하여 외부로 배출됨에 따라, 상기 솔더 페이스트(24)와 상기 보드(10)의 마운팅 영역(12)간의 계면에서 보이드가 발생되는 것을 방지할 수 있다.At this time, the air present between the solder paste 24 and the mounting area 12 of the board 10 is air vent line 22 composed of a horizontal vent line 22a and a vertical vent line 22b having grooves. As it is discharged to the outside through), it is possible to prevent the generation of voids at the interface between the solder paste 24 and the mounting region 12 of the board (10).

이렇게 보이드 발생 현상을 방지함에 따라, 솔더 페이스트의 두께를 균일하게 제어할 수 있고, 뿐만 아니라 보드 표면에 요철 구조로 형성된 에어벤트라인은 패키지와 보드간의 접합강도를 증가시켜 기계적 신뢰성도 향상시킬 수 있다.By preventing the occurrence of voids, the thickness of the solder paste can be uniformly controlled, as well as the air vent line formed by the uneven structure on the board surface can increase the bonding strength between the package and the board, thereby improving the mechanical reliability. .

이상과 같이, 써멀 쓰루 비아의 인접부위에 에어벤트라인을 형성하는 구조를 보드로 국한하여 설명하였지만, 이는 하나의 실시예일 뿐, 솔더 페이스트를 솔더링하는 공정이 필요한 패키지의 내부 즉, 칩탑재판과 칩의 경계부, 또는 내부에 도터 보드(daughter board)를 사용하는 SIP 모듈 패키지에도 동일한 에어벤트라인을 적용할 수 있는 것으로 이해해야 할 것이다.As described above, the structure for forming the air vent line in the adjacent portion of the thermal through via has been described as a board, but this is only one embodiment, and the inside of the package that requires the process of soldering the solder paste, that is, the chip mounting plate and It is to be understood that the same air vent line can be applied to a SIP module package using a daughter board inside or at a chip boundary.

도 1은 본 발명에 따른 반도체 패키지 실장용 보드에 대한 일 실시예와, 종래의 보드를 대비하여 도시한 평면도 및 단면도,1 is a plan view and a cross-sectional view showing an embodiment of a semiconductor package mounting board according to the present invention, and a conventional board,

도 2는 본 발명에 따른 반도체 패키지 실장용 보드에 대한 다른 실시예와, 종래의 보드를 대비하여 도시한 평면도 및 단면도,2 is a plan view and a cross-sectional view showing another embodiment of a board for mounting a semiconductor package according to the present invention and a conventional board,

도 3a 내지 도 3b는 MLF 타입의 패키지 구조를 설명하는 단면도 및 저면도,3A to 3B are cross-sectional and bottom views illustrating a package structure of the MLF type,

도 4는 종래의 반도체 패키지 실장용 보드 구조를 설명하는 평면도,4 is a plan view illustrating a conventional semiconductor package mounting board structure;

도 5는 종래의 반도체 패키지 실장용 보드의 써멀 쓰루 비아를 막아주는 방법을 설명하는 요부 단면도,5 is a cross-sectional view illustrating main parts of a method of preventing thermal through vias of a conventional semiconductor package mounting board;

도 6은 종래의 반도체 패키지 실장용 보드의 써멀 쓰루 비아를 통해 솔더 레지스트가 유출되는 현상을 보여주는 현미경 사진.Figure 6 is a micrograph showing the phenomenon that the solder resist is leaked through the thermal through vias of the conventional semiconductor package mounting board.

<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for main parts of the drawings>

10 : 보드 12 : 마운팅 영역10: board 12: mounting area

14 : 써멀 쓰루 비아 16 : 구리 도금층14 thermal through via 16 copper plating layer

18 : 솔더 마스크 20 : 구리18 solder mask 20 copper

22 : 에어벤트라인 22a : 가로방향 벤트라인22: air vent line 22a: horizontal vent line

22b : 세로방향 벤트라인 24 : 솔더 페이스트22b: longitudinal vent line 24: solder paste

30 : 패키지 32 : 칩 탑재판30: package 32: chip mounting plate

34 : 반도체 칩 36 : 리드34: semiconductor chip 36: lead

38 : 타이바 40 : 리드프레임38: tie bar 40: lead frame

42 : 와이어 44 : 몰딩 컴파운드 수지42: wire 44: molding compound resin

46 : 입출력단자46: I / O terminal

Claims (2)

칩탑재판의 저면이 노출된 타입의 패키지가 실장되는 보드에 있어서, In a board on which a package of a type having an exposed bottom surface of a chip mounting board is mounted, 상기 칩탑재판이 솔더 페이스트에 의하여 접착되는 상기 보드의 마운팅 영역에 별도의 에어벤트라인을 형성하되, 상기 마운팅 영역내에 형성된 다수의 써멀 쓰루 비아의 인접 부위에 요홈 구조로 형성된 것을 특징으로 하는 반도체 패키지 실장용 보드.The chip mounting board is formed in the mounting area of the board to be bonded by a solder paste, the air package is a semiconductor package mounting, characterized in that formed in the groove structure in the adjacent portion of the plurality of thermal through vias formed in the mounting area Board. 청구항 1에 있어서, 상기 에어벤트라인은 상기 마운팅 영역내에 형성된 다수의 써멀 쓰루 비아 사이를 가로방향으로 지나는 가로방향 벤트라인과, 세로방향으로 지나는 세로방향 벤트라인이 서로 교차되는 구조로 형성된 것을 특징으로 하는 반도체 패키지 실장용 보드.The method of claim 1, wherein the air vent line is characterized in that the horizontal vent line passing in the transverse direction between the plurality of thermal through vias formed in the mounting area and the longitudinal vent line passing in the longitudinal direction cross each other Board for semiconductor package mounting.
KR1020080049434A 2008-05-28 2008-05-28 Board for mounting semiconductor package KR20090123385A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020080049434A KR20090123385A (en) 2008-05-28 2008-05-28 Board for mounting semiconductor package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020080049434A KR20090123385A (en) 2008-05-28 2008-05-28 Board for mounting semiconductor package

Publications (1)

Publication Number Publication Date
KR20090123385A true KR20090123385A (en) 2009-12-02

Family

ID=41685629

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020080049434A KR20090123385A (en) 2008-05-28 2008-05-28 Board for mounting semiconductor package

Country Status (1)

Country Link
KR (1) KR20090123385A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP4422359A1 (en) 2023-02-23 2024-08-28 Magna Electronics Sweden AB Circuit board
EP4429418A1 (en) 2023-03-08 2024-09-11 Magna Electronics Sweden AB Circuit board

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP4422359A1 (en) 2023-02-23 2024-08-28 Magna Electronics Sweden AB Circuit board
WO2024175441A1 (en) 2023-02-23 2024-08-29 Magna Electronics Sweden Ab Circuit board
EP4429418A1 (en) 2023-03-08 2024-09-11 Magna Electronics Sweden AB Circuit board
WO2024184084A1 (en) 2023-03-08 2024-09-12 Magna Electronics Sweden Ab Circuit board

Similar Documents

Publication Publication Date Title
US7656015B2 (en) Packaging substrate having heat-dissipating structure
JP5633210B2 (en) Semiconductor device
TWI543314B (en) Semiconductor package
US20030057545A1 (en) PBGA substrate for anchoring heat sink
US20080054443A1 (en) Carrier board structure with semiconductor chip embedded therein
US20070215995A1 (en) Fabrication processes of leadframe-based BGA packages and leadless leadframe implemented in the processes
US9252068B2 (en) Semiconductor package
KR101054440B1 (en) Electronic device package and manufacturing method thereof
US7714417B2 (en) Substrate for mounting semiconductor element and method of manufacturing the same
KR20090081038A (en) Mold for manufacturing semiconductor package and Method for molding semiconductor package using the same
JP5000105B2 (en) Semiconductor device
JP2006073586A (en) Semiconductor device manufacturing method
KR20090123385A (en) Board for mounting semiconductor package
JP4647673B2 (en) Heat dissipation type multi-hole semiconductor package
JP5298714B2 (en) Manufacturing method of semiconductor device
KR101088087B1 (en) Heat slug for semiconductor package and method for manufacturing semiconductor package using the same
JP3920657B2 (en) Manufacturing method of resin-encapsulated semiconductor device
JP2010010569A (en) Circuit device and method of manufacturing the same
JPH09116045A (en) Resin-sealed semiconductor device of bga type using lead frame and its manufacture
JP3684517B2 (en) Semiconductor device
KR20130059580A (en) Semiconductor package and method for manufacturing the same
KR100658903B1 (en) Lead frame and semiconductor package using it
JP2004031561A (en) Semiconductor device and its manufacturing method
KR101047874B1 (en) Lead frame and semiconductor package and manufacturing method thereof
KR100600366B1 (en) Semiconductor and method for manufacturing the same

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E601 Decision to refuse application