KR20090118594A - High voltage generation circuit and flash memory device including same - Google Patents

Abstract

The high voltage generation circuit of the flash memory device includes a high voltage detector, a clock signal controller, an oscillator, a pumped clock controller and a charge pump. The high voltage detector provides at least one comparison signal by comparing the high voltage applied to the memory cell array with at least one reference voltage. The clock signal controller provides a clock control signal for changing the frequency of the clock signal in response to the at least one comparison signal. The oscillator generates a clock signal whose frequency changes in accordance with the clock control signal. The pumping clock controller provides a pumping clock by blocking or passing the clock signal in response to a control signal indicating that the high voltage is above a certain level. The charge pump continuously pumps while the pumping clock is applied to generate the high voltage.

Description

High voltage generation circuit and flash memory device including the same

The present invention relates to a semiconductor memory device, and more particularly to a flash memory device.

Semiconductor memory is the most essential device in digital logic designs based on microprocessors, from satellites to consumer electronics. Thus, advances in semiconductor memory fabrication technology for high integration and high speeds help establish performance benchmarks for other digital logic families.

The semiconductor memory device is largely divided into a volatile semiconductor memory device and a nonvolatile memory device. In a volatile semiconductor memory device, data is stored and read while power is applied, and data is lost when power is cut off. On the other hand, nonvolatile memory devices, such as MROM (MASK ROM), PROM (Programmable ROM), EPROM (Erasable and Programmable ROM), and EEPROM (Electrically Erasable and Programmable ROM), may store data even when the power is cut off.

The data storage state of the nonvolatile memory can be permanent or reprogrammable, depending on the manufacturing technique used. Among the nonvolatile memory devices, MROM, PROM, and EPROM are not freely erased and written by the system itself, and thus it is not easy for ordinary users to update the memory contents. On the other hand, since EEPROMs can be electrically erased and written, applications to system programming or auxiliary storage devices requiring continuous updating are expanding. In particular, the flash EEPROM (hereinafter referred to as flash memory) has a higher density than the conventional EEPROM, which is very advantageous for application to a large capacity auxiliary storage device.

Flash memory is classified into NOR and NAND types according to cell and bit line connection states. A NOR flash memory has two or more cell transistors connected in parallel to one bit line. NOR flash memory stores data using channel hot electrons and erases data using Fowler-Nordheim tunneling. A NAND flash memory has two or more cell transistors connected in series to one bit line. NAND-type flash memories use F-N tunneling to store and erase data. In general, NOR flash memory is disadvantageous for high integration due to the large current consumption, but has an advantage of easily coping with high speed. Recently, multi-level cell (hereinafter referred to as MLC) scheme has been adopted for high integration of NOR flash memory.

For example, when single-bit data is stored in a flash memory, data stored in a unit cell may be represented by two threshold voltage distributions corresponding to data '1' and data '0', respectively. On the other hand, when the multi-bit data is stored in the NOR type flash memory, the data stored in the unit cell includes four data corresponding to data '11', data '10', data '00', and data '01'. It can be represented by threshold voltage distributions. As the number of bits of data stored in each cell increases, the level of voltage required to program, erase, and read each data becomes more diverse.

Thus, in order to more accurately program, erase, and read data stored in the flash memory, it is necessary to accurately generate respective voltages necessary to program, erase, and read each data. There is also a need for a technique that allows each generated voltage level to remain constant without fluctuation. In addition, if there is a need to adjust the voltage level actually applied to the flash memory, there is a need for a technology that can adjust the voltage level without additional work such as cutting a fuse or a metal option.

Accordingly, an object of the present invention is to provide a high voltage generation circuit capable of efficiently adjusting the voltage level of the high voltage applied to the memory cell array.

An object of the present invention is to provide a flash memory device including the high voltage generation circuit.

In order to achieve the above object of the present invention, a high voltage generation circuit of a flash memory device according to an embodiment of the present invention includes a high voltage detector, a clock signal controller, an oscillator, a pumping clock controller and a charge pump. The high voltage detector provides at least one comparison signal by comparing the high voltage applied to the memory cell array with at least one reference voltage. The clock signal controller provides a clock control signal for changing a frequency of a clock signal in response to the at least one comparison signal. The oscillator generates the clock signal whose frequency changes in accordance with the clock control signal. The pumping clock controller provides a pumping clock by blocking or passing the clock signal in response to a control signal indicating that the high voltage is higher than or equal to a predetermined level. The charge pump pumps continuously while the pumping clock is applied to generate the high voltage.

In an embodiment, the high voltage generating circuit may include a high voltage regulator configured to compare the voltage obtained by dividing the high voltage using at least two resistors with a first reference voltage and to provide the control signal selectively activated accordingly. It may further include. The high voltage generation circuit may further include a trim block configured to provide a trim control signal for adjusting the divided voltage according to trim information applied from the outside when it is necessary to change the voltage level of the high voltage.

In example embodiments, the at least one reference voltage may include a second reference voltage and a third reference voltage having a lower voltage level than the second reference voltage. The at least one comparison signal includes a first comparison signal and a second comparison signal, and when the voltage level of the high voltage is higher than the voltage level of the second reference voltage, the first comparison signal is included in the clock control signal unit. The frequency of the clock signal may be increased according to the clock control signal. When the voltage level of the high voltage is lower than the voltage level of the second reference voltage, the second comparison signal may be applied to the clock signal controller, and the frequency of the clock signal may be decreased according to the clock control signal. .

A high voltage generation circuit of a flash memory device according to another embodiment of the present invention for achieving the above object includes a high voltage regulator, a trim block, a clock signal controller, an oscillator, a pumping clock controller and a charge pump. The high voltage regulator compares the divided voltage obtained by dividing the high voltage applied to the memory cell array with a reference voltage and provides a control signal that is selectively activated according to the result. The trim block provides a trim control signal in response to trim information applied from the outside when it is necessary to change the voltage level of the high voltage. The clock signal controller provides a clock control signal for varying the frequency of the clock signal in response to the trim control signal. The oscillator generates the clock signal whose frequency changes in accordance with the clock control signal. The pumping clock controller provides a pumping clock by blocking or passing the clock signal in response to a control signal indicating that the high voltage is higher than or equal to a predetermined level. The charge pump pumps continuously while the pumping clock is applied to generate the high voltage.

In example embodiments, the control signal may be activated when the voltage level of the high voltage is higher than the voltage level of the reference voltage, and the pumping clock controller may block the clock signal when the control signal is activated. The control signal may be deactivated when the voltage level of the high voltage is lower than the voltage level of the reference voltage. When the control signal is deactivated, the pumping clock controller may pass the clock signal.

In example embodiments, when the voltage level of the high voltage needs to be increased, the clock signal controller may control the oscillator to increase the frequency of the clock signal in response to the trim control signal. When the voltage level of the high voltage needs to be lowered, the clock signal controller may control the oscillator to decrease the frequency of the clock signal in response to the trim control signal.

A high voltage generation circuit of a flash memory device according to another embodiment of the present invention for achieving the above object includes a high voltage detector, a high voltage regulator, a trim block, a clock signal controller, an oscillator, a pumped clock controller and a charge pump. The high voltage sensing unit compares a high voltage applied to the memory cell array with at least one reference voltage to provide at least one comparison signal. The high voltage regulator compares the divided voltage obtained by dividing the high voltage with a first reference voltage and provides a control signal that is selectively activated according to the result. The trim block provides a trim control signal in response to trim information applied from the outside when it is necessary to change the voltage level of the high voltage. The clock signal controller provides a clock control signal for varying a frequency of a clock signal in response to the trim control signal or the at least one comparison signal or the trim control signal and the at least one comparison signal. The oscillator generates the clock signal whose frequency changes in accordance with the clock control signal. The pumping clock controller provides a pumping clock by blocking or passing the clock signal in response to a control signal indicating that the high voltage is higher than or equal to a predetermined level. The charge pump pumps continuously while the pumping clock is applied to generate the high voltage.

The at least one reference voltage may include a second reference voltage and a third reference voltage having a lower voltage level than the second reference voltage, wherein the at least one comparison signal is compared with the first comparison signal. A signal, wherein the first comparison signal is applied to the clock control signal part when the voltage level of the high voltage is higher than the voltage level of the second reference voltage, and the frequency of the clock signal is increased according to the clock control signal. Can be increased. In addition, when the voltage level of the high voltage is lower than the voltage level of the second reference voltage, the second comparison signal is applied to the clock signal controller, and the frequency of the clock signal may be decreased according to the clock control signal. have.

In order to achieve the above object of the present invention, a flash memory device according to an embodiment of the present invention includes a memory cell array including a plurality of memory cells, a high voltage generation circuit, and a selection circuit. The high voltage generation circuit generates a plurality of high voltages to be applied to the memory cell array according to an operation mode. The selection circuit selects one of the plurality of high voltages and applies it to the memory cell array. The high voltage generation circuit changes the frequency of a clock signal for generating the high voltages according to a result of comparing the voltage levels of the high voltages applied to the memory cell array with one or more reference voltages according to the operation mode, thereby changing the voltage levels of the high voltages. To change.

The high voltage regulator may include a high voltage regulator configured to compare a divided voltage obtained by dividing the high voltage with a first reference voltage among the at least one reference voltage, and provide a control signal selectively activated according to the result. A high voltage detection unit comparing the second reference voltage and the third reference voltage among the at least one reference voltage and providing a first comparison signal and a second comparison signal according to a result of the comparison, the first comparison signal and the second comparison signal A clock signal controller for providing a clock control signal for changing a frequency of the clock signal in response to a comparison signal, an oscillator for generating the clock signal having a frequency change in accordance with the clock control signal, and generating the clock signal in response to the control signal A pumping clock control unit for blocking or passing the pumping clock to provide a pumping clock It may include a charge pump that pumps continuously while the rack is applied to generate the high voltage.

The high voltage regulator may include a high voltage regulator configured to compare a divided voltage obtained by dividing the high voltage with a first reference voltage among the at least one reference voltage, and provide a control signal selectively activated according to the result. When it is necessary to change the voltage level of the trim block for providing a trim control signal in response to the trim information applied from the outside, the clock for providing a clock control signal for changing the frequency of the clock signal in response to the trim control signal A signal controller, an oscillator for generating the clock signal whose frequency changes in accordance with the clock control signal, a pumping clock controller for blocking or passing the clock signal in response to the control signal to provide a pumping clock, and while the pumping clock is applied When pumping continuously to generate the high voltage It may include a charge pump.

The high voltage generation circuit may compare the high voltage with a second reference voltage and a third reference voltage of the at least one reference voltage and provide a first comparison signal and a second comparison signal according to a result of the comparison. A high voltage detector configured to compare the divided voltage obtained by dividing the high voltage with a first reference voltage among the at least one reference voltage, and to provide a control signal selectively activated according to the result; Is in response to a trim block, the trim control signal or the at least one comparison signal or the trim control signal and the at least one comparison signal in response to the trim information applied from the outside. Providing a clock control signal for varying the frequency of the clock signal A clock signal control unit, an oscillator for generating the clock signal whose frequency changes according to the clock control signal, a pumping clock control unit which provides a pumping clock by blocking or passing the clock signal in response to the control signal, and the pumping clock is applied It may include a charge pump for continuously pumping while generating the high voltage.

According to the present invention, it is possible to stably supply a plurality of high voltages necessary for programming, erasing and reading data stored in the flash memory, and to change the level of the high voltage, it is not necessary to perform additional operations such as metal options or laser fuses. It can increase the speed of external work and test.

With respect to the embodiments of the present invention disclosed in the text, specific structural to functional descriptions are merely illustrated for the purpose of describing embodiments of the present invention, embodiments of the present invention may be implemented in various forms and It should not be construed as limited to the embodiments described in.

As the inventive concept allows for various changes and numerous embodiments, particular embodiments will be illustrated in the drawings and described in detail in the text. However, this is not intended to limit the present invention to a specific disclosure form, it should be understood to include all modifications, equivalents, and substitutes included in the spirit and scope of the present invention. In describing the drawings, similar reference numerals are used for the components.

Terms such as first and second may be used to describe various components, but the components should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be referred to as the second component, and similarly, the second component may also be referred to as the first component.

When a component is referred to as being "connected" or "connected" to another component, it may be directly connected to or connected to that other component, but it may be understood that other components may be present in between. Should be. On the other hand, when a component is said to be "directly connected" or "directly connected" to another component, it should be understood that there is no other component in between. Other expressions describing the relationship between components, such as "between" and "immediately between," or "neighboring to," and "directly neighboring to" should be interpreted as well.

The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of the present invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this application, the terms "comprise" or "having" are intended to indicate that there is a feature, number, step, action, component, part, or combination thereof that is described, and that one or more other features or numbers are present. It should be understood that it does not exclude in advance the possibility of the presence or addition of steps, actions, components, parts or combinations thereof.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art. Terms such as those defined in the commonly used dictionaries should be construed as having meanings consistent with the meanings in the context of the related art and shall not be construed in ideal or excessively formal meanings unless expressly defined in this application. Do not.

Hereinafter, with reference to the accompanying drawings, it will be described in detail a preferred embodiment of the present invention. The same reference numerals are used for the same elements in the drawings, and duplicate descriptions of the same elements are omitted.

1 is a block diagram showing the overall configuration of a flash memory device 100 according to the present invention. 1 illustrates a configuration of a flash memory of a NOR type according to an MLC data storage method as an example to which the present invention is applied.

Referring to FIG. 1, a flash memory device 100 according to the present invention may include a memory cell array 10, a column selector 20, a row selector 30, a data input / output circuit 40, and an input / output buffer 50. , A controller 60, and a high voltage generation circuit 70.

The memory cell array 10 includes a plurality of memory cells arranged in an intersection area of a plurality of rows (ie, word lines) and a plurality of columns (ie, bit lines). The voltage generation circuit 70 generates a plurality of high voltages required for program, erase, and read operations of the memory cell. The plurality of high voltages generated by the voltage generation circuit 70 are applied to the corresponding word lines through the row selector 30. The row selector 30 selects any one of the plurality of high voltages generated by the voltage generation circuit 70 and selects a word line to which the selected high voltage is applied. The column selector 20 selects a bit line to which a cell to be programmed (or read) is connected among a plurality of memory cells included in the selected word line.

The input / output buffer 50 stores data to be programmed in the memory cell array 10 and data sensed from the memory cell array 10. The data input / output circuit 40 is composed of a write driver 41 and a sense amplifier 44. The write driver 42 receives data to be programmed from the input / output buffer 50 and performs a program operation on the selected memory cell. The sense amplifier 44 senses data programmed into the selected memory cell. Data sensed by the sense amplifier 44 is stored in the input / output buffer 50. The controller 60 controls all operations related to program, erase, and read operations of the flash memory.

Detailed configurations of the memory cell array 10, the column selector 20, the row selector 30, the data input / output circuit 40, the input / output buffer 50, and the controller 60 are known in the art. It is already well known to those who have it. Therefore, in the present invention, detailed configurations of the memory cell array 10, the column selector 20, the row selector 30, the data input / output circuit 40, the input / output buffer 50, and the controller 60 will be described in detail. I decided not to.

2 is a block diagram showing a detailed configuration of the voltage generation circuit 70 of FIG. 1 according to the first embodiment of the present invention.

2, a voltage generation circuit 70 according to an embodiment of the present invention includes a high voltage detector (HVD) 110, a clock signal control unit (CSCU) 120, and an oscillator ( OSC., 130), a pumping clock control unit (PCCU) 140, and a charge pump (CP) 150. The voltage generation circuit may further include a high voltage regulator HVR 160 and a trim block TB 170.

The high voltage detector 110 compares the high voltage HVO applied to the memory cell array MCA 10 with at least one reference voltage REF2 and REF3, and compares the at least one comparison signal CS1 and CS2. It provides a) comprising a. The clock signal controller 120 provides a clock control signal CCS for changing the frequency of the clock signal CK in response to the at least one comparison signal CS. The oscillator 130 generates the clock signal CK whose frequency is changed according to the clock control signal CCS. The pumping clock controller 140 blocks or passes the clock signal CK according to the control signal HV_OK signal provided from the high voltage regulator 160 to provide a pumping clock PCK. The charge pump 150 pumps continuously while the pumping clock PCK is applied to generate the high voltage HVO.

3 is a circuit diagram illustrating a detailed configuration of the high voltage regulator 160 of FIG. 2 according to an embodiment of the present invention.

Referring to FIG. 3, the high voltage regulator 160 includes a PMOS transistor 161, first and second voltage divider resistors 163 and 164, a first comparator 162, an inverter 165, and a level shifter 166. ).

The high voltage regulator 160 turns on / off the PMOS transistor 161 according to the logic level of the high voltage activation signal HV_ENABLE according to the voltage level of the high voltage HVO. The first comparator 162 compares the first divided voltage V1 divided by the first and second resistors 163 and 164 with the first reference voltage REF1 to compare the high voltage HVO. When the voltage reaches or exceeds the predetermined level, that is, when the divided voltage is equal to or greater than the first reference voltage REF1, the control signal HV_OK that is transitioned to the high level is provided.

4 is a circuit diagram illustrating a detailed configuration of the high voltage detecting unit 110 of FIG. 1 according to an embodiment of the present invention.

Referring to FIG. 4, the high voltage detector 110 includes third to fifth voltage divider resistors 111, 112, and 113, a second comparator 114, and a third comparator 115. The high voltage detection unit 110 compares the high voltage HVO with the second reference voltage REF2 and the third reference voltage REF3, and according to the comparison result, the first comparison signal CS1 and the second comparison signal CS2. ). More specifically, the high voltage HVO is divided into the second divided voltage V2 and the third divided voltage V3 by the second to fourth divided resistors 111, 112, and 113. The second comparator 114 compares the second divided voltage V2 with the second reference voltage and provides a first comparison signal CS1 having a logic level according to the comparison result. The third comparator 115 compares the third divided voltage V3 with the third reference voltage and provides a second comparison signal CS2 having a logic level according to the comparison result.

The high voltage detector 110 may provide a single bit of the first comparison signal CS1 and the second comparison signal CS2, and the first comparison signal CS1 and the second comparison signal CS2 are combined. 2 bits of the comparison signal CS may be provided. For example, when the first comparison signal CS1 and the second comparison signal CS2 are combined, if the voltage level of the high voltage HVO is greater than or equal to the second reference voltage REF2, the comparison signal CS may be “11”. have. When the voltage level of the high voltage HVO is between the second reference voltage REF2 and the third reference voltage REF3, the comparison signal CS may be "01". In addition, when the voltage level of the high voltage HVO is equal to or less than the third reference voltage REF3, the comparison signal CS may be “00”. In addition, the comparison signal may be 3 bits or more depending on the number of voltage divider resistors included in the high voltage detector 110.

Hereinafter, the operation of the high voltage generation circuit 70 according to an embodiment of the present invention will be described in detail with reference to FIGS. 2 to 4.

When the voltage level of the high voltage HVO applied to the memory cell array 10 is greater than or equal to the first reference voltage REF1, the high voltage regulator 160 transitions to the high level with the control signal HV_OK provided by the high voltage regulator 160. When the control signal HV_OK is at a high level, the pumping clock controller 140 blocks the clock signal CK provided from the oscillator 130. That is, when the control signal HV_OK is at a high level, the pumping clock PCK is not supplied to the charge pump 150. Since the pumping clock PCK is not supplied to the charge pump 150, the voltage level of the high voltage HVO applied to the memory cell array 10 is maintained at a constant level.

The voltage level of the high voltage HVO applied to the memory cell array 10 is also continuously sensed by the high voltage detector 110 based on the second reference voltage REF2 and the third reference voltage REF3. When the voltage level of the high voltage HVO is greater than or equal to the second reference voltage REF2, the first comparison signal CS1 provided from the second comparator 114 is transitioned to a high level. When the first comparison signal CS1 having the high level is applied to the clock signal controller 120, the clock signal controller 120 decreases the frequency of the clock signal CK according to the first comparison signal CS1 having the high level. The clock control signal CCS is provided to the oscillator 130. Accordingly, the oscillator 130 provides the clock signal CK having the reduced frequency to the pumping clock controller 140. At this time, the pumping clock signal PCK whose frequency is reduced according to the logic level of the control signal HV_OK is applied to or blocked by the charge pump 150. At this time, the resistance values of the first and second voltage divider resistors 163 and 164 of the high voltage regulator 160 and the third to fifth voltage divider resistors 111, 112, and 113 of the high voltage detector 110 are all included. If the same, the first divided voltage is smaller than the second divided voltage, so that the control signal HV_OK is at a high level. Therefore, the pumping clock signal PCK having a reduced frequency is not applied to the charge pump 150. Therefore, the voltage level of the high voltage HVO is lowered.

When the voltage level of the high voltage HVO continues to decrease according to the program, read, and erase operations of the flash memory cell 10 and becomes lower than the third reference voltage REF3, the output of the third comparator 115 is output. The logic level of the second comparison signal CS2 is transitioned to the low level. When the second comparison signal CS2 at the low level is applied to the clock signal controller 120, the clock signal controller 120 increases the frequency of the clock signal CK according to the second comparison signal CS2 at the low level. The clock control signal CCS is provided to the oscillator 130. Accordingly, the oscillator 130 provides a clock signal CK having an increased frequency to the pumping clock controller 140. At this time, the pumping clock signal PCK whose frequency is reduced according to the logic level of the control signal HV_OK is applied to or blocked by the charge pump 150. At this time, the resistance values of the first and second voltage divider resistors 163 and 164 of the high voltage regulator 160 and the third to fifth voltage divider resistors 111, 112, and 113 of the high voltage detector 110 are all included. If the same, the first divided voltage is greater than the third divided voltage, so that the control signal HV_OK is at a low level. Therefore, the pumping clock signal PCK having an increased frequency is applied to the charge pump 150. Therefore, the charge pump 150 increases the voltage level of the high voltage HVO by a continuous pumping operation.

As such, the frequency of the clock signal CK output from the oscillator 130 by the clock control signal CCS may be controlled by the capacitors (not shown) included in the oscillator 130 according to the clock control signal CCS. This is because the time constant of the oscillator can be adjusted by being connected or disconnected.

The first to third reference voltages REF1, REF2, and REF3 may be set in various ways as necessary, and may include first and second voltage divider resistors 163 and 164 of the high voltage regulator 160. It is apparent to those skilled in the art that the third to fifth voltage dividers 111, 112, and 113 of the high voltage detector 110 may be implemented in various ways as necessary.

The voltage level of the initially set high voltage (HVO) may not be the desired voltage level due to a process change, and the voltage level of the high voltage (HVO) applied to the memory cell array 10 is different from the initially set voltage level. There may be a situation that needs to be set. When this situation occurs, the trim block 170 may apply the trim control signal TCS to the high voltage regulator 160 to change the resistance ratio of the divided resistors 163 and 164 to generate a desired high voltage. The trim block 170 stores trim information TI applied from the outside and applies the trim control signal TCS to the high voltage regulator 160 based on the trim information TI.

5A to 5E are timing diagrams illustrating various signals of the voltage generation circuit 70 of FIG. 1 according to an exemplary embodiment of the present invention.

5A illustrates a clock signal CK having an unadjusted frequency output from the oscillator 130.

5B illustrates a control signal HV_OK output from the high voltage regulator 160.

5C illustrates a clock signal CK in which the frequency output from the oscillator 130 is increased by the clock control signal CCS.

FIG. 5D illustrates a control signal HV_OK applied to the pumping clock controller 140 when the frequency of the clock signal CK is increased.

5E illustrates the pumping clock PCK applied to the charge pump 150 when the frequency of the clock signal CK is increased.

5A to 5E, it can be seen that the frequency of the clock signal CK can be increased according to the voltage level of the high voltage HVO as described above with reference to FIGS. 2 to 4. Although not shown in FIGS. 5A to 5E, as described above with reference to FIGS. 2 to 4, when the voltage level of the high voltage HVO rises above a certain level, the frequency of the clock signal CK may be decreased.

The frequency of the clock signal CK may be changed by the trim control signal TI provided by the trim block 170 as well as the comparison signal of the high voltage detector 110.

6 is a block diagram showing a detailed configuration of the voltage generation circuit 70 of FIG. 1 according to another embodiment of the present invention.

Referring to FIG. 6, the voltage generation circuit 200 according to another embodiment of the present invention includes a clock signal controller 220, an oscillator 130, a pumped clock controller 140, a charge pump 150, and a high voltage regulator 160. ) And trim block 170. The voltage generation circuit 200 of FIG. 6 does not include the high voltage detector 110, and the trim control signal TCS is provided to the clock signal controller 220 as well as the high voltage regulator 160. There is a difference from the circuit 70.

3 and 6, the operation of the voltage generation circuit 200 according to another embodiment of the present invention will be described in detail.

The trim block 170 provides the trim control signal TCS to the high voltage regulator 160 and the clock signal controller 220 based on the trim information TI applied from the outside. The high voltage regulator 160 changes the voltage level of the first divided voltage V1 by changing the resistance ratio of the first and second divided resistors 163 and 164 according to the trim control signal TCS. The clock signal controller 220 receives the trim control signal TCS from the trim block 170 and provides the clock control signal CCS to the oscillator 130 according to the trim control signal TCS. For example, since the trim control signal TCS is a signal based on the trim information TI applied from the outside, the trim control signal TCS may include information for changing the resistance ratio of the second voltage divider resistors 163 and 164. It may also be a signal of two or more bits. Accordingly, the clock signal controller 220 provides the clock control signal CCS to the oscillator 130 according to the bit level logic level of the trim control signal TCS. In response to the clock control signal CCS, the oscillator 130 generates a clock signal CK having an increased or decreased frequency and provides the generated clock signal CK to the pumping clock controller 140. The pumping clock controller 140 may include a pumping clock PCK whose frequency is changed according to a logic level of the control signal HV_OK according to a result of comparing the first divided voltage V1 having the changed voltage level with the first reference voltage REF1. Is applied to the charge pump 150 to lower the voltage level of the high voltage HVO by increasing the voltage level of the high voltage HVO or blocking the pumping clock PCK whose frequency is changed.

As described above with reference to FIGS. 2 to 5E, the oscillator 130 includes capacitors (not shown), so that capacitors (not shown) included in the oscillator 130 may be connected according to a clock control signal CCS. It is cut off so that the time constant of the oscillator can be adjusted to adjust the frequency of the clock signal CK.

7 is a block diagram showing a detailed configuration of the voltage generation circuit 70 of FIG. 1 according to another embodiment of the present invention.

Referring to FIG. 7, the voltage generation circuit 300 according to another embodiment of the present invention may include a high voltage detector 110, a clock signal controller 320, an oscillator 130, a pumping clock controller 140, and a charge pump. 150, includes. High voltage regulator 160 and trim block 170. In the voltage generation circuit 300 of FIG. 7, the high voltage detector 110 and the trim block 170 provide the comparison signal CS and the trim control signal TCS to the clock signal controller 320, respectively. 6 is different from the voltage generation circuit 70 of FIG. 6 in that the high voltage sensing unit 110 provides the comparison signal CS to the clock signal controller 320. have.

3, 4 and 7 will be described in detail the operation of the voltage generating circuit 300 according to another embodiment of the present invention.

The trim block 170 provides the trim control signal TCS to the high voltage regulator 160 and the clock signal controller 320 based on the trim information TI applied from the outside. The high voltage regulator 160 changes the voltage level of the first divided voltage V1 by changing the resistance ratio of the first and second divided resistors 163 and 164 according to the trim control signal TCS. The clock signal controller 220 receives the trim control signal TCS from the trim block 170 and provides the clock control signal CCS to the oscillator 130 according to the trim control signal TCS. For example, since the trim control signal TCS is a signal based on the trim information TI applied from the outside, the trim control signal TCS may include information for changing the resistance ratio of the second voltage divider resistors 163 and 164. It may also be a signal of two or more bits. Accordingly, the clock signal controller 220 provides the clock control signal CCS to the oscillator 130 according to the bit level logic level of the trim control signal TCS. In response to the clock control signal CCS, the oscillator 130 generates a clock signal CK having an increased or decreased frequency and provides the generated clock signal CK to the pumping clock controller 140. The pumping clock controller 140 may include a pumping clock PCK whose frequency is changed according to a logic level of the control signal HV_OK according to a result of comparing the first divided voltage V1 having the changed voltage level with the first reference voltage REF1. Is applied to the charge pump 150 to lower the voltage level of the high voltage HVO by increasing the voltage level of the high voltage HVO or blocking the pumping clock PCK whose frequency is changed.

The high voltage detection unit 110 compares the high voltage HVO with the second reference voltage REF2 and the third reference voltage REF3 and according to the comparison result, the first comparison signal CS1 and the second comparison signal CS2. To provide. The first comparison signal CS1 and the second comparison signal CS2 are applied to the clock signal controller 320. A clock signal whose frequency is increased or decreased in the oscillator 130 by a clock control signal CS applied to the oscillator 130 according to the logic level of the first comparison signal CS1 and the second comparison signal CS2. (CK) is generated and provided to the pumping clock controller 140. The pumping clock controller 140 may include a pumping clock PCK whose frequency is changed according to a logic level of the control signal HV_OK according to a result of comparing the first divided voltage V1 having the changed voltage level with the first reference voltage REF1. Is applied to the charge pump 150 to lower the voltage level of the high voltage HVO by increasing the voltage level of the high voltage HVO or blocking the pumping clock PCK whose frequency is changed.

That is, the voltage generation circuit 300 according to the third embodiment of the present invention uses the comparison signal CS provided from the high voltage detection circuit 110 and the trim control signal TCS provided from the trim block 170. The frequency of the clock signal CK may be adjusted respectively. In this case, when the frequency of the clock signal CK is largely adjusted, that is, when the voltage level of the initially set high voltage is largely increased or decreased, the trim control signal TCS provided from the trim block 170 is increased. It is available. In addition, when the frequency of the clock signal CK is adjusted to a small width, that is, when the voltage level of the initially set high voltage is increased or decreased to a small width, the comparison signals CS or CS1 and CS2 provided by the high voltage detection unit 110 are provided. ) Can be used. Of course, the trim control signal TCS and the comparison signal CS may be simultaneously used to adjust the voltage level of the high voltage HVO to a desired level.

As described above with reference to FIGS. 2 to 6, since the oscillator 130 includes capacitors (not shown), capacitors (not shown) included in the oscillator 130 may be connected according to a clock control signal CCS. It is cut off so that the time constant of the oscillator can be adjusted to adjust the frequency of the clock signal CK.

8 shows a configuration of an oscillator 130 according to an embodiment of the present invention. The oscillator 130 includes a plurality of delay elements 131, 132, and 133, a plurality of resistors R1, R2, and R3, a plurality of capacitors C1, C2, and C3, and a plurality of switches S1 and S2. , S3). The plurality of switches S1, S2, and S3 are connected to the comparison signal CS or the trim control signal TCS or the comparison signal CS and the trim control signal TCS applied to the clock signal controller 320. A plurality of capacitors C1, C2, and C3 are selectively connected by the applied clock control signal CCS to change the time constant of the oscillator so that the frequency of the clock signal CK can be changed.

Although the configuration and operation of the circuit according to the embodiments of the present invention have been described above with reference to the above description and drawings, this is merely an example. And various changes and modifications are possible without departing from the technical spirit of the present invention. For example, the configuration of the voltage generation circuit provided in the NOR type flash memory is described as an example. This is just one embodiment to which the present invention is applied. Therefore, as long as it is a memory device that needs to stably generate a plurality of high voltages, the voltage generation circuit according to the present invention is not only a NAND type flash memory device but also various kinds of nonvolatile memory devices, for example, MROM ( MASK ROM (PROM), programmable ROM (PROM), erasable and programmable ROM (EPROM), and electrically erasable and programmable ROM (EEPROM) are all applicable.

According to the present invention, it is possible to stably supply a plurality of high voltages necessary for programming, erasing and reading data stored in the flash memory, and to change the level of the high voltage, it is not necessary to perform additional operations such as metal options or laser fuses. It can be applied to a nonvolatile memory device that requires high voltage because it can reduce external work and test time.

As described above, the present invention has been described with reference to a preferred embodiment of the present invention, but those skilled in the art may vary the present invention without departing from the spirit and scope of the present invention as set forth in the claims below. It will be understood that modifications and changes can be made.

1 is a block diagram showing the overall configuration of a flash memory device according to the present invention.

2 is a block diagram illustrating a detailed configuration of the voltage generation circuit 70 of FIG. 1 according to an embodiment of the present invention.

3 is a circuit diagram illustrating a detailed configuration of the high voltage regulator of FIG. 2 according to an embodiment of the present invention.

4 is a circuit diagram illustrating a detailed configuration of the high voltage detector of FIG. 1 according to an embodiment of the present invention.

5A through 5E are timing diagrams illustrating various signals of the voltage generation circuit of FIG. 1, according to an exemplary embodiment.

6 is a block diagram illustrating a detailed configuration of the voltage generation circuit of FIG. 1 according to another exemplary embodiment of the present invention.

7 is a block diagram illustrating a detailed configuration of the voltage generation circuit of FIG. 1 according to another embodiment of the present invention.

8 is a circuit diagram showing the configuration of an oscillator according to an embodiment of the present invention.

Description of the main parts of the drawing

110: high voltage detection unit 120, 220, 320: clock signal control unit

130; Oscillator 140; Pumping clock control

150; Charge pump 160; High voltage regulator

170; Trim block

Claims (20)

A high voltage detector configured to compare the high voltage applied to the memory cell array with at least one reference voltage to provide at least one comparison signal; A clock signal controller configured to provide a clock control signal for changing a frequency of a clock signal in response to the at least one comparison signal; An oscillator for generating the clock signal whose frequency varies in accordance with the clock control signal; A pumping clock controller which provides a pumping clock by blocking or passing the clock signal in response to a control signal indicating that the high voltage is above a predetermined level; And And a charge pump that pumps continuously while the pumping clock is applied to generate the high voltage. 2. The high voltage regulator of claim 1, further comprising a high voltage regulator configured to compare the voltage divided by the at least two resistors with a first reference voltage and provide the control signal selectively activated according to the result. A high voltage generation circuit of a flash memory device. The trim block of claim 2, further comprising a trim block for providing a trim control signal for adjusting the divided voltage according to trim information applied from the outside when it is necessary to change the voltage level of the high voltage. High voltage generation circuit of flash memory device. The high voltage generating circuit of claim 1, wherein the at least one reference voltage comprises a second reference voltage and a third reference voltage having a lower voltage level than the second reference voltage. The method of claim 4, wherein the at least one comparison signal comprises a first comparison signal and a second comparison signal, and when the voltage level of the high voltage is higher than the voltage level of the second reference voltage, The high voltage generation circuit of the flash memory device, characterized in that applied to the clock control signal portion, the frequency of the clock signal is increased in accordance with the clock control signal. 6. The method of claim 5, wherein when the voltage level of the high voltage is lower than the voltage level of the second reference voltage, the second comparison signal is applied to the clock signal controller, and the frequency of the clock signal according to the clock control signal. The high voltage generating circuit of the flash memory device, characterized in that is reduced. A high voltage regulator for comparing the divided voltage obtained by dividing the high voltage applied to the memory cell array with a reference voltage and providing a control signal selectively activated according to the result; A trim block configured to provide a trim control signal in response to trim information applied from the outside when it is necessary to change the voltage level of the high voltage; A clock signal controller configured to provide a clock control signal for varying a frequency of a clock signal in response to the trim control signal; An oscillator for generating the clock signal whose frequency varies in accordance with the clock control signal;  A pumping clock controller which provides a pumping clock by blocking or passing the clock signal in response to the control signal; And And a charge pump that pumps continuously while the pumping clock is applied to generate the high voltage. The flash memory of claim 7, wherein the control signal is activated when the voltage level of the high voltage is higher than the voltage level of the reference voltage, and the pumping clock controller blocks the clock signal when the control signal is activated. High voltage generator circuit of the device. The flash signal of claim 7, wherein the control signal is deactivated when the voltage level of the high voltage is lower than the voltage level of the reference voltage, and the pumping clock controller passes the clock signal when the control signal is deactivated. High voltage generation circuit of memory device. The high voltage generation of the flash memory device as claimed in claim 7, wherein when the voltage level of the high voltage needs to be increased, the clock signal controller controls the oscillator to increase the frequency of the clock signal in response to the trim control signal. Circuit. The high voltage generation of the flash memory device as claimed in claim 7, wherein the clock signal controller controls the oscillator to decrease the frequency of the clock signal in response to the trim control signal when the voltage level of the high voltage needs to be lowered. Circuit. A high voltage detector configured to compare the high voltage applied to the memory cell array with at least one reference voltage to provide at least one comparison signal; A high voltage regulator for comparing the divided voltage obtained by dividing the high voltage with a first reference voltage and providing a control signal selectively activated according to the result; A trim block which provides a trim control signal in response to trim information applied from the outside when it is necessary to change the voltage level of the high voltage; A clock signal controller providing a clock control signal for varying a frequency of a clock signal in response to the trim control signal or the at least one comparison signal or the trim control signal and the at least one comparison signal; An oscillator for generating the clock signal whose frequency varies in accordance with the clock control signal; A pumping clock controller which provides a pumping clock by blocking or passing the clock signal in response to the control signal; And And a charge pump that pumps continuously while the pumping clock is applied to generate the high voltage. The high voltage generation of the flash memory device as claimed in claim 12, wherein when the voltage level of the high voltage needs to be increased, the clock signal controller controls the oscillator to increase the frequency of the clock signal in response to the trim control signal. Circuit. The high voltage generation of the flash memory device as claimed in claim 12, wherein when the voltage level of the high voltage needs to be lowered, the clock signal controller controls the oscillator to decrease the frequency of the clock signal in response to the trim control signal. Circuit. The method of claim 12, wherein the at least one reference voltage includes a second reference voltage and a third reference voltage having a lower voltage level than the second reference voltage, wherein the at least one comparison signal includes a first comparison signal and a second comparison voltage. And a comparison signal, wherein the first comparison signal is applied to the clock control signal part when the voltage level of the high voltage is higher than the voltage level of the second reference voltage, and according to the clock control signal, the frequency of the clock signal. The high voltage generating circuit of the flash memory device, characterized in that is increased. 13. The method of claim 12, wherein when the voltage level of the high voltage is lower than the voltage level of the second reference voltage, the second comparison signal is applied to the clock signal controller, and the frequency of the clock signal according to the clock control signal. The high voltage generating circuit of the flash memory device, characterized in that is reduced. A memory cell array consisting of a plurality of memory cells; A high voltage generation circuit generating a plurality of high voltages to be applied to the memory cell array in accordance with an operation mode; And A selection circuit for selecting one of the plurality of high voltages and applying the selected voltage to the memory cell array; The high voltage generation circuit changes the frequency of a clock signal for generating the high voltages according to a result of comparing the voltage levels of the high voltages applied to the memory cell array with one or more reference voltages according to the operation mode, thereby changing the voltage levels of the high voltages. Flash memory device, characterized in that for changing. The method of claim 17, wherein the high voltage generating circuit, A high voltage regulator which compares the divided voltage obtained by dividing the high voltage with a first reference voltage of the at least one reference voltage and provides a control signal selectively activated according to the result; A high voltage detector comparing the high voltage with a second reference voltage and a third reference voltage among the at least one reference voltage and providing a first comparison signal and a second comparison signal according to a result of the comparison; A clock signal controller configured to provide a clock control signal for changing a frequency of the clock signal in response to the first comparison signal and the second comparison signal; An oscillator for generating the clock signal whose frequency varies in accordance with the clock control signal; A pumping clock controller which provides a pumping clock by blocking or passing the clock signal in response to the control signal; And And a charge pump that pumps continuously while the pumping clock is applied to generate the high voltage. The method of claim 17, wherein the high voltage generating circuit, A high voltage regulator for comparing the divided voltage obtained by dividing the high voltage with a first reference voltage among the at least one reference voltage, and providing a control signal selectively activated according to the result; A trim block configured to provide a trim control signal in response to trim information applied from the outside when it is necessary to change the voltage level of the high voltage; A clock signal controller providing a clock control signal for varying a frequency of the clock signal in response to the trim control signal or the at least one comparison signal or the trim control signal and the at least one comparison signal; An oscillator for generating the clock signal whose frequency varies in accordance with the clock control signal; A pumping clock controller which provides a pumping clock by blocking or passing the clock signal in response to the control signal; And And a charge pump that pumps continuously while the pumping clock is applied to generate the high voltage. The method of claim 17, wherein the high voltage generation circuit, A high voltage detector comparing the high voltage with a second reference voltage and a third reference voltage among the at least one reference voltage and providing a first comparison signal and a second comparison signal according to a result of the comparison; A high voltage regulator which compares the divided voltage obtained by dividing the high voltage with a first reference voltage of the at least one reference voltage and provides a control signal selectively activated according to the result; A trim block configured to provide a trim control signal in response to trim information applied from the outside when it is necessary to change the voltage level of the high voltage; A clock signal controller providing a clock control signal for varying a frequency of the clock signal in response to the trim control signal or the at least one comparison signal or the trim control signal and the at least one comparison signal; An oscillator for generating the clock signal whose frequency varies in accordance with the clock control signal; A pumping clock controller which provides a pumping clock by blocking or passing the clock signal in response to the control signal; And And a charge pump that pumps continuously while the pumping clock is applied to generate the high voltage.

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