KR20090115474A - Thin film transistor and fabricating method of the same - Google Patents

Abstract

PURPOSE: A thin film transistor and a manufacturing method thereof are provided to connect a gate electrode material with a amorphous silicon layer through a contact hole included in the thin film transistor. CONSTITUTION: A gate electrode(108) is located on surface a gate insulating film. An interlayer insulating film(109) is located on the gate electrode and includes the second contact hole. The second contact hole exposes a predetermined area of the semiconductor layer exposed by the first contact hole. Source and drain electrodes(112,113) are located on the interlayer insulating film and are electrically connected with the semiconductor layer through the first and second contact holes.

Description

Thin film transistor and its manufacturing method {Thin film transistor and fabricating method of the same}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor and a method for manufacturing the same, wherein the semiconductor layer of the thin film transistor is formed from a polycrystalline silicon layer crystallized by high heat generated by Joule heating by applying an electric field to a gate electrode material. By connecting the gate electrode material and the amorphous silicon layer through a contact hole included in the insulating layer, arc generation that may occur during crystallization may be prevented without introducing a separate mask for removing a predetermined region of the gate insulating layer. The present invention relates to a thin film transistor and a method for manufacturing the same, which can reduce manufacturing costs and simplify a process.

In general, amorphous silicon (a-Si) has disadvantages of low mobility and opening ratio of electrons, which are charge carriers, and incompatibility with CMOS processes. On the other hand, in the poly-silicon thin film device, it is possible to configure a driving circuit on the substrate like the pixel TFT-array, which is necessary for writing an image signal to the pixel, which was not possible in the amorphous silicon TFT (a-Si TFT). . Therefore, in the polycrystalline silicon thin film element, the connection between the plurality of terminals and the driver IC becomes unnecessary, thereby increasing productivity and reliability and reducing the thickness of the panel. In addition, in the polycrystalline silicon TFT process, since the microfabrication technology of silicon LSI can be used as it is, a microstructure can be formed in wiring etc. Therefore, since there is no pitch constraint on the TAB mounting of the driver IC seen in the amorphous silicon TFT, pixel reduction is easy and a large number of pixels can be realized with a small field of view. The thin film transistor using polycrystalline silicon in the active layer has a high switching capability and the channel position of the active layer is determined by self-matching, compared with the thin film transistor using amorphous silicon, so that device miniaturization and CMOS are possible. For this reason, polycrystalline silicon thin film transistors are used as pixel switch elements in active matrix type flat panel displays (e.g., liquid crystal displays, organic ELs), and the like. It is emerging as a major device.

The inventors of the present invention as a method of crystallizing an amorphous silicon layer into a polycrystalline silicon layer in Korean Patent Application No. 2004-74493, forming an insulating layer on the amorphous silicon layer, and then forming a conductive layer on the insulating layer By applying an electric field to the conductive layer to induce Joule heating to generate high heat, such a high temperature at a lower temperature than conventionally, preferably at room temperature, very short time without damaging the substrate A method for better crystallization and dopant activation, thermal oxide process, and crystal lattice defect healing was proposed. In Korean Patent Application No. 2005-62186, a portion of the insulating layer is removed by removing a portion of the insulating layer in a method for preventing arc generation due to dielectric breakdown of the insulating layer due to a potential difference between the amorphous silicon layer and the conductive layer. And a method of directly contacting the conductive layer.

When the crystallization method is introduced into a thin film transistor manufacturing process, a gate electrode material may be used as a conductive layer and a gate insulating film may be used as an insulating layer without forming a separate conductive layer. In this case, the gate insulating film may be used to prevent arc generation. It is desirable to remove a portion of the gate electrode material so that the amorphous silicon layer is in direct contact with the gate electrode material. However, for this purpose, if a part of the gate insulating film is removed at a position other than the contact hole, a separate mask is required.

The present invention is to solve the above-mentioned problems of the prior art, in forming a semiconductor layer of a thin film transistor with a polycrystalline silicon layer crystallized by the high heat generated by the joule heating by applying an electric field to the gate electrode material, By connecting the gate electrode material and the amorphous silicon layer through a contact hole included in the thin film transistor, an arc may be generated during crystallization without introducing a separate mask for removing a certain region of the gate insulating film. It is possible to prevent the generation of arcs that can occur during crystallization without introducing a separate mask for removing a certain area of the gate insulating film, which can reduce manufacturing costs and simplify the process. A thin film transistor and a method of manufacturing the same.

The present invention is a substrate; A semiconductor layer on the substrate, the semiconductor layer comprising a Joule heating polycrystalline silicon layer; A gate insulating layer on the semiconductor layer, the gate insulating layer including a first contact hole exposing a predetermined region of the semiconductor layer; A gate electrode on the gate insulating layer; An interlayer insulating layer disposed on the gate electrode and including a second contact hole exposing a predetermined region of the semiconductor layer exposed by the first contact hole; And source and drain electrodes on the interlayer insulating layer, the source and drain electrodes electrically connected to the semiconductor layer through the first contact hole and the second contact hole, wherein a predetermined region forming a side surface of the first contact hole is formed. Provided is a thin film transistor, which is an interlayer insulating film.

The present invention also provides a substrate, an amorphous silicon layer is formed on the substrate, the amorphous silicon layer is patterned, a gate insulating film is formed over the substrate, and a predetermined region of the amorphous silicon layer is formed on the gate insulating film. Forming a first contact hole to expose the gate electrode, forming a gate electrode material on the gate insulating film on which the first contact hole is formed, and applying an electric field to the gate electrode material to apply the patterned amorphous silicon layer to polycrystalline silicon by Joule heating Crystallization into a layer, patterning the gate electrode material to form a gate electrode, forming an interlayer insulating film on the entire surface of the substrate on which the gate electrode is formed, and the amorphous silicon layer exposed by the first contact hole in the interlayer insulating film Forming a second contact hole exposing a predetermined region of the first contact hole; And forming source and drain electrodes electrically connected to the source and drain regions of the semiconductor layer through the second contact hole, respectively.

According to the present invention, in forming a semiconductor layer of a thin film transistor with a polycrystalline silicon layer crystallized by high heat generated by Joule heating by applying an electric field to a gate electrode material, the contact hole included in the thin film transistor is used to form the semiconductor layer. By connecting the gate electrode material and the amorphous silicon layer, it is possible to prevent arc generation that may occur during crystallization without introducing a separate mask for removing a certain region of the gate insulating film, the gate in which the contact hole is formed By performing an impurity doping process in the source / drain regions of the semiconductor layer using the insulating film and the gate electrode as masks, a separate mask for doping is not required, thereby reducing manufacturing costs and simplifying the process.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the drawings, but the scope of the present invention is not limited thereto.

1A to 1H are cross-sectional views illustrating a process of manufacturing a thin film transistor according to a first embodiment of the present invention.

Referring to FIG. 1A, a buffer layer 101 is formed on a substrate 100 such as glass or plastic. The buffer layer 101 is formed as a single layer or a plurality of layers thereof by using an insulating film such as a silicon oxide film or a silicon nitride film by using chemical vapor deposition or physical vapor deposition. At this time, the buffer layer 101 serves to prevent the diffusion of moisture or impurities generated in the substrate 100, or to control the heat transfer rate during crystallization, so that the amorphous silicon layer can be crystallized well. The buffer layer 101 may be formed to a thickness of 2000 to 5000Å.

Subsequently, an amorphous silicon layer 102 is formed on the substrate 100 on which the buffer layer 101 is formed. The amorphous silicon layer 102 may be formed by, for example, low pressure chemical vapor deposition, atmospheric pressure chemical vapor deposition, plasma enhanced chemical vapor deposition (PECVD), sputtering, vacuum evaporation, or the like. PECVD method is used. The amorphous silicon layer 102 may be formed to a thickness of 500 to 2000Å.

Subsequently, referring to FIG. 1B, the amorphous silicon layer 102 is patterned such that the amorphous silicon layer 102 has a semiconductor layer shape of a thin film transistor.

Subsequently, a gate insulating layer 104 is formed on the patterned amorphous silicon layer 103. The gate insulating layer 104 serves to insulate the gate electrode and the semiconductor layer, and the patterned amorphous silicon layer 103 is contaminated by the gate electrode material when the patterned amorphous silicon layer 103 is crystallized by Joule heating. It can play a role in preventing it. The gate insulating film 104 may be formed of a silicon oxide film or a silicon nitride film, and may be formed to a thickness of 500 to 2000 Å.

Subsequently, a predetermined region of the gate insulating layer 104 is etched to expose a predetermined region of the patterned amorphous silicon layer 103 to be formed as a source / drain region of the semiconductor layer, thereby forming a first contact in the gate insulating layer 104. The hole 105 is formed.

Subsequently, referring to FIG. 1C, a gate electrode material 106 is formed on the entire surface of the substrate 100 on which the gate insulating layer 104 is formed. Subsequently, an electric field is applied to the gate electrode material 106 to crystallize the patterned amorphous silicon layer 103 by Joule heating to form a polycrystalline silicon layer. This forms a semiconductor layer (107 in FIG. 1D) formed of a polycrystalline silicon layer by Joule heating.

Here, the patterned amorphous silicon layer 103 is applied by the joule heating by applying an electric field to the gate electrode material 106 with the gate insulating film 104 interposed on the patterned amorphous silicon layer 103. In the case of crystallizing with this polycrystalline silicon layer, the polycrystalline silicon layer may exhibit conductivity at high temperatures. In this case, the polycrystalline silicon layer and the gate electrode material 106 and the gate insulating film 104 interposed therebetween form a capacitor, and the potential difference generated at this time exceeds the dielectric breakdown voltage of the gate insulating film 104. In this case, an electric current may flow through the gate insulating layer 104 to generate an arc.

However, in the present invention, the gate electrode material 106 and the polycrystalline silicon layer may be directly contacted through the first contact hole 105 formed in the gate insulating layer 104 while applying an electric field to the gate electrode material 106. By electrical connection, it is possible to prevent the generation of arc. In addition, in the present invention, in the manufacture of the thin film transistor, by using the first contact hole 105 for the electrical connection between the source and drain electrodes and the semiconductor layer to prevent the occurrence of arc, the gate electrode material 106 and the patterning In order to directly contact the amorphous silicon layer 103, a separate mask for removing a predetermined region of the gate insulating layer 104 may not be introduced, thereby reducing manufacturing costs and simplifying the process.

The application of the electric field to the gate electrode material 106 is done by applying energy of a power density that can generate by Joule heating a high heat sufficient to induce crystallization of the amorphous silicon layer 103. Since the application of the electric field is determined by various factors such as resistance, length, thickness, etc. of the gate electrode material 106, it is difficult to be specified, but about 100 W / cm ² to 1,000,000 W / cm ² It is about 100,000 W / cm ² -, and preferably about 1000 W / cm ^2. The applied current may be direct current or alternating current. The application time of the electric field may be 1 / 10,000,000 to 1 second, which is continuously applied, preferably 1 / 100,000 to 1/10 second. The application of this electric field can be repeated several times in regular or irregular units.

On the other hand, since the amorphous silicon layer 103 is relatively thin compared to the substrate 100, the thermal conductivity from the gate electrode material 106 heated to a high temperature in a short time is the temperature of the amorphous silicon layer 103. However, since the overall thickness is low, the substrate 100 having a thick thickness cannot be heated to a high temperature, so that despite the high heat that the heat treatment of the amorphous silicon layer 103 can be performed, It does not cause thermal deformation of the substrate 100.

Application of the electric field to the gate electrode material 106 is preferably applied to the extent that high heat of 1100 ° C. or more occurs. When the crystallization is performed at a high temperature of less than 1100 ° C., crystallization may not be completed by applying a single electric field for a short time of about 1 / 1,000,000 to 1 second. Then, the electric field application process must be repeated several times. In this case, in order to prevent the occurrence of non-uniformity due to accumulated heat, it is necessary to leave the electric field application for several seconds after the electric field application is completed once. As a result, the total process time for crystallization can reach several minutes.

However, when the crystallization is performed at a high temperature of 1100 ° C. or higher, crystallization may be completed by one electric field application, and the time required for one electric field application is very short, such as several hundreds of microseconds. Therefore, when the crystallization is performed at a high temperature of 1100 ° C or higher, the total process time for crystallization can be significantly reduced. In addition, crystallization may be improved by crystallizing a single electric field in a short process time at a high temperature.

As described above, in order to secure the stability of the gate electrode material 106 at a high temperature of 1100 ° C or higher, the gate electrode material 106 may be formed using a metal or an alloy having a melting point of 1100 ° C or higher. The metal or alloy having the melting point of 1100 ° C. or more includes molybdenum (Mo), titanium (Ti), chromium (Cr), or molybdenum (MoW).

In addition, when an electric field generating high heat of 1100 ° C. or more is applied to the gate electrode material 106 for a very short time of 0.1 to 300 kPa, tension is applied to the amorphous silicon layer 103 during crystallization by Joule heating, thereby crystallizing. Peak value of the Raman spectrum of the polycrystalline silicon layer is shifted to the left than the conventional 518-520 cm ^-1 515-517 cm ^{- 1} . If the time for which the electric field is applied to the gate electrode material 106 is shorter than 0.1 ms, the amorphous silicon layer 103 may not be crystallized into a polycrystalline silicon layer. If it is longer than 300 ms, incontinence may occur in the silicon film during crystallization. Due to the incontinence, the tension applied to the amorphous silicon layer 103 may be alleviated so that the peak value of the Raman spectrum of the crystallized polycrystalline silicon film may not move to the left side than before. The polycrystalline silicon layer having the peak value of the Raman spectrum at 515-517 cm ⁻¹ has excellent resistance characteristics. The present invention, the peak value of the Raman spectrum due to crystallization caused by Joule heating from 515-517 cm ^- Joule a polycrystalline silicon layer that appears on the ^first is referred to as heating the polycrystalline silicon layer.

The gate electrode material 106 may be formed by a method such as sputtering or evaporation, and may be formed to a thickness of 500 to 3000 m 3.

Before applying an electric field to the gate electrode material 106, the substrate 100 may be preheated to an appropriate temperature range. The appropriate temperature range refers to a temperature range in which the substrate 100 is not damaged throughout the process, and is preferably a range lower than the heat deformation temperature of the substrate 100. The preheating method is not particularly limited, and for example, a method of putting in a general heat treatment furnace, a method of irradiating radiant heat such as a lamp, or the like may be used.

1D, the gate electrode material 106 is patterned to form a gate electrode 108 positioned corresponding to the region to be defined as a channel region of the semiconductor layer 108.

Subsequently, referring to FIG. 1E, an interlayer insulating layer 109 is formed over the entire surface of the substrate 100 including the gate electrode 108. The interlayer insulating layer 109 may be a silicon nitride film, a silicon oxide film, or a multilayer thereof.

Subsequently, a photo for forming a second contact hole (111 in FIG. 1F) exposing a predetermined region of the semiconductor layer 108 exposed by the first contact hole 105 on the interlayer insulating layer 109. The resist pattern 110 is formed. Subsequently, the interlayer insulating layer 109 is etched using the photoresist pattern 110 as a mask to form a second contact hole (111 in FIG. 1F) in the interlayer insulating layer.

1F, the photoresist pattern 110 is removed.

In the present invention, the first contact hole 105 is formed in the gate insulating film 104 to prevent arc generation during crystallization by Joule heating, rather than forming a contact hole by stacking the gate insulating film and the interlayer insulating film and collectively etching them. Is formed first, and then the interlayer insulating film 109 is formed. Then, the interlayer insulating layer 109 is formed in the first contact hole 105. When the interlayer insulating layer 109 is etched using the photoresist pattern 110 as a mask, after etching, the etch rate in the vertical direction is greater than that in the horizontal direction, and as shown in FIG. 1F after etching. The interlayer insulating layer 109 may be left in a predetermined region of the side surface of the first contact hole 105. This is because the first contact hole 105 is first formed in the gate insulating film 104 to prevent arc generation during crystallization by Joule heating as in the present invention.

As shown in FIG. 1G, the interlayer insulating layer 109 may cover the entirety of the side surface of the first contact hole 105 according to an etching condition. In addition, as illustrated in FIG. 1F, a line connecting side surfaces of the first contact hole 105 and the second contact hole 111 may have a step shape.

Subsequently, referring to FIG. 1H, the semiconductor layer 108 may be electrically connected to the semiconductor layer 108 through the first contact hole 105 and the second contact hole 111 formed in the gate insulating film 104 and the interlayer insulating film 109. Source / drain electrodes 112 and 113 are connected to each other, wherein the source / drain electrodes 112 and 113 are formed of molybdenum (Mo), chromium (Cr), tungsten (W), and aluminum-neodymium (Al-Nd). ), Titanium (Ti), molybdenum tungsten (MoW), and aluminum (Al) may be formed of any one, thereby completing a thin film transistor according to an embodiment of the present invention.

2 is a cross-sectional view of a thin film transistor according to a second exemplary embodiment of the present invention. Reference is made to the first embodiment above except as specifically mentioned below.

In the first embodiment, the case where the interlayer insulating layer 109 remains in a predetermined region of the side of the first contact hole 105 has been described. Alternatively, the interlayer insulating layer 109 is formed on the side of the first contact hole 105. The etching process may be performed so that no) remains. In this case, the taper angles of the first contact hole 1050 and the second contact hole 111 may be different from each other. In the present invention, the taper angle of the contact hole refers to an angle formed between the side surface of the contact hole and the horizontal plane of the film on which the contact hole is formed. The taper angle of the second contact hole 111 may be greater than the taper angle of the first contact hole 1050.

3 is a cross-sectional view of a thin film transistor according to a third exemplary embodiment of the present invention. Reference is made to those mentioned in the above examples, except as specifically mentioned below.

When the etching process is performed as in the second embodiment, a predetermined region of the upper surface of the semiconductor layer 108 under the first contact hole 105 may be over-etched. When a predetermined region of the upper surface of the semiconductor layer 108 is overetched, a groove 300 is formed in the upper surface of the semiconductor layer 108 under the first contact hole 105. In this case, the side surface of the groove 300 of the semiconductor layer 108, the side surface of the first contact hole 105, and the side surface of the second contact hole 111 may be formed in a step shape. .

4 is a cross-sectional view of an organic light emitting display device including a thin film transistor according to an embodiment of the present invention.

Referring to FIG. 4, an insulating film 400 is formed on the entire surface of the substrate 100 including the thin film transistor according to the exemplary embodiment of FIG. 1H. The insulating film 400 is any one selected from an inorganic film, a silicon oxide film, a silicon nitride film, or a spin-on glass film, or an organic film, polyimide, benzocyclobutene series resin, or acrylate. It may be formed of any one selected from. In addition, the inorganic film and the organic film may be formed in a laminated structure.

The insulating layer 400 is etched to form via holes exposing the source or drain electrodes 112 and 113. A first electrode 401 connected to any one of the source or drain electrodes 112 and 113 is formed through the via hole. The first electrode 401 may be formed as an anode or a cathode. When the first electrode 401 is an anode, the anode may be formed of a transparent conductive film made of any one of ITO, IZO, or ITZO, and in the case of a cathode, the cathode may be Mg, Ca, Al, Ag, Ba, or these. It can be formed using an alloy of.

Subsequently, a pixel definition layer 402 having an opening exposing a part of the surface of the first electrode 401 is formed on the first electrode 401, and a light emitting layer is formed on the exposed first electrode 401. An organic film layer 403 is formed. The organic layer 403 may further include one or a plurality of layers selected from the group consisting of a hole injection layer, a hole transport layer, a hole suppression layer, an electron suppression layer, an electron injection layer, and an electron transport layer. Subsequently, a second electrode 404 is formed on the organic layer 403. The second electrode 404 may be formed of an anode or a cathode. In the case of an anode, the second electrode 404 may be formed of a transparent conductive film made of any one of ITO, IZO, or ITZO. In the case of a cathode, Mg, Ca, Al, Ag may be used. , Ba or alloys thereof. This completes the organic light emitting display device according to the embodiment of the present invention.

Therefore, in forming the semiconductor layer of the thin film transistor with a polycrystalline silicon layer crystallized by the high heat generated by the joule heating by applying an electric field to the gate electrode material, the gate electrode material through the contact hole included in the thin film transistor. By connecting the silicon layer to the amorphous silicon layer, it is possible to prevent the generation of arcs that can occur during crystallization without introducing a separate mask for removing a certain region of the gate insulating film, thereby reducing the manufacturing cost and the process. Can be simplified.

1A to 1H are cross-sectional views illustrating a process of manufacturing a thin film transistor according to a first embodiment of the present invention.

2 is a cross-sectional view of a thin film transistor according to a second embodiment of the present invention.

3 is a cross-sectional view of a thin film transistor according to a third embodiment of the present invention.

4 is a cross-sectional view of an organic light emitting display device including a thin film transistor according to an embodiment of the present invention.

<Description of Symbols for Main Parts of Drawing>

100 substrate 101 buffer layer

102 amorphous silicon layer 104 gate insulating film

105: first contact hole 106: gate electrode material

107: semiconductor layer 108: gate electrode

109: interlayer insulating film 110: photoresist pattern

111: second contact hole 112,113: source / drain electrode

300 groove 400 400 insulating film

401: First electrode 402: Pixel defining layer

403: organic film layer 404: second electrode

Claims (19)

Board; A semiconductor layer on the substrate, the semiconductor layer comprising a Joule heating polycrystalline silicon layer; A gate insulating layer on the semiconductor layer, the gate insulating layer including a first contact hole exposing a predetermined region of the semiconductor layer; A gate electrode on the gate insulating layer; An interlayer insulating layer disposed on the gate electrode and including a second contact hole exposing a predetermined region of the semiconductor layer exposed by the first contact hole; And A source and drain electrode on the interlayer insulating layer, the source and drain electrodes electrically connected to the semiconductor layer through the first contact hole and the second contact hole; And the interlayer insulating layer is positioned at a predetermined region of the side surface of the first contact hole. The method of claim 1, And the interlayer insulating layer is located in an entire area of the side surface of the first contact hole. The method of claim 1, The thin film transistor according to claim 1, wherein a surface connecting the side surfaces of the first contact hole and the second contact hole has a step shape. The method of claim 1, The Joule heating polycrystalline silicon layer is the peak value of the Raman spectra 515-517 cm ^- thin-film transistor, characterized in that appearing on the ^first. The method of claim 1, The gate electrode may include molybdenum (Mo), titanium (Ti), chromium (Cr), or molybdenum tungsten (MoW). The method of claim 1, The substrate is a thin film transistor, characterized in that formed of a glass or plastic substrate. Board; A semiconductor layer on the substrate, the semiconductor layer comprising a Joule heating polycrystalline silicon layer; A gate insulating layer on the semiconductor layer, the gate insulating layer including a first contact hole exposing a predetermined region of the semiconductor layer; A gate electrode on the gate insulating layer; An interlayer insulating layer disposed on the gate electrode and including a second contact hole exposing a predetermined region of the semiconductor layer exposed by the first contact hole; And A source and drain electrode on the interlayer insulating layer, the source and drain electrodes electrically connected to the semiconductor layer through the first contact hole and the second contact hole; The taper angle of the first contact hole and the taper angle of the second contact hole are different from each other. The method of claim 7, wherein The taper angle of the second contact hole is larger than the taper angle of the first contact hole. The method of claim 7, wherein The Joule heating polycrystalline silicon layer is the peak value of the Raman spectra 515-517 cm ^- thin-film transistor, characterized in that appearing on the ^first. The method of claim 7, wherein The gate electrode includes molybdenum (Mo), titanium (Ti), chromium (Cr) or molybdenum ten (MoW). Board; A semiconductor layer on the substrate, the semiconductor layer comprising a Joule heating polycrystalline silicon layer; A gate insulating layer on the semiconductor layer, the gate insulating layer including a first contact hole exposing a predetermined region of the semiconductor layer; A gate electrode on the gate insulating layer; An interlayer insulating layer disposed on the gate electrode and including a second contact hole exposing a predetermined region of the semiconductor layer exposed by the first contact hole; And A source and drain electrode on the interlayer insulating layer, the source and drain electrodes electrically connected to the semiconductor layer through the first contact hole and the second contact hole; The groove is located in a predetermined region of the semiconductor layer exposed by the first contact hole, and the side connecting the side of the groove, the side of the first contact hole, and the side of the second contact hole has a step shape. Thin film transistor, characterized in that. The method of claim 11, The Joule heating polycrystalline silicon layer is the peak value of the Raman spectra 515-517 cm ^- thin-film transistor, characterized in that appearing on the ^first. The method of claim 11, The gate electrode may include molybdenum (Mo), titanium (Ti), chromium (Cr), or molybdenum tungsten (MoW). Providing a substrate, Forming an amorphous silicon layer on the substrate, Patterning the amorphous silicon layer, Forming a gate insulating film on the entire surface of the substrate, Forming a first contact hole in the gate insulating layer to expose a predetermined region of the amorphous silicon layer, Forming a gate electrode material on the gate insulating film on which the first contact hole is formed, Applying an electric field to the gate electrode material to crystallize the patterned amorphous silicon layer into a polycrystalline silicon layer by Joule heating, Patterning the gate electrode material to form a gate electrode, An interlayer insulating film is formed over the entire substrate on which the gate electrode is formed; Forming a second contact hole in the interlayer insulating layer to expose a predetermined region of the amorphous silicon layer exposed by the first contact hole, And forming source and drain electrodes electrically connected to the source and drain regions of the semiconductor layer through the first contact hole and the second contact hole, respectively. The method of claim 14, And the gate electrode material and the amorphous silicon layer or the polycrystalline silicon layer are electrically connected through the first contact hole during crystallization. The method of claim 14, A thin film, characterized in that the peak value of the Raman spectrum of the crystallized polycrystalline silicon layer appears at 515-517 cm ^-1 by applying an electric field to the gate electrode material for 0.1 to 300 kV to apply tension to the amorphous silicon layer. Method for manufacturing a transistor. The method of claim 16, A method of manufacturing a thin film transistor, characterized in that the temperature applied to the amorphous silicon layer is 1100 ℃ or more. The method of claim 14, And preheating the substrate before applying an electric field to the gate electrode material. The method of claim 14, Forming a second contact hole in the interlayer insulating layer to expose a predetermined region of the amorphous silicon layer exposed by the first contact hole Forming a photoresist pattern on the interlayer insulating film, And etching the interlayer insulating film using the photoresist pattern as a mask.

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