KR20090110605A - Non-volatile memory device having dummy cell and program method thereof - Google Patents

Abstract

PURPOSE: A non-volatile memory device having dummy cell and program method thereof are provided to increase the boosting efficiency of the string for which a program is disabled. CONSTITUTION: The non-volatile memory device including the dummy cell includes the selecting transistor, and the memory cell and dummy cell. The selecting transistor is connected to the bit line. The memory cell is serially connected to the selecting transistor. The dummy cell is positioned between a plurality of memory cells. The dummy cell has the threshold voltage corresponding to the highest state.

Description

A nonvolatile memory device including a dummy cell and a program method thereof The present invention relates to a nonvolatile memory device including a dummy cell.

The present invention relates to a semiconductor memory device, and more particularly to a nonvolatile semiconductor memory device having a dummy cell.

In general, NAND flash memories use a tunneling phenomenon to program and erase charges in a manner of storing charges in a floating gate or releasing charges stored in a floating gate into a channel. The above-described program and erase method satisfies the excellent preservation of stored data, and thus is suitable as a nonvolatile memory. In addition, flash memory has high integration, low power consumption, and strong durability against external shock, and thus its use is increasing in auxiliary storage devices and other applications of mobile devices. In particular, in recent years, NAND flash memory has rapidly emerged as an alternative memory of an auxiliary storage device such as a large capacity hard disk. This change is a high-capacity storage device for computer systems and portable devices, compared to magnetic disk devices such as hard disks (HDDs). Semiconductor disk devices are disadvantageous in terms of storage capacity and cost, but have advantages such as access speed, miniaturization, and stability from impact. Because it is occupied. In addition, with advances in process technology and design technology, the storage capacity and cost of semiconductor disks are expected to increase gradually. In the near future, semiconductor disks will replace magnetic disks.

However, inevitable physical barriers are associated with increasing process density. In particular, in the case of a NAND flash memory in which a high voltage is applied to a word line in a program operation, the coupling effect increases as the physical spacing between word lines becomes denser as the density increases. In addition, when the cell is fabricated to include more cells in a string, which is a unit of memory cells connected in series to share one bit line, the boosted channel charge is leaked to the channels of neighboring cells. (Charge Sharing) phenomenon occurs. Due to the drop in the channel voltage due to charge sharing of the channel charges, the phenomenon in which the unselected cells are programmed may occur.

1 is a circuit diagram illustrating a cell string structure of a general flash memory. Referring to FIG. 1, one cell string includes 32 memory cells MC <0> to MC <31> between a string selection transistor (SST) and a ground selection transistor (GST). ) Are connected in series. Word lines WL <0> to WL <31> are connected to gates of the memory cells. Each of the selection transistors SST and GST for selecting a cell string is connected to a bit line BL and a common source line CSL. A string selection line (SSL) is connected to the gate of the SST, and a ground selection line (GSL) is connected to the gate of the GST.

One of the techniques for programming the memory cell 10 shown in the drawings and program inhibiting the memory cells MC <30> of adjacent strings connected to the same word line is a self-boosting scheme. ). According to the program prohibition method using the self-boosting scheme, as shown, 0V is applied to the gate of the GST to block the ground path. The ground voltage 0V is applied to the bit line BL <m>, and the power supply voltage Vcc is applied to the bit line BL <m + 1>. At the same time, after the power source voltage Vcc is applied to the gate of the SST, the source of the SST is charged up to (Vcc-Vth) (Vth is the threshold voltage of the SST), and in effect, the SST is cut off. Under these conditions, the channel of the program inhibited cell transistor is boosted by applying the program voltage Vpgm to the select word line WL <30> and the pass voltage Vpass to the unselected word line. This condition prevents the potential difference between the floating gate and the channel of the memory cell MC <30> from forming an electric field such that F-N tunneling occurs. As a result, the program inhibited memory cell MC <30> maintains its previous state. However, in such a self-boosting scheme, when the number of memory cells included in one string increases, charges induced in a channel of the program inhibited memory cell MC <30> may be reduced. Increase the amount of charge sharing leaking into the channel. As the charges induced in the channel of the program inhibited cell MC <30> are leaked by the above-described charge sharing, the channel potential of the cell MC <30> is lowered. The lowering of the channel potential means that the strength of the electric field between the floating gate and the channel of the program forbidden cell MC <30> to which the program voltage Vpgm is applied to the control gate is increased. This condition causes the program inhibited cell MC <30> to be programmed. Arrows on the right side of FIG. 1 indicate the direction of program progress and the direction in which charge sharing occurs. The method which appeared to solve this problem is a program banning method by Local Self-boosting Scheme. According to local self-boosting, a voltage of 0V is applied to the two unselected word lines adjacent to the select word line. The pass voltage Vpass is applied to the remaining unselected word lines, and then the program voltage Vpgm is applied to the selected word lines. Under these bias conditions, the channel of the program inhibited cell transistor with the program voltage applied to the control gate is boosted, and the channel of two adjacent cell transistors with the pass voltage Vpass applied to the control gate leaking (or leaking) the boosted charge. Charge sharing). As a result, the program voltage is applied and the channel voltage of the cell transistor which is program inhibited is maintained, which is F-N tunneling does not occur and is program inhibited. However, the above-described program prohibition method by local self-boosting causes a problem due to coupling in a flash memory in which a high voltage is applied to a word line as the degree of integration increases. Due to the high degree of integration, the spacing between word lines is narrowed, and the coupling ratio is increased between the selected word line to which the program voltage Vpgm is applied and the adjacent word lines to which 0V is applied. The unselected word line to which 0 V is applied is increased from the select word line to which the program voltage Vpgm is applied due to the coupling effect. This phenomenon causes the memory cells on the unselected word line to turn on to form a channel and creates a condition in which the boosted charge of the program inhibited cell on the selected word line is likely to leak to the remaining cells. . Therefore, as the spacing between word lines is narrowed, the blocking effect of charge sharing by local self-boosting is difficult to expect due to the coupling between word lines.

2 is a cross-sectional view of a cell string structure for explaining the charge sharing described above. Referring to FIG. 2, the power supply voltage Vcc is applied to the SST and the bit line BL <m + 1>, 0V to the GST, and to the gate of the program inhibited memory cell MC <30> connected to the selected word line. The pass voltage Vpass is applied to the gates of the memory cells to which the program voltage Vpgm is connected to the remaining unselected word lines. Under the above bias condition, charges are charged to the channel of the memory cell MC <30> by self-boosting and boosted to a higher charge density than the channel of the remaining unselected memory cells. However, the cells MC <0 to 29> are turned on since the pass voltage Vpass is applied to the gate, and a channel will be formed. In particular, in the cells MC <0 to 29> that are programmed to a low state or maintain an erase state, the width of the channel formed by the application of the pass voltage Vpass will also be relatively large. The channel capacities of the cells MC <0 to 29> formed according to these conditions share the channel charges of the select transistor MC <30>, which is program inhibited by boosting. Of course, when the above-described memory cells are multi-level cells (hereinafter referred to as MLC), the degree of formation of the channel may vary according to the program state of each memory cell. Such a problem of charge sharing becomes particularly a problem in NAND flash memory in which a program proceeds in the SST direction starting from the word line WL <0>. That is, the more cells adjacent to the SST in the string, the greater the likelihood of charge sharing with cells programmed to various previous states when the program is inhibited. This is because the number of cells programmed in a state that can cause charge sharing increases even if the cell adjacent to the SST is biased to be program inhibited.

FIG. 3 is a diagram for explaining a drop in channel potential of the program inhibited memory cell MC <30> described with reference to FIG. Initially, upon biasing for self-boosting of SST and GST, the channel potential is boosted to (Vcc-Vth). When a program voltage is applied to the word line (at time t1), the channel potential of the program inhibited memory cell MC <30> is preferably boosted to a relatively high Vch1 so that F-N tunneling cannot occur. However, due to the above-described charge sharing, the charge of the channel will leak into the channel of the programmed cells, and as a result, the channel potential will be lowered to Vch2. If the Vch2 potential is a channel potential that is not high enough to prevent F-N tunneling, then the worst problem will arise where the program inhibited memory cell MC <30> is programmed.

In view of the problem that the program inhibited cell caused by the above-mentioned charge sharing is programmed, a pass voltage Vpass has been set in the self-boosting scheme. In addition, in the local self-boosting scheme, a voltage of 0V is applied to two word lines adjacent to the selected word line, thereby minimizing charge sharing. However, as the density increases, the spacing between word lines decreases, making it difficult to apply local self-boosting. In addition, when the self-boosting scheme is applied, the setting of the pass voltage Vpass applied to the unselected word lines does not prevent charge sharing as the number of memory cells included in one string increases. There was a problem that was not appropriate. Like the method of applying the pass voltage Vpass to the unselected word line, it is difficult to solve the charge sharing problem caused by the increase in the number of memory cells in the string by only adjusting the voltage of the word line.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems, and an object of the present invention is to provide an apparatus and a method for increasing program reliability of a highly integrated NAND flash memory.

According to an aspect of the present invention, there is provided a nonvolatile memory device including: a selection transistor connected to a bit line; A plurality of memory cells connected in series with the selection transistor; And at least one dummy cell positioned between the plurality of memory cells, wherein the dummy cell is turned off during a program operation of a memory cell positioned between the dummy cell and the selection transistor.

A nonvolatile memory device of the present invention for achieving the above object, the selection transistor is connected to the bit line; A plurality of memory cells connected in series with the selection transistor; And at least one dummy cell positioned between the plurality of memory cells, wherein during the program operation, the dummy cell is selectively turned off according to a position of a programmed memory cell among the plurality of memory cells. .

According to another aspect of the present invention, there is provided a method of programming a flash memory device, the method including: (a) floating a channel of a program prohibited cell string; And (b) boosting the floated channel into a plurality of channel regions, each of the plurality of channel regions including at least one dummy cell positioned between a plurality of memory cells included in the cell string. To isolate.

In accordance with another aspect of the present invention, a memory system includes: a string select transistor connected to a bit line; A plurality of memory cells connected to the string select transistor and each connected in series; And at least one dummy cell positioned between the plurality of memory cells, wherein the dummy cell is turned off during a program operation of a memory cell closer to the string select transistor than the dummy cell. Device; And a memory controller for controlling the nonvolatile memory device.

A nonvolatile memory device of another aspect of the present invention for achieving the above object comprises a selection transistor connected to a bit line; A plurality of memory cells connected in series with the selection transistor; And at least one dummy cell positioned between the plurality of memory cells, wherein during the program operation, the dummy cell is selectively turned off according to a position of a programmed memory cell among the plurality of memory cells. Nonvolatile memory devices; And a memory controller for controlling the nonvolatile memory device.

According to the apparatus and method according to the present invention as described above, the flash memory device including the dummy word line according to the present invention can block the program disturb problem by increasing the boosting efficiency of the program inhibited string.

It is to be understood that both the foregoing general description and the following detailed description are exemplary, and that additional explanations of the claimed invention are provided. Reference numerals are shown in detail in preferred embodiments of the invention, examples of which are shown in the reference figures. In any case, like reference numerals are used in the description and the drawings to refer to the same or like parts.

In the following, a NAND type flash memory device is used as an example for explaining the features and functions of the present invention. However, one of ordinary skill in the art will readily appreciate the other advantages and performances of the present invention in accordance with the teachings herein. The present invention may be implemented or applied through other embodiments as well. In addition, the detailed description may be modified or changed according to aspects and applications without departing from the scope, technical spirit and other objects of the present invention. Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

4 is a circuit diagram of a cell string including a configuration for minimizing charge sharing according to the present invention. Referring to FIG. 4, in the cell string structure 30 of the present invention, a dummy cell DMC is designated among memory cells. The dummy cell DMC minimizes the sharing of charge induced by boosting the channel of the program inhibited memory cell.

The dummy cell DMC of the present invention is a cell transistor whose operation characteristic is the same as that of the remaining memory cells. In general, in a standard in which 32 word lines are designated per block, 32 word lines are connected to control gates of a memory cell. However, in the cell string 30 according to the present invention, at least one memory cell is further added, so that an appropriate memory cell may be selected as the dummy cell DMC among the increased memory cells (for example, 33 memory cells in total). Can be. The selection of the dummy cell DMC is preferably selected as the cell immediately before the cell in which the program voltage Vpgm is applied and the program inhibited program starts to deteriorate rapidly due to the problem of charge sharing.

Referring back to FIG. 4, in the memory block of the present invention, the memory cell between the word line WL <N> and the word line WL <N-1> is designated as the dummy cell DMC, and the dummy cell DMC ) Is designated as a dummy word line (DWL). The selection of the dummy word line DWL is because the program prohibition characteristic becomes undesirably due to charge sharing from the word line WL <N>. Since these characteristics are generally highly dependent on the manufacturing process, the optimal location of the dummy cell during the test process can be evaluated and stored in a fuse program or other nonvolatile storage device. The dummy cell is always programmed to the highest state after the erase operation in the mounting environment. In addition, during a program operation, a voltage equal to or lower than an unselected word line may be applied to the dummy word line DWL. Charge sharing may be minimized even in the cell string structure of the NAND flash memory having a high degree of integration through the above-described application voltage configuration of the dummy word line DWL. Therefore, a phenomenon in which the program voltage Vpgm is applied and the program inhibited cell is programmed can be minimized.

5 is a block diagram schematically illustrating a flash memory device including an optional dummy word line (DWL) of the present invention. Referring to FIG. 5, the flash memory device according to the present invention refers to the dummy word line information DWL_DATA stored in the fuse box 110 such that the same voltage as the unselected word line is applied to the dummy word line during program / read. Is set. In erasing, after block erasing is completed, the dummy cells 171 are programmed to the highest state.

The fuse box 110 stores position information of a word line designated as a dummy word line among the word lines in each block. Word lines designated as dummy word lines in one block may be changed according to a semiconductor manufacturing process. Therefore, the position of the word line where the program prohibition characteristic due to charge sharing starts to deteriorate to an undesirable level can be designated as the position of the dummy word line. The position of such dummy word lines is evaluated in the test process, and the evaluated information for specifying the position of the dummy word lines is stored in the fuse box 110 by the fuse program. However, although the fuse box 110 is exemplarily disclosed as a means for storing the position information of the dummy word line in the present embodiment, it is well known to those who have acquired the general knowledge in this field. In other words, the fuse box 110 may be replaced with other nonvolatile memories or registers.

The address buffer 120 temporarily stores an address from the outside and transmits the address to the free decoder 130.

The predecoder 130 converts the row address R_ADD input from the outside into the row address DR_ADD including the dummy word line by referring to the dummy word line information DWL_DATA from the controller 140 which will be described later. -To the decoder 150. The predecoder 130 refers to the dummy word line information DWL_DATA and converts it into an internal address DR_ADD having a word line increased by one more than the number of word lines defined in the row address R_ADD from the outside. If the number of externally defined word lines is 32 per block, the predecoder 130 will generate an internal address DR_ADD including the dummy word line DWL in the 32 word lines. If there are 16 word lines per block, the predecoder 130 will generate an internal address DR_ADD to the X-decoder 150 so that there are 17 word lines per block. The number of word lines specified per block is not limited to the above description, and various modifications are possible for those skilled in the art.

The controller 140 receives dummy word line information DWL_DATA from the fuse box 110 and controls all memory operations such as programming, erasing, and reading of the memory block including the dummy word line. The controller 140 controls the program to be sequentially programmed starting from the word line WL <0> during programming. In addition, when the program sequence of the dummy word line DWL is reached, the controller 140 controls the predecoder 130 so that the program operation is omitted and the program sequence jumps to the upper word line. When reading, the controller 140 controls the driver 160 to always apply the same voltage to the dummy word line DWL as the unselected word line as in the above-described program operation. In the erase operation, the controller 140 applies 0V to the dummy word line DWL like the other word lines and applies an erase voltage (for example, 18V) to the P-well. Clear the block. After the erase operation, the dummy word line DWL is selected under the control of the controller 140, and the dummy cells DMC of the selected dummy word line DWL are programmed to have the highest state. In this case, the page buffer stage 180 may be controlled to bias the bit line to the ground level Vss so that all the dummy cells DMC of the dummy word line DWL are programmed. The controller 140 controls the predecoder 130 and the driver 160 with reference to the dummy word line information DWL_DATA to program and read a row address (R_ADD: address for 32 word lines) applied from the outside. Operations such as, erase, etc. are configured.

The X-decoder 150 receives the internal row address DR_ADD from the predecoder 130 and selects a block corresponding to the internal row address DR_ADD and each word line included in the block. The block corresponding to the internal row address DR_ADD is selected by controlling the high voltage switches PS0 to PS34 through the block select line BSL. The X-decoder 150 transmits an internal row address to the driver 160 to select a total of 33 word lines WL <0> to WL <31> and DWL and two selection lines SSL and GSL.

The driver 160 supplies the same voltage as the unselected word line to the dummy word line during programming in response to the control signal CNT from the controller 140. For example, the driver 160 applies the pass voltage Vpass to the dummy word line DWL while the driver 160 applies the program voltage Vpgm to the selected word line. In the verify operation, the driver 160 applies the verify voltage Vvfy to the selected word line and the read voltage Vread to the dummy word line DWL. In the read operation, the driver 160 applies the same voltage as the unselected word line to the dummy word line DWL.

On the other hand, during the erase operation, the driver 160 is controlled such that a voltage of 0V level identical to that of all word lines is applied to the dummy word line DWL. Under this bias condition, all cells in a block including dummy cells (DMCs) are erased. After erasing, the driver 160 programs the word line designated by the fuse box 110 to operate as the dummy word line DWL of the present invention in response to the control signal CNT of the controller 140. An operation of programming the dummy cells included in the dummy word line DWL will be referred to as a dummy cell program hereinafter. The dummy cell program may be included in an erase operation during the operation of the memory device. Under the control of the controller 140, the dummy cell program is implemented such that the dummy cells are programmed to the highest state among states of the memory cell. For example, in the case of a multi-level cell (MLC) in which two bits are stored per cell, a dummy word line program is performed in a state of [01] among the states of [11], [10], [00], and [01]. The dummy cell is initialized with a high threshold voltage.

The cell array 170 includes blocks of a cell string structure in which the dummy word line 171 of the present invention is added. In the drawing, only the strings included in one block are illustrated, but all the blocks included in the cell array 170 will have the same cell string structure as the illustrated block.

The page buffer stage 180 loads program data into bit lines during a program operation. The page buffer stage 180 includes a latch (not shown) corresponding to each of the bit lines of the cell array 170. During a read operation, the page buffer stage 180 senses data stored in a cell from a bit line of selected cells. The sensed data is transferred externally via a heat pass gate (not shown). On the other hand, the data to be programmed is temporarily stored during the program operation. That is, the page buffer stage 180 senses and latches data of the cell array. The page buffer stage 180 of the present invention sets the bit lines such that all memory cells included in the dummy word line are programmed to the highest state in the above-described dummy word line program operation. That is, during the dummy cell program operation, 0 V is applied to all bit lines in synchronization with the application of the program voltage Vpgm of the driver 160. The page buffer stage 180 allows the dummy cells included in the dummy word line DWL to be programmed to the highest state through the above-described bit line bias setting.

The memory device of the present invention having the above operation and function receives the same row address R_ADD as the conventional one from the outside. However, internally, all settings of the dummy word line DWL are controlled by generating the internal row address DR_ADD by the predecoder 130. In the program and read operation, the dummy word line DWL receives the same voltage from the driver 160 as the unselected word lines. In the erase operation, dummy cells are programmed and initialized to the highest state by a dummy cell program operation following a block erase operation.

6 is a diagram illustrating a dummy cell program scheme performed after the block erase operation of the present invention. Referring to FIG. 6, the dummy cell program of the present invention moves the threshold voltages of the dummy cells from the erase state [11] to the highest state [01]. Although the memory cell shown in the figure shows a multi-level cell in which two bits of data are stored per cell, the present invention is not limited thereto, and it is obvious to those skilled in the art. That is, in an erase operation, even if more than 3 bits of data are stored per cell, the cells included in the dummy word line will be programmed to the highest state. Although the dummy cell programmed to the highest state has the program voltage Vpgm applied to the adjacent word line and the pass voltage Vpass applied to the dummy word line, the charges charged in the channel of the memory cell of the selected word line are stored in the remaining cells. The amount of leakage (or charge sharing) into the channel can be minimized. If channel time of the cell programmed to the highest state is narrower than the channel of the cells programmed to the other states (11, 10, 00) upon application of the pass voltage (Vpass), charge sharing is blocked or It can be minimized. Therefore, in the string to which the program inhibit voltage is applied to the bit line, the dummy cell minimizes the charge sharing of the charge boosted to the channel of the cell to which the program voltage is applied to ensure the program inhibit operation.

FIG. 7 is a table for explaining application voltage conditions of word lines and select lines that the driver 160 of the present invention supplies for each operation.

In the program operation, the bias conditions are as follows. The program voltage Vpgm may be applied to the word line selected for the program. In addition, a pass voltage Vpass is applied to the unselected word line. The power supply voltage Vcc may be applied to the string select line SSL, and 0V may be applied to the ground select line GSL and the common source line CSL. In particular, the same pass voltage Vpass or lower than the above-described unselected word line may be applied to the dummy word line DWL. In addition, 0 V is applied to the bit line including the cell to be programmed, and a power supply voltage Vcc is applied to the bit line to maintain the erased state.

In the read operation, the bias conditions are as follows. A power supply voltage Vcc is applied to the string select line SSL and the ground select line GSL. 0V is applied to the common source line CSL. A read voltage Vrd is applied to the selected word line and a voltage sufficient to turn on memory cells in the non-selected word line and the dummy word line DWL. (Vread) is applied.

In the erase operation, the bias conditions are as follows. The bit line BL, the string select line SSL, the ground select line GSL, and the common source line CSL are maintained in a floating state. 0 V is applied to all word lines (including dummy word lines). An erase voltage Vera of 18V is applied to the P-well to bias the injection electrons in the floating gates of the word lines and the dummy word line to flow out of the channel by F-N tunneling.

The dummy cell program for initializing the dummy word line after the erase operation is further included in the present invention. The controller 140 of the present invention performs a dummy cell program for programming to the highest state only for the dummy cells DMC included in the dummy word line DWL after all the cells in the block are erased. In order to program the dummy cells DMC to the highest state, the page buffer stage 180 applies 0V to all bit lines in the block. The pass voltage Vpass is applied to all word lines except the dummy word line DWL, the program voltage is applied to the dummy word line, the power supply voltage Vcc is applied to the string select line SSL, and the ground select line GSL. And 0V are applied to the common source line CSL. In this case, the dummy cells DMC included in the dummy word line DWL in the block are programmed to the highest state, and the initialization setting of the dummy word line DWL is completed.

The control of the memory device including the dummy word line DWL having the above function is performed by the controller 140 controlling the driver 160 with reference to the dummy word line information DWL_DATA programmed in the fuse box 110. Is implemented. Through such internal control, the external device can interface to a general memory that does not include the dummy word line (DWL).

8 is a flowchart for explaining the above-described erase operation and dummy cell program operation. The dummy cell program operation may be included in the erase operation in the sense of initializing the state of the entire block. Hereinafter, each step operation of FIG. 8 will be described in detail with reference to FIG. 5 described above.

When the erasing starts, all memory cells in the block included in the word line and the dummy word line DWL are erased under the bias condition shown in FIG. 8. The state of the erased memory cells will be set to the lowest state (S10). The controller 140 receives the dummy word line information DWL_DATA and generates a control signal CNT for applying a program voltage to the internal row address DR_ADD for the dummy cell program and the dummy word line DWL (S20). ). Thereafter, a program voltage Vpgm is applied to the dummy word line DWL to program all dummy cells included in the dummy word line. Programming of the dummy cells may also be performed by a general incremental step pulse programming (ISPP) scheme. Although the flowchart illustrates that the dummy cell program is made based on the ISPP, the scope of the present invention is not limited thereto (S30). The operation of verifying the program state by the program voltage Vpgm is then performed. In particular, the dummy cells are verified whether they are always programmed to the highest state (S40). If all cells have been programmed to the highest state as a result of the verification, all erase operations including the program operation of the dummy cell are terminated. If it is determined that the program to the highest state is not completed, the program operation is repeated with the increased program voltage Vpgm for the dummy cells (S50).

According to the erase method of the present invention including the above-described dummy cell program step, all the cells in the block including the dummy cells are erased, and then all the dummy cells included in the dummy word line DWL are the highest state. The erase operation is completed by programming with.

As described above, the memory cell array according to the present invention includes a word line added with the same function and operation to a word line designated by the row address R_ADD. Among the word lines in the block, a word line arranged at a position capable of minimizing charge sharing may be designated as a dummy word line DWL. The position information of the word line designated as the dummy word line DWL is stored in the fuse box 110 or other nonvolatile memory, and the dummy word line is referred to by the controller 140 in the program / read operation and the erase operation of the flash memory. The voltage applied to the DWL is controlled. In the dummy word line DWL, the same voltage as that of the unselected word line is applied during the program / read operation, and when the erase word is applied to the dummy word line DWL in accordance with the application of the erase voltage. The setting is completed. The dummy word line DWL including the dummy cells programmed to the highest state ensures program prohibition characteristics by minimizing charge sharing in a subsequent program operation.

9 is a circuit diagram showing another embodiment for blocking a decrease in boosting efficiency according to the present invention. Referring to FIG. 9, 64 memory cells are formed in one cell string 210. Boosting efficiency of a cell string that is program inhibited by a dummy cell DMC positioned between memory cells may be increased.

The dummy cell DMC is a cell transistor whose operation characteristic is the same as that of the remaining memory cells. When NAND flash memory cells are formed according to the Self Aligned Double Patterning (SADP) technology to form 64 memory cells in one cell string, 67 cell transistors having a narrow cell gap are formed. Thus, three cell transistors of the 67 memory cells will be used as dummy cells. Using SADP technology to form 32 memory cells, 35 cell transistors are formed. Two dummy cells of the three dummy cells are formed adjacent to the select transistors SST and GST to block the influence of the select transistors on the memory cell. Although not shown in the drawings, dummy cells adjacent to the selection transistors SST and GST may be configured to operate in the same manner as the selection transistor or to operate as a memory cell. The other one dummy cell is used as a dummy cell (DMC) of the present invention for increasing the boosting efficiency.

The position of the dummy cell DMC may be determined by the position of the word line where the boosting efficiency is sharply deteriorated by the charge sharing effect when the program voltage is applied. For example, the dummy cell DMC may be located in the middle of the cell string. Alternatively, it may be located at a point moved in the middle of the cell string in the direction of the string select transistor SST. It will be apparent to those skilled in the art that the position of the dummy cell DMC may be located at a point moved from the middle of the cell string toward the ground select transistor GST.

Referring back to FIG. 9, in the program operation, a blocking voltage Vco is provided to the dummy word line DWL to increase the boosting efficiency of the program inhibited cell string. A channel formed by floating and boosting a cell string is divided into a plurality of channel regions based on the dummy cell DMC by a blocking voltage. Therefore, the charges in the channel region located above the dummy cell DMC do not leak to the lower channel region. The boosting potential of the upper channel region can maintain the initial boosting potential without dropping by blocking the charge sharing effect.

In the memory block of the present invention, a memory cell between a word line WL <N> and a word line WL <N-1> is designated as a dummy cell DMC, and a word line connected to the dummy cell DMC is provided. Designated as a dummy word line (DWL). The optimal location of the dummy cell (DMC) can be evaluated during the test process and stored in a fuse program or other nonvolatile storage device. The dummy cell DMC is then programmed to a state corresponding to the highest threshold voltage in the mounting environment. In addition, during a program operation, a voltage equal to or lower than an unselected word line may be applied to the dummy word line DWL. Charge sharing may be minimized even in the cell string structure of the NAND flash memory having a high degree of integration through the above-described application voltage of the dummy word line DWL.

10 is a cross-sectional view of the program inhibited cell string 210 of FIG. 9. The cell string of FIG. 10 shows an example in which the dummy lines 212 and 221 adjacent to the selection lines GSL1 and SSL1 operate the same as the selection lines. Referring to FIG. 10, the channel floated by the power supply voltage Vcc applied to the bit line BL may be connected to the first channel Ch1 and the second channel by the cutoff voltage Vco applied to the dummy word line 216. The channel Ch2 is separated. If the potential of the second channel Ch2 is not sufficiently boosted by the pass voltage Vpass and the program voltage Vpgm applied to the word line WL <61>, a program disturb phenomenon in which unselected memory cells are programmed may be caused. Can be. Accordingly, the blocking voltage Vco is applied to the dummy word line DWL to block the drop of the potential of the second channel Ch2. The channel floated by the cutoff voltage Vco is separated. Therefore, charge sharing of the second channel is blocked. In more detail,

In the program operation, the power supply voltage Vcc is the bit line BL and the string select lines SSL1 and SSL2 of the program prohibited cell string, and the ground voltage Vss is the ground selection lines GSL1 and GSL2. The source line voltage V _CSL is applied to the common source line CSL. The channel of the program inhibited cell string is floated by the source of the string select transistor being charged and shut-off by the power supply voltage Vcc provided through the bit line. After the pass voltage Vpass is provided to all the word lines WL <0> to WL <63> and the dummy word line DWL, the floated channel is boosted. Following the provision of the pass voltage Vpass, a program voltage is applied to the select word line WL <61> and a cutoff voltage Vco is applied to the dummy word lines DWL and 216, whereby the channel is a dummy word line DWL. ) Is separated into a first channel Ch1 and a second channel Ch2. The boosting potential of the second channel Ch2 raised by the program voltage Vpgm may be maintained at a predetermined level according to the blocking of charge sharing. Here, the magnitude of the blocking voltage Vco may be lower than the pass voltage Vpass and may be set to 0 V or more (0 ≦ Vco <Vpass). In addition, it is apparent to those skilled in the art that the timing of applying the blocking voltage Vco may be the same as the timing of applying the pass voltage Vpass.

The charge sharing phenomenon may be blocked by the separation of the channel by the above-described blocking voltage Vco. By blocking the charge sharing phenomenon, program disturb of unselected memory cells can be suppressed. According to the program prohibition method of the present invention, the channel potential Vch2 of the second channel may be expressed by Equation 1 below.

(N is the number of memory cells to which the pass voltage Vpass is applied to boost the second channel, and N is the number of memory cells boosting the second channel.)

As shown in Equation 1, the boosted second channel potential Vch2 depends on the magnitude of the pass voltage Vpass and the program voltage Vpgm. However, when charge sharing occurs, the potential of the second channel is lowered, and the magnitude of the electric field formed by the lowered second channel potential and the word line potential can cause a soft program. However, the channel is separated by the blocking voltage Vco of the dummy word line DWL, and the charge sharing is cut off, so that the potential of the boosted second channel can be maintained.

Here, although the idea of the present invention has been described using an example in which two dummy cells 212 and 221 positioned outside the cell string are used as the string select line SSL2 and the ground select line GSL2, respectively, It is not limited to this. That is, the two dummy cells 212 and 221 positioned outside the cell string may be formed in the same shape as the memory cell and may be controlled separately from the string select line SSL and the ground select line GSL. This example is shown in FIG.

FIG. 11 is a cross-sectional view of a cell string 210 having a different shape from that of FIG. 10. Referring to FIG. 11, the dummy lines DWL_G and DWL_S positioned outside the cell string form memory cells unlike the dummy lines of the memory FIG. 10. In this case, the dummy lines DWL_G and DWL_S may be controlled in the same manner as the unselected word lines.

In the program operation, the channel floated by the power supply voltage Vcc applied to the bit line BL is connected to the first channel Ch1 and the second channel by the cutoff voltage Vco applied to the dummy word line 236. Ch2). If the potential of the second channel Ch2 is not sufficiently boosted by the pass voltage Vpass and the program voltage Vpgm applied to the word line WL <61>, a program disturb phenomenon in which unselected memory cells are programmed may be caused. Can be. Accordingly, the blocking voltage Vco is applied to the dummy word line DWL to block the drop of the potential of the second channel Ch2. The channel floated by the cutoff voltage Vco is separated. Therefore, charge sharing of the second channel is blocked.

In the program operation, the power supply voltage Vcc is the bit line BL and the string select line SSL of the program inhibited cell string, the ground voltage Vss is the ground select line GSL, and the common source line. The source line voltage V _CSL is applied to the _CSL . The channel of the program inhibited cell string is floated by the source of the string select transistor being charged and shut-off by the power supply voltage Vcc provided through the bit line. After the pass voltage Vpass is provided to all the word lines WL <0> to WL <63> and the dummy word lines DWL, DWL_G, and DWL_S, the floated channel is boosted. Following the provision of the pass voltage Vpass, a program voltage is applied to the select word line WL <61> and a cutoff voltage Vco is applied to the dummy word line DWL, whereby the channel is a dummy word line DWL, 236. ) Is separated into a first channel Ch1 and a second channel Ch2. The boosting potential of the second channel Ch2 raised by the program voltage Vpgm may be maintained at a predetermined level according to the blocking of charge sharing. Here, the magnitude of the blocking voltage Vco may be lower than the pass voltage Vpass and may be set to 0 V or more (0 ≦ Vco <Vpass). In addition, it is apparent to those skilled in the art that the timing of applying the blocking voltage Vco may be the same as the timing of applying the pass voltage Vpass.

10 and 11, the application of the present invention to a general self-boosting scheme has been briefly described. However, in the second channel Ch2 provided with the program voltage Vpgm, it can be separated into another plurality of channels according to a local self boosting scheme. It is self-evident to those who have learned. That is, the control and operation of the dummy word line DWL of the present invention are not limited to the boosting method of the channel applied for program prohibition.

FIG. 12 is a block diagram illustrating a structure of a flash memory device 300 including the above-described dummy word line DWL. Referring to FIG. 11, the flash memory device 300 generates a cutoff voltage Vco provided to the dummy word line DWL and transfers the cutoff voltage Vco to the cell array 310 during a program operation. Under the control of the controller 340, the dummy cells are maintained at a program state corresponding to the highest threshold voltage.

The cell array 310 includes blocks of a cell string structure to which the dummy word line DWL of the present invention is added. The use of dummy word lines located outside the cell string can be variously changed. However, the position of the dummy word line DWL formed between the memory cells may be determined according to a design rule or a process. For example, in a 32 cell string structure, a dummy word line may be specified at a location where the effects of charge sharing may cause program disturb. In the 64 cell string structure, the dummy word line may be positioned at an intermediate position of the string. However, the position of the dummy word line DWL may be arbitrarily changed through various tests, and it is obvious to those who have acquired a general knowledge in the art.

The row decoder 320 transfers the high voltage from the high voltage generator 350 to the word lines and the selection lines SSL and GSL of the cell array 310 in response to the row address. The row decoder 320 performs a decoding function for decoding a row address of a memory cell to be programmed, and a word line selection function for selecting a word line corresponding to the decoded address. A voltage corresponding to the selected word line and word lines adjacent to the selected word line is applied. In the program operation, the row decoder 320 applies a program voltage Vpgm to a selected word line and a pass voltage Vpass to unselected word lines. The row decoder 320 applies the cutoff voltage Vco or the pass voltage Vpass to the dummy word line DWL positioned between the memory cells when the program voltage Vpgm is applied. That is, in the program operation of memory cells positioned below the dummy word line DWL (the ground select line side), the row decoder 320 provides a pass voltage Vpass to the dummy word line DWL. However, when programming the memory cells positioned above the dummy word line DWL, the row decoder 320 provides the blocking voltage Vco to the dummy word line DWL. Alternatively, the row decoder 320 may cut off the voltage to minimize the coupling effect only when the program voltage Vpgm is applied to the dummy word line DWL and the adjacent word line WL <N> (see FIG. 10). Instead of Vco, a pass voltage Vpass may be provided. The row decoder 320 may block erasing of the dummy cells by floating the dummy word line DWL during the erase operation.

The page buffer 330 stores data in or reads data from the memory cell array 310. The page buffer 330 is connected to the memory cell array 310 through a plurality of bit lines. The page buffer 330 includes a plurality of latches (not shown) corresponding to each bit line. Each latch stores data to be programmed or data read. The page buffer 330 applies a ground voltage (0V) or a power supply voltage (Vcc) to a bit line in accordance with a data value stored in each latch during programming. For example, in a program operation, a latch in which data of logic '0' is stored applies a ground voltage (0V) to a connected bit line. The latch, in which data of logic '1' is stored, applies a power supply voltage Vcc to the connected bit line.

The controller 340 selects the voltage applied to the word lines and the selection lines SSL and GSL with reference to the location information DWL Location Info. Of the dummy word line. In the program operation, the controller 340 may apply the cutoff voltage Vco to the dummy word line DWL, the program voltage Vpgm to the selected word line, and the pass voltage Vpass to the unselected word lines. ). Alternatively, the controller 340 may transfer the pass voltage Vpass to the dummy word line DWL during a program operation of memory cells connected to a word line (eg, WL <N>) adjacent to the dummy word line DWL. Can be controlled to be provided. In the read operation, the controller 340 controls the high voltage generator 350 such that the same read voltage Vread as the unselected word line is always applied to the dummy word line DWL as in the above-described program operation. During an erase operation, the controller 340 erases the dummy cells connected to the dummy word line DWL simultaneously with the remaining cells, and thereafter, only the dummy cells are selectively programmed to a state corresponding to the highest threshold voltage. Can be. The controller 340 may control the dummy cells to be erased by plotting the dummy word line DWL every time the block erase operation is performed after the dummy cells are programmed once to a state corresponding to the highest threshold voltage. Here, the dummy word line location information (DWL Location Info.) May be read from the fuse box or code data stored in a specific area of the cell array 310 and provided during the power-on or initialization operation of the flash memory device 300. have.

The high voltage generator 350 generates various word line voltages required for a program operation and a read operation under the control of the controller 340. In addition, the high voltage generator 350 generates a blocking voltage Vco provided to the dummy word line DWL. The cutoff voltage Vco is provided as a voltage for dividing a boosted channel of a cell string which is program inhibited during a program operation. Therefore, the level of the cutoff voltage Vco may be provided at 0V. Alternatively, the blocking voltage Vco may be determined to have a voltage level such that the dummy cell programmed to the state corresponding to the highest threshold voltage is turned off. The boosted channel is separated into the first channel Ch1 and the second channel Ch2 based on the dummy cell by the blocking voltage Vco applied to the gate of the dummy cell. The charge of the second channel Ch2 including the channel of the memory cell to which the program voltage Vpgm is applied has a boosting potential independent of the first channel Ch1 by separation from the first channel Ch1. Therefore, the potential drop due to the charge sharing of the second channel Ch2 is blocked, and the program disturb phenomenon does not occur.

According to the flash memory device 300 according to the present invention, the dummy word line DWL may be used as a means for blocking charge sharing by providing a blocking voltage Vco. Therefore, when the number of cells included in one string increases, such as a 64-cell string, it is possible to solve a program disturb problem caused by charge sharing.

FIG. 13 is a table briefly showing gate voltages of a cell string having a dummy word line DWL in the program operation. In the description of the present invention, only the program operation of the memory cells located above the dummy word line DWL (the side closer to SSL) will be described. That is, in the program operation of memory cells positioned below the dummy word line DWL, a pass voltage Vpass may be applied to the dummy word line DWL. Referring to FIG. 13, a first program case 1 in which the blocking voltage Vco is always provided to the dummy word line DWL, and a pass voltage Vpass or the blocking voltage Vco are supplied to the dummy word line DWL. It may be divided into a provided second program case case2.

A first program case case1 in which a cutoff voltage Vco is always provided to the dummy word line DWL during a program operation of a memory cell located above the dummy word line DWL will be described first. In the first program case 1, the cell string may be program-prohibited according to a self-boosting method or a local self-boosting method. When the program is inhibited according to the self-boosting method, when the program voltage Vpgm is applied to the select word line WL <N>, the bit line BL and the string select line SSL may be used. A power supply voltage Vcc is provided. The pass voltage Vpass is provided to the unselected word lines, the ground voltage Vss is provided to the ground select line GSL, and the source line voltage V _CSL is provided to the common source line CSL. A cutoff voltage Vco is provided to the dummy word line DWL. Here, even when the program voltage Vpgm is applied to the word line WL <N> adjacent to the dummy word line DWL, the cutoff voltage Vco is applied to the dummy word line DWL. Also, even when a word line not adjacent to the dummy word line DWL is selected to apply a program voltage, the cutoff voltage Vco is applied to the dummy word line DWL. In the first program case 1, the cutoff voltage Vco is provided to the dummy word line DWL even if any word line located above the dummy word line DWL is selected.

Subsequently, the first program case 1 of the present invention may be applied even when the program is prohibited according to a local self boosting scheme. That is, when the program voltage Vpgm is applied to the select word line WL <N + 2>, the power supply voltage Vcc is provided to the bit line BL and the string select line SSL. Unselected word lines, including dummy word lines and adjacent word lines WL <N>, have a pass voltage Vpass and a word adjacent to the selected word line WL <N + 2> for generation of a local channel. The line WL <N + 1> is provided with a ground voltage Vss. A ground voltage Vss is provided to the ground select line GSL, and a source line voltage V _CSL is provided to the common source line CSL. A cutoff voltage Vco is provided to the dummy word line DWL. Here, the local self boosting scheme is one example of various schemes for convenience of description. In the program operation, the cutoff voltage Vco is applied to the dummy word line DWL, regardless of any local self boosting scheme.

In the second program case2, the bias of the dummy word line DWL when the word line selected for the program is adjacent to and not adjacent to the dummy word line DWL is different. That is, when the word line DWL <N> adjacent to the dummy word line DWL is selected to block the coupling effect on the program voltage Vpgm, the pass voltage Vpass is applied to the dummy word line DWL. Is provided. Since the blocking voltage Vco provided to separate the boosted channel is relatively low compared to the program voltage Vpgm, the potential increase of the select word line WL <N> may be affected. Therefore, a pass voltage Vpass is applied to the dummy word line DWL. However, when the word line selected for the program is not adjacent to the dummy word line DWL, the cutoff voltage Vco is provided to the dummy word line DWL similarly to the first program case1. At the same time, the power supply voltage Vcc is provided to the bit line BL and the string select line SSL. The pass voltage Vpass is provided to the unselected word lines, the ground voltage Vss is provided to the ground select line GSL, and the source line voltage V _CSL is provided to the common source line CSL. The second program case 2 may also be implemented according to a self-boosting scheme or a local self-boosting scheme. When the program operation is performed according to a self-boosting method, the dummy word line DWL may be included in the dummy word line DWL except when the dummy word line DWL and the adjacent word line WL <N> are selected for the program. A cutoff voltage Vco is provided. The bias condition of the dummy word line DWL is the same in a local self-boosting method. That is, when the program voltage Vpgm is applied to the select word line WL <N + 2>, the power supply voltage Vcc is provided to the bit line BL and the string select line SSL. For the unselected word lines including the dummy word line DWL and the adjacent word line WL <N>, the pass voltage Vpass is applied to the selected word line WL <N + 2> to generate a local channel. The adjacent word line WL <N + 1> is provided with a ground voltage Vss. A ground voltage Vss is provided to the ground select line GSL, and a source line voltage V _CSL is provided to the common source line CSL. A cutoff voltage Vco is provided to the dummy word line DWL.

14 is a flowchart illustrating a program method according to the first program case 1 described above. Referring to FIG. 14, when a program is started, voltages to be provided to word lines and a dummy word line DWL are generated during a program operation. That is, the high voltage generator 350 generates the cutoff voltage Vco, the program voltage Vpgm, and the pass voltage Vpass (S110). The generated voltages are provided to the selected and unselected word lines and the dummy word line DWL. The program voltage Vpgm is provided as a select word line, the pass voltage Vpass is provided as unselected word lines, and the cutoff voltage Vco is provided as a dummy word line (S120). Subsequently, a verification operation for determining whether the program is normal is followed. When the selected memory cells are programmed above the target threshold voltage, the program operation for the selected word line is terminated. However, if there are memory cells that do not reach the target threshold voltage, the process returns to step S110 for reprogramming.

15 is a flowchart briefly illustrating the above-described second program case case2. Referring to FIG. 15, in the case of a program operation in which a program voltage is applied to a word line adjacent to the dummy word line DWL, an exceptionally pass voltage Vpass is provided to the dummy word line DWL. In more detail,

When the program operation starts, the position i of the selection word line WL <i> is detected. The detection operation is an operation for determining whether the position of the selection word line WL <i> is a word line adjacent to the dummy word line DWL (S210). If the position of the select word line WL <i> is the same as the word line WL <N> adjacent to the dummy word line DWL or is located below the dummy word line DWL, the procedure is a program voltage. When (Vpgm) is applied to the dummy word line (DWL), the pass voltage (Vpass) is applied to the step. However, when the position of the selection word line WL <i> is located above (the string selection line side) than the word line WL <N> adjacent to the dummy word line DWL, the procedure is performed with the program voltage Vpgm. In operation S220, the blocking voltage Vco is applied to the dummy word line DWL.

When the position of the selection word line WL <i> is located at the same or lower side than the word line WL <N> adjacent to the dummy word line DWL, the high voltage generator 350 may include a word line and a dummy word line ( The program voltage Vpgm and the pass voltage Vpass to be provided to the DWL are generated (S230). The generated program voltage Vpgm and the pass voltage Vpass are provided to the selected and unselected word lines and the dummy word line DWL. The program voltage Vpgm may be provided to the selected word line, and the pass voltage Vpass may be provided to the unselected word lines and the dummy word line DWL (S240). Subsequently, a verification operation for determining whether the program is normal is followed (S250). When the selected memory cells are programmed above the target threshold voltage, the program operation for the selected word line is terminated. However, if there are memory cells that do not reach the target threshold voltage, the process returns to step S230 for reprogramming.

When the position of the selection word line WL <i> is located above the word line WL <N> adjacent to the dummy word line DWL, the high voltage generator 350 may include a cutoff voltage Vco and a program voltage ( Vpgm) and the pass voltage Vpass are generated (S260). The generated program voltage Vpgm and the pass voltage Vpass are provided to the selected word line and the unselected word lines, respectively. The cutoff voltage Vco is provided to the dummy word line DWL (S270). Subsequently, a verification operation for determining whether the program is normal is followed (S280). When the selected memory cells are programmed above the target threshold voltage, the program operation for the selected word line is terminated. However, if there are memory cells that do not reach the target threshold voltage, the process returns to step S260 for reprogramming.

According to the second program case2 described above, when the word line WL <N> adjacent to the dummy word line DWL is programmed, a pass voltage Vpass is provided to the dummy word line DWL. . Therefore, the coupling effect of the selected word line may be blocked by the relatively low blocking voltage Vco applied to the dummy word line DWL.

16 is a table for exemplarily illustrating bias conditions in an erase operation of a flash memory device of the present invention. Referring to FIG. 16, dummy cells connected to a dummy word line may be managed according to a first erase case case1 or a second erase case case2.

The erase operation of the dummy cells is blocked in the first erase case case1 to maintain a programmed state in a state corresponding to the highest threshold voltage. The dummy cells are already programmed to a state corresponding to the highest threshold voltage. During the block erase operation, the dummy word line DWL may be floated to block the erase operation by F-N tunneling.

The second erase case case2 is a method of managing the dummy cells to be programmed to a state corresponding to the highest threshold voltage after the dummy cells are erased simultaneously with the memory cells during the block erase operation. As a result, according to the second erase case case2, the dummy cells are programmed to a state corresponding to the highest threshold voltage following the erase operation. That is, according to the second erase case case2, the erase operation of the dummy cell must have a program operation following the erase operation.

 17 is a flowchart briefly illustrating the above-described second erase case case2. Referring to FIG. 17, block erase is first performed (S310). Following the block erase operation, a dummy cell program operation for initializing the dummy cell is necessarily performed (S320). In the program operation of the dummy cell, a verification operation for determining whether the threshold voltage of the dummy cell reaches the highest state will be performed (S330). When the verification result is that the dummy cell program operation is normally performed, the dummy cell initialization is terminated. However, if the threshold voltage of the dummy cell does not reach the target threshold voltage, the procedure moves to step S320 for reprogramming the dummy cell.

FIG. 18 is a diagram schematically illustrating a string cross section 400 of a charge trap type flash memory device capable of increasing channel boosting efficiency by a dummy word line DWL of the present invention. Referring to FIG. 18, the charge trap layer 430 of the charge trap type flash memory device is formed of a non-conductive material. The charge trap layer 430 is formed between the oxide layers 420 and 440, and data stored in the charge trap layer 430 is captured by charges introduced by F-N tunneling during the program operation. In the program operation, the channels Ch1 and Ch2 are divided based on the dummy word line DWL to which the cutoff voltage Vco is applied. Charge sharing between the divided channels Ch1 and Ch2 is blocked, and thus, the potential of the boosted second channel Ch2 can be maintained, and the program disturb can be blocked. In the case of charge trapping flash memory devices, as the degree of integration increases, the problem of program disturb is intensified. Therefore, the dummy word line DWL disposed between the word lines may be formed and used as a means for blocking the charge sharing phenomenon. Here, although the charge trap layer 430 and the oxide films 420 and 440 are shown to be continuously formed for the respective memory cells, this is merely exemplary. Therefore, the program method or the program prohibition method of the present invention can be applied to any type of charge trap type NAND flash memory device.

19 is a block diagram illustrating a memory system 500 including a flash memory device 520 for performing a program operation according to the present invention. Referring to FIG. 19, a memory system 500 according to the present invention may include a flash memory device 520 and a memory controller 510. The flash memory device 520 is substantially the same as any of those shown in FIG. 5 or 11 described above, and thus a detailed description thereof will be omitted. The memory controller 510 may be configured to control the flash memory device 520. The combination of the flash memory device 520 and the memory controller 510 may be provided as a memory card or a solid state disk (SSD).

The SRAM 511 is used as the operating memory of the processing unit 512. The host interface 513 includes a data exchange protocol of a host that is connected to the memory system 500. The error correction block 514 detects and corrects an error included in data read from the flash memory device 520. The memory interface 514 interfaces with the flash memory device 520 of the present invention. The processing unit 512 performs various control operations for exchanging data of the memory controller 510. Although not shown in the drawings, the memory system 500 according to the present invention may further be provided with a ROM (not shown) for storing code data for interfacing with a host, and the like. Self-explanatory to those who have learned. The flash memory device 520 may be provided in a multi-chip package composed of a plurality of flash memory chips.

According to the memory system 500 of the present invention, it is possible to provide a storage medium having high capacity and high reliability by drastically improving the program disturb characteristic generated due to high integration. In particular, the flash memory device of the present invention may be provided in a memory system such as a solid state disk (SSD), which is being actively studied recently. In this case, the memory controller 510 may be configured to communicate with an external (eg, host) via one of a variety of interface protocols such as USB, MMC, PCI-E, SATA, PATA, SCSI, ESDI, IDE, and the like. will be.

The flash memory device is a nonvolatile memory device that can retain stored data even when power is cut off. With the increasing use of mobile devices such as cellular phones, PDA digital cameras, portable game consoles, and MP3Ps, flash memory devices are widely used not only as data storage but also as code storage. Flash memory devices may also be used in home applications such as HDTVs, DVDs, routers, and GPS.

20 schematically shows a computing system 600 including a flash memory device 612 in accordance with the present invention. Computing system 600 according to the present invention includes a modem 650 such as a microprocessor 620, a RAM 630, a user interface 640, a baseband chipset electrically connected to the system bus 660. And a memory system 610. The memory system 610 includes a memory controller 611 and a flash memory device 612. The flash memory device 612 may be configured substantially the same as any of those shown in FIG. 5 or 11. The flash memory device 612 may store, via the memory controller 611, N-bit data (N is an integer of 1 or larger) to be processed / processed by the microprocessor 620. If the computing system according to the present invention is a mobile device, a battery (not shown) for supplying an operating voltage of the computing system will be further provided. Although not shown in the drawings, the computing system according to the present invention may further be provided with an application chipset, a camera image processor (CIS), a mobile DRAM, and the like. Self-explanatory to those who have learned. The memory controller 611 and the flash memory device 612 may configure, for example, a solid state drive / disk (SSD) that uses a nonvolatile memory to store data.

The flash memory device and / or the memory controller according to the present invention may be mounted using various types of packages. For example, the flash memory device and / or the memory controller according to the present invention may be a package on package (PoP), ball grid arrays (BGAs), chip scale packages (CSPs), plastic leaded chip carrier (PLCC), plastic dual in- Line Package (PDIP), Die in Waffle Pack, Die in Wafer Form, Chip On Board (COB), Ceramic Dual In-Line Package (CERDIP), Plastic Metric Quad Flat Pack (MQFP), Thin Quad Flatpack (TQFP), Small Outline (SOIC), Shrink Small Outline Package (SSOP), Thin Small Outline (TSOP), Thin Quad Flatpack (TQFP), System In Package (SIP), Multi Chip Package (MCP), Wafer-level Fabricated Package (WFP), It can be implemented using packages such as Wafer-Level Processed Stack Package (WSP), or the like.

As described above, optimal embodiments have been disclosed in the drawings and the specification. Although specific terms have been used herein, they are used only for the purpose of describing the present invention and are not used to limit the scope of the present invention as defined in the meaning or claims. Therefore, those skilled in the art will understand that various modifications and equivalent other embodiments are possible from this. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

1 is a circuit diagram showing a block-by-block string and word line arrangement according to the prior art;

FIG. 2 is a cross-sectional view illustrating charge sharing in the unselected string of FIG. 1; FIG.

3 is a waveform diagram illustrating channel voltage drop of a program inhibited cell according to charge sharing;

4 is a circuit diagram showing a dummy word line of the present invention;

5 is a block diagram illustrating a control scheme in accordance with the addition of a dummy word line of the present invention;

6 illustrates a dummy cell program of the present invention;

7 is a table for explaining bias conditions of a memory block including a dummy word line of the present invention;

8 is a flowchart illustrating an erase operation of the present invention.

9 is a circuit diagram showing a dummy word line of the present invention;

10 is a view showing a separation effect of a channel region by a dummy word line of the present invention;

FIG. 11 is another view showing the effect of separating channel regions by dummy word lines of the present invention; FIG.

12 is a block diagram showing a flash memory device for performing the program operation of the present invention;

13 is a table showing embodiments of the program method of the present invention;

14 is a flowchart showing a first embodiment of the program method of the present invention;

15 is a flowchart showing a second embodiment of the program method of the present invention;

16 is a table showing erase operations for maintaining a threshold voltage of a dummy cell;

17 is a flow chart showing a program of a dummy cell;

18 is a cross sectional view showing a cell string of a charge trap type flash memory device including a dummy cell of the present invention;

19 is a block diagram showing a memory system including a flash memory device of the present invention;

20 is a block diagram illustrating a computing system including the memory system of the present invention.

* Description of the symbols for the main parts of the drawings *

10: program selection memory cell 20, 30: program inhibit string

110: fuse box 120: address buffer

130: pre decoder 140: control unit

150: X-decoder 160: driver

170: memory block 180: page buffer stage

310: cell array 320: row-decoder

330: page buffer

340: Dummy Word Line Location Information Storage

350 control unit 360 high voltage generator

410, 412, 413, 414: word line 411: dummy word line

420 and 440 oxide film 430 charge trap layer

510: memory controller 511: SRAM

512: processing unit 513: host interface

514: error correction block 515: memory interface

520: flash memory device 610: memory system

611: memory controller 612: flash memory device

620: microprocessor 630: RAM

640: user interface 650: modem

660: system bus

Claims (24)

A select transistor coupled to the bit line; A plurality of memory cells connected in series with the selection transistor; And At least one dummy cell positioned between the plurality of memory cells, And the dummy cell is turned off during a program operation of a memory cell positioned between the dummy cell and the selection transistor. The method of claim 1, The dummy cell has a threshold voltage corresponding to a highest state. The method of claim 1, And a power supply voltage Vcc is provided to the bit line during the program operation. The method of claim 3, wherein And a blocking voltage lower than a pass voltage Vpass is provided to the gate of the dummy cell during the program operation. The method of claim 1, The gate of the dummy cell is floating during an erase operation. The method of claim 1, And the dummy cell is programmed to a threshold voltage corresponding to a highest state after an erase operation. The method of claim 1, And the plurality of memory cells are formed of NAND flash memory cells. The method of claim 1, And the dummy cell is turned on during a program operation of a memory cell not located between the dummy cell and the selection transistor. A select transistor coupled to the bit line; A plurality of memory cells connected in series with the selection transistor; And At least one dummy cell positioned between the plurality of memory cells, The dummy cell is selectively turned off according to a position of a memory cell to be programmed among the plurality of memory cells during a program operation. The method of claim 9, And when the memory cell being programmed is located between the dummy cell and the selection transistor, the dummy cell is turned off. The method of claim 9, And the dummy cell is turned on when the memory cell being programmed is located between the dummy cell and the selection transistor and adjacent to the dummy cell. The method of claim 9, And when the programmed memory cell is not located between the dummy cell and the selection transistor, the dummy cell is turned on. The method of claim 9, The dummy cell has a threshold voltage corresponding to a highest state. The method of claim 13, And a pass voltage (Vpass) is provided to a gate of the dummy cell so that the dummy cell is turned on. The method of claim 14, And a blocking voltage lower than the pass voltage Vpass is provided to a gate of the dummy cell so that the dummy cell is turned off. The method of claim 9, The dummy cell is composed of two or more memory cells. The method of claim 9, And a gate of the dummy cell is floating during an erase operation. The method of claim 9, And the dummy cell is programmed to a threshold voltage corresponding to a highest state after an erase operation. The method of claim 9, And the plurality of memory cells are formed of NAND flash memory cells. In the method of programming a nonvolatile memory device: (a) floating a channel of a program inhibited cell string; And (b) boosting the floated channel into a plurality of channel regions, wherein And the plurality of channel regions are separated by blocking at least one dummy cell positioned between a plurality of memory cells included in the cell string. The method of claim 20, And the dummy cell has a threshold voltage corresponding to a highest state. The method of claim 21, In the step (b), a blocking voltage lower than a pass voltage (Vpass) is provided to the gate of the dummy cell. Nonvolatile memory devices; And And a memory controller for controlling the nonvolatile memory device, wherein the nonvolatile memory device is a nonvolatile memory device according to claim 1. Nonvolatile memory devices; And And a memory controller for controlling the nonvolatile memory device, wherein the nonvolatile memory device is a nonvolatile memory device according to claim 9.

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