KR20090124291A - Non-volatile memory device and program method thereof - Google Patents

Abstract

PURPOSE: A non-volatile memory device and a programming method thereof are provided to improve a program speed by selectively using a self boosting mode according to a location of a selected word line. CONSTITUTION: A memory cell array(110) includes a plurality of memory blocks. A page buffer circuit(120) stores data in memory cells according to control of a control circuit(180). A high voltage generating circuit(130) generates high voltage necessary to write and read data onto and from a memory device according to the control of the control circuit. A row selection circuit(140) performs a decoding function, a word line selection function, and function of applying voltage corresponding to word lines. A column selecting circuit(150) performs a decoding function, a bit line selection function, and a function of outputting voltage corresponding to bit lines. A data input/output circuit(160) is controlled by the control circuit. A pass/fail check circuit(170) outputs pass/fail signals to the control circuit. The control circuit controls the overall operation of a non-volatile memory device.

Description

Nonvolatile memory device and its program method {NON-VOLATILE MEMORY DEVICE AND PROGRAM METHOD THEREOF}

The present invention relates to a semiconductor memory device, and more particularly to a nonvolatile memory device and a program method thereof.

Semiconductor memory devices are largely classified into volatile memory devices and nonvolatile memory devices.

Volatile memory devices read and write quickly, but they lose their stored data when their power supplies are interrupted. Volatile memory devices include static random access memory (SRAM), dynamic random access memory (DRAM), and synchronous dynamic random access memory (SDRAM).

In the nonvolatile memory device, stored data is not lost even when the power supply is cut off. Nonvolatile memory devices include read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EPROM), flash memory devices, and PRAM ( Phase-change Random Access Memory (MRAM), Magnetic Random Access Memory (MRAM), Resistive Random Access Memory (RRAM), Ferroelectric Random Access Memory (FRAM), and the like.

Among nonvolatile memories, flash memory is widely used in computers and memory cards because it has a function of electrically erasing data of cells.

Flash memories are classified into NOR and NAND types according to connection states of memory cells and bit lines. NOR flash memory is a form in which two or more cell transistors are connected in parallel to one bit line. The NOR flash memory stores data using a Channel Hot Electron method and uses a Fowler-Nordheim tunneling method. Clear the data. On the other hand, a NAND flash memory has two or more cell transistors connected in series to one bit line, and stores and erases data using F-N tunneling. NOR flash memory is disadvantageous for high integration because of the large current consumption, but has the advantage of easily coping with high speed. On the other hand, the NAND flash memory uses less cell current than the NOR flash memory, which is advantageous for high integration.

In order to program data into a memory cell of a NAND flash memory, a high voltage (for example, 20V) is applied to a word line of a selected memory cell. In a NAND flash memory device, the threshold voltage of a selected memory cell is changed to a higher level while being programmed, while the threshold voltages of unselected memory cells are not changed. An operation of providing a bias condition so that unselected memory cells connected to the same word line as the memory cell to be programmed is not programmed is referred to as program inhibition. The channel potential of the unselected memory cells is raised to reduce the strength of the electric field applied to the charge storage layer, thereby blocking the F-N tunneling phenomenon. An unintended program for an unselected memory cell connected to a selected word line is called program disturb. As a technique for preventing program disturb, there are a program banning method using a self-boosting method and a program banning method using a local self-boosting method.

A program method using a self-boosting method is described in US Patent No. " METHOD OF at 5,677,873 PROGRAMMING FLASH EEPROM INTEGRATED CIRCUIT MEMORY DEVICES TO PREVENT INADVERTENT PROGRAMMING OF NONDESIGNATED NAND MEMORY CELLS THEREIN "in the title, and in US Patent No. 5,991,202" METHOD FOR REDUCING PROGRAM DISTURB DURING SELF - BOOSTING IN A NAND FLASH MEMORY ", which is incorporated herein by reference.

A circuit diagram for describing a program method using a self-boosting method is shown in FIG. 1, and a waveform diagram for explaining a program method using a self-boosting method is shown in FIG. 2. Hereinafter, a program method using a self-boosting method will be described with reference to FIGS. 1 and 2.

The ground path is blocked by applying a voltage of 0 V to the gate of the ground select transistor GST, that is, the ground select line GSL. A voltage of 0 V is applied to the selection bit line (e.g., BL0), and a power supply voltage Vcc is applied as a program prohibition voltage to the unselected bit line (e.g., BL1). A power supply voltage Vcc is applied to the gate of the string select transistor SST, that is, the string select line SSL. This causes the string select transistor SST to shut off after the source of the string select transistor SST is charged to (Vcc-Vth) (Vth is the threshold voltage of the string select transistor).

Thereafter, the pass voltage Vpass is supplied to all the word lines WL0 to WLm-1 during the time t1 of FIG. 2. During the t2 time, the program voltage Vpgm is applied to the selected word line (eg, WL0) and the pass voltage Vpass is continuously supplied to the unselected word lines (eg, WL1 to WLm-1). will be. According to this bias condition, the channel voltage of the program inhibited memory cell, for example, the memory cell M0 located at the intersection of the word line WL0 and the bit line BL1, is boosted. This prevents F-N tunneling between the floating gate and the channel of the program inhibited memory cell, resulting in the program inhibited memory cell being kept in an initial erase state. During the t3 period, voltages applied to the word lines WL0 to WLm-1 are discharged.

However, according to the program method using the self-boosting scheme, as the channel voltage of the program inhibited memory cell is lowered, program disturb in which the program inhibited memory cell is programmed may be caused.

Another technique for preventing program disturb is a program method using a local self-boosting method. The program method using the local self-boosting method is described in US Patent No. 5,715,194 " BIAS SCHEME OF PROGRAM INHIBIT FOR RANDOM PROGRAMMING IN A NAND FLASH MEMORY ", USPatent No. 6,061,270" METHOD FOR PROGRAMMING A NON - VOLATILE MEMORY DEVICE WITH PROGRAM DISTURB CONTROL "and US Pat. No. 6,930,921" NAND TYPE FLASH EEPROM IN WHICH SEQUENTIAL PROGRAMMING PROCESS IS PERFORMED BY USING DIFFERENT INTERMEDIATE VOLTAGES ", which are incorporated herein by reference.

A circuit diagram for describing a program method using a local self boosting method is shown in FIG. 3, and a waveform diagram for explaining a program method using a local self boosting method is shown in FIG. 4. Hereinafter, a program method using a local self-boosting method will be described with reference to FIGS. 3 and 4.

The ground path is blocked by applying a voltage of 0 V to the gate of the ground select transistor GST, that is, the ground select line GSL. A voltage of 0 V is applied to the selection bit line (e.g., BL0), and a power supply voltage Vcc is applied as a program prohibition voltage to the unselected bit line (e.g., BL1). A power supply voltage Vcc is applied to the gate of the string select transistor SST, that is, the string select line SSL. This causes the string select transistor SST to shut off after the source of the string select transistor SST is charged to (Vcc-Vth) (Vth is the threshold voltage of the string select transistor).

Thereafter, the pass voltage Vpass is supplied to all of the word lines WL0 to WLm-1 during the time t10 of FIG. 4. During t11 time, the pass voltage Vpass applied to the unselected word line (eg, WLm-3) located below the selected word line (eg, WLm-2) is discharged to the ground voltage. Once the pass voltage Vpass applied to the unselected word line (eg, WLm-3) is discharged and charged to the local voltage (Vlocal) for t12 hours, the selected word line (eg, for t13 hours) The program voltage Vpgm is applied to WLm-2. In this case, a local voltage (for example, 0 V or a voltage lower than the pass voltage Vpass) is applied to the unselected word line (for example, WLm-3), and the unselected word lines (for example, WL0 to WLm-3). The pass voltage Vpass is continuously applied to WLm-4 and WLm-1. During the time t14, the voltages applied to the word lines WL0 to WLm−1 may be discharged. According to the bias condition corresponding to the time t13, the memory cell to which the local voltage Vlocal is applied is turned off because the voltage difference between the gate and the source (channel) is lower than the threshold voltage. Thus, the channel boosting voltage of the program inhibited memory cell will increase because it is electrically isolated from adjacent channels. According to this condition, F-N tunneling does not occur between the floating gate and the channel of the program inhibited memory cell, and as a result, the program inhibited memory cell is maintained in an initial erase state.

The programming method using the local self-boosting method improves the channel boosting voltage of the program inhibited cell transistor higher than the programming method using the self-boosting method. Therefore, it is widely used in a multi-level cell program and the like.

However, the program method using the local self-boosting method has a disadvantage that the program time is increased by (t11 + t12) time compared to the program method using the self-boosting method.

Therefore, there is a demand for a method for improving program speed in a multi-level cell program using a local self-boosting method.

An object of the present invention is to provide a nonvolatile memory device and a program method thereof that can improve the program speed.

According to an aspect of the present invention, a program method of a nonvolatile memory device including a memory cell array including a plurality of memory cells each storing at least 2-bit data may include: least significant data to be stored in a selected memory cell Bit) determining whether the data; And when the data to be stored in the selected memory cell is LSB data, perform a program operation according to one of a self-boosting method and a local self-boosting method according to whether a word line of the selected memory cell is located below a reference word line. It includes a step.

In example embodiments, when the word line of the selected memory cell is located below the reference word line, the selected memory cell is programmed in the self-boosting manner.

In an embodiment, when the word line of the selected memory cell is not located below the reference word line, the selected memory cell is programmed in the local self-boosting method.

In an embodiment, the position of the reference word line is determined according to the boosting efficiency of the self-boosting method.

According to another feature of the invention, a nonvolatile memory device comprises a memory cell array consisting of memory cells each storing at least 2-bit data; And a controller for determining whether data to be stored in the selected memory cell of the memory cell array is LSB data, and if it is determined that the data to be stored in the selected memory cell is LSB data, the controller is a word of the selected memory cell. Depending on whether the line is located below the reference word line, the program operation of the selected memory cell is controlled to be performed by one of a self-boosting method and a local self-boosting method.

In an embodiment, when the word line of the selected memory cell is located below the reference word line, the selected memory cell is programmed in the self-boosting manner under the control of the controller.

In example embodiments, when the word line of the selected memory cell is not located below the reference word line, the selected memory cell is programmed by the local self-boosting method under the control of the controller.

In an embodiment, the memory cells are arranged to form a plurality of NAND strings.

In example embodiments, when 3-bit data is stored in each of the memory cells, the controller may further determine whether data to be stored in the selected memory cell of the memory cell array is Most Significant Bit (MSB) data.

In example embodiments, when data to be stored in the selected memory cell of the memory cell array is not MSB data, the controller may determine whether the selected memory cell is located below or equal to the reference word line. The program operation is controlled to be performed by any one of the self-boosting method and the local self-boosting method.

According to the present invention, a nonvolatile memory device having improved program speed and a program method thereof are provided.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .

5 is a block diagram schematically illustrating a nonvolatile memory device according to an exemplary embodiment of the present invention. A nonvolatile memory device according to a preferred embodiment of the present invention is a NAND type flash memory device. However, it will be apparent to those skilled in the art that the present invention can be applied to other memory devices (e.g., MROM (Mask ROM), PROM, FRAM, NOR type flash memory device, etc.). .

Referring to FIG. 5, a nonvolatile memory device according to the present invention may include a memory cell array 110, a page buffer circuit 120, a high voltage generation circuit 130, a row selection circuit 140, a column selection circuit 150, The data input / output circuit 160, the pass / fail check circuit 170, and the control circuit 180 are included.

The memory cell array 110 includes a plurality of memory blocks, and a plurality of bit lines BL0 to BLm-1 are arranged in parallel in the plurality of memory blocks. Each memory block is provided with a plurality of strings (or called "NAND strings") corresponding to the bit lines BL0 to BLm-1, respectively.

Each string includes a string select transistor SST, a ground select transistor GST, and a plurality of floating gate transistors M0 to Mn connected in series between a source of the string select transistor SST and a drain of the ground select transistor GST. It consists of -1). Each floating gate transistor M0-Mn-1 is used as a memory cell for storing data. According to the present invention, at least 2-bit data is stored in each memory cell.

A drain of the string select transistor SST included in each string is connected to a corresponding bit line, and a source of the ground select transistor GST is connected to a common source line CSL. Gates of the string select transistors SST included in each string are commonly connected to the string select line SSL, and gates of the ground select transistors GST are commonly connected to the ground select line GSL. Control gates of the floating gate transistors M0 to Mn-1 included in each string are commonly connected to the corresponding word lines WL0 to WLn-1.

Of course, the nonvolatile memory device according to the present invention is not limited to the above configuration, and depending on the circuit configuration or the method of applying the voltages to be used in the program, two or more ground selections in one string are selected. Transistors may be provided, or two or more string select transistors may be provided in one string.

The page buffer circuit 120 stores data in the memory cells or reads data from the memory cells under the control of the control circuit 180. The page buffer circuit 120 is connected to the memory cell array 110 through a plurality of bit lines BL0 to BLm-1. The page buffer circuit 120 includes a plurality of page buffers (not shown) corresponding to each bit line. Each page buffer stores data to be programmed in memory cells or data read from memory cells. The page buffer circuit 120 applies a ground voltage (0V) or a power supply voltage (Vcc) to the bit line in accordance with the data value stored in each page buffer during programming. For example, a ground voltage 0V is applied to a bit line connected to a page buffer in which data of '0' is stored (that is, a bit line connected to a memory cell to be programmed). In addition, a power supply voltage Vcc is applied to a bit line connected to a page buffer in which data of '1' is stored (that is, a bit line connected to a program inhibited memory cell).

The high voltage generation circuit 130 may control the high voltage required for writing and reading data to and from the memory device under the control of the control circuit 180, for example, the program voltage Vpgm, the pass voltage Vpass, the local voltage Vlocal, and the read voltage Vread) and the like.

The program voltage Vpgm is a voltage applied to a selected word line during programming and has a high voltage level close to 20V.

The pass voltage Vpass is lower than the program voltage Vpgm and has a higher voltage level than the local voltage Vlocal. The level of the pass voltage Vpass may be generated at a single voltage level or may be generated at a plurality of different voltage levels.

The local voltage Vlocal is a voltage used to localize the boosting area that prohibits the program. The local voltage Vlocal is applied to at least one word line adjacent to the selected word line. The local voltage Vlocal is lower than the pass voltage Vpass and has a voltage level equal to or higher than the ground voltage 0V. As the local voltage Vlocal, a power supply voltage Vcc may be used, and a read voltage Vread may be used. In addition, even though the voltage is not defined as a fixed level such as the power supply voltage Vcc or the read voltage Vread, voltages having various levels satisfying the range of the local voltage Vlocal described above may be used as the local voltage Vlocal. Can be. The level of the local voltage Vlocal may be generated at a single voltage level or may be generated at a plurality of different voltage levels.

The row selection circuit 140 includes a decoding function for decoding the row address of the memory cell to be programmed, a word line selection function for selecting a word line corresponding to the decoded row address, and a selected word line and adjacent to the selected word line. A function of applying a voltage corresponding to the word lines is performed. When applying a corresponding voltage, the row selection circuit 140 applies bias voltages according to one of a self boosting method and a local self boosting method to corresponding word lines. Since the bias voltage condition of the self-boosting method and the local self-boosting method has been described above, the description thereof will be omitted. The function of the row selection circuit 140 is performed by the control of the control circuit 180.

The column select circuit 150 includes a decoding function for decoding a column address of a memory cell to be programmed, a bit line selection function for selecting a bit line corresponding to the decoded column address, and a selected bit line and adjacent to the selected bit line. Outputs the voltage corresponding to the bit lines.

The data input / output circuit 160 is controlled by the control circuit 180 to receive program data upon data input and to output data read upon data output.

The pass / fail check circuit 170 outputs a pass / fail signal indicating a program path to the control circuit 180 when all data values transmitted through the column select circuit 150 have a pass data value during the program verify operation. . On the other hand, the pass / fail check circuit 170 outputs a pass / fail signal indicating a program fail to the control circuit 180 if at least one of the data values has a fail data value.

The control circuit 180 is configured to control the overall operation of the nonvolatile memory device. In particular, the control circuit 180 determines whether the data to be stored in the memory cell to be programmed is LSB (Least Significant Bit) data. Here, the reason why the control circuit 180 determines whether the data to be stored in the memory cell to be programmed is LSB data is as follows. The distribution allowance range of the threshold voltage formed by programming LSB data is wider than the distribution allowance range of the threshold voltage formed by programming MSB (Most Significant Bit) data. Accordingly, when the LSB data is programmed by determining whether the LSB data is to be programmed, the self-boosting method, which is low in boosting efficiency but has a high program speed, may be mixed with the local self-boosting method.

When the control circuit 180 determines that the data to be stored in the memory cell to be programmed is LSB data, the program operation of the memory cell to be programmed is performed according to whether the word line of the memory cell to be programmed is located below the reference word line. And local self-boosting.

Specifically, the control circuit 180 controls the memory cell to be programmed to be programmed in a self-boosting manner when the word line of the memory cell to be programmed is located below the reference word line. Meanwhile, when the word line of the memory cell to be programmed is not located below the reference word line, the control circuit 180 controls the memory cell to be programmed to be programmed in a local self-boosting manner. That is, the present invention improves program speed during multi-level cell programming by using a combination of a self-boosting method and a local self-boosting method when programming LSB data.

Here, the position of the reference word line is determined according to the boosting efficiency of the self-boosting method, which will be described with reference to FIG. 6.

6 is a diagram comparing a boosting voltage change of a channel when a program is executed by a self-boosting method and a boosting voltage change of the channel when a program is performed by a local self-boosting method.

When the position of the select word line is close to the string select line (or the number of word lines is increased) and the program is executed in a local self-boosting manner, the channel potential rises rapidly during the program operation after the word line WLi. do. However, when the position of the select word line is close to the string select line (or the number of the word lines is increased) and the program is performed in a self-boosting manner, the channel potential suddenly increases during the program operation after the word line WLi. Descend. Therefore, the boosting efficiency caused by the self-boosting method may be degraded during the program operation after the word line WLi, causing a program disturb phenomenon. Accordingly, the reference word line according to the present invention is preferably a word line (for example, WLi) at a position where the channel potential of the self-boosting method drops below a predetermined voltage (ie, the boosting efficiency is lowered).

7 is a diagram illustrating a program processing method in the case of storing 2-bit data per memory cell according to an embodiment of the present invention, where WLi represents a reference word line.

Referring to FIG. 7, when the data to be stored in the memory cell to be programmed is LSB data (shown as a lower page program), the word line of the memory cell to be programmed is located below the reference word line WLi (WL0 to WLi) The program operation is performed using the self-boosting method. If not located below the reference word line WLi (WLi + 1 to WLn-1), the program operation is performed using a local self-boosting method. On the other hand, when the data to be stored in the memory cell to be programmed is not LSB data (shown as an upper page program), the program operation will be performed using a local self-boosting scheme regardless of the position of the word line of the memory cell to be programmed. .

A program flow in the case of programming 2-bit data in each memory cell is described with reference to FIG. 8 as follows.

First, when the program is started, the control circuit 180 determines whether the data to be stored in the memory cell to be programmed is LSB data (S100). As a result of the determination, when the data is LSB data, the control circuit 180 determines whether the word line of the memory cell to be programmed is located below the reference word line (S110). When the word line of the memory cell to be programmed is located below the reference word line, the control circuit 180 controls the program operation to be performed by using a self-boosting method (S120). On the other hand, if the word line of the memory cell to be programmed is not located below the reference word line, the control circuit 180 controls the program operation to be performed using the local self-boosting scheme (S130).

On the other hand, if the data to be stored in the memory cell to be programmed in step S100 is not LSB data, the MSB data is programmed (S140). In this case, the program operation is performed in a local self-boosting manner regardless of the position of the word line of the memory cell to be programmed.

9 is a diagram illustrating a program processing method in the case of storing 3-bit data per memory cell according to another exemplary embodiment of the present invention, where WLi represents a reference word line.

Referring to FIG. 9, when the data to be stored in the memory cell to be programmed is LSB data (shown as a 1 ^st page program), the word line of the memory cell to be programmed is located below the reference word line WLi (WL0). WLi) is programmed using the self-boosting method, and is programmed using the local self-boosting method when it is not located below the reference word line WLi (WLi + 1 to WLn-1). On the other hand, when the data to be stored in the memory cell to be programmed is not LSB data (shown as 2 ^nd and 3 ^rd page programs), it can be programmed using the local self-boosting scheme regardless of the position of the word line of the memory cell to be programmed. ( ^{Marked as} 'option 1' for a 2nd page program).

In another embodiment, when the data to be stored in the memory cell to be programmed is LSB data (shown as a 1 ^st page program), the word line of the memory cell to be programmed is located below the reference word line WLi (WL0 to WLi) is programmed using the self-boosting method, and is programmed using the local self-boosting method when it is not located below the reference word line WLi (WLi + 1 to WLn-1). And, when the data to be stored in the memory cell to be programmed is not the MSB data (as shown by the 2 ^nd page program), the self-boosting scheme, depending on whether the word lines of the memory cell based located below a word line (WLi) to be programmed and which one program operation of local self-boosting scheme is carried out (for the 2 ^nd page program labeled as "option 2"). To this end, the control circuit 180 further determines whether the data to be stored in the memory cell to be programmed is MSB data. When the data to be stored in the memory cell to be programmed is MSB data (shown as a 3 ^rd page program), a local self-boosting scheme is used regardless of the position of the word line of the memory cell to be programmed.

Of course, the present embodiment has been described as an example of storing 2-bit data or 3-bit data per cell, but the present invention is not limited thereto.

Accordingly, the present invention can improve the program speed by selectively using the self-boosting method according to the position of the selected word line when programming LSB data in a multi-level cell program operation.

Flash memory devices are nonvolatile memory devices capable of retaining stored data even when power is cut off. With the growing use of mobile devices such as cellular phones, PDA digital cameras, portable game consoles, and MP3Ps, flash memory devices are becoming more widely used as code storage as well as data storage. Flash memory devices can also be used for home applications such as HDTV, DVD, routers, and GPS. A computing system including the memory device according to the present invention is schematically illustrated in FIG. The computing system according to the present invention includes a microprocessor 2100 electrically connected to a bus 2001, a user interface 2200, a modem 2300 such as a baseband chipset, a memory controller 2400, and a flash memory. Device 2500. The flash memory device 2500 may be configured substantially the same as that shown in FIG. 5. The flash memory device 2500 may store, via the memory controller 2400, N-bit data (N is an integer greater than or equal to 1) processed / to be processed by the microprocessor 2100. When the computing system according to the present invention is a mobile device, a battery 2600 for supplying an operating voltage of the computing system will be further provided. Although not shown in the drawings, the computing system according to the present invention may further be provided with an application chipset, a camera image processor (CIS), a mobile DRAM, and the like. Self-explanatory to those who have learned. The memory controller 2400 and the flash memory device 2500 may configure, for example, an SSD (Solid State Drive / Disk) that uses a nonvolatile memory to store data.

The flash memory device and / or the memory controller according to the present invention may be mounted using various types of packages. For example, the flash memory device and / or the memory controller according to the present invention may be a package on package (PoP), ball grid arrays (BGAs), chip scale packages (CSPs), plastic leaded chip carrier (PLCC), plastic dual in- Line Package (PDIP), Die in Waffle Pack, Die in Wafer Form, Chip On Board (COB), Ceramic Dual In-Line Package (CERDIP), Plastic Metric Quad Flat Pack (MQFP), Thin Quad Flatpack (TQFP), Small Outline (SOIC), Shrink Small Outline Package (SSOP), Thin Small Outline (TSOP), Thin Quad Flatpack (TQFP), System In Package (SIP), Multi Chip Package (MCP), Wafer-level Fabricated Package (WFP), It can be implemented using packages such as Wafer-Level Processed Stack Package (WSP), or the like.

In the detailed description of the present invention, specific embodiments have been described, but it is obvious that various modifications can be made without departing from the scope and spirit of the present invention. Therefore, the scope of the present invention should not be limited to the above-described embodiments, but should be defined by the equivalents of the claims of the present invention as well as the following claims.

1 is a circuit diagram illustrating a program method using a self-boosting method.

2 is a waveform diagram illustrating a program method using a self-boosting method.

3 is a circuit diagram illustrating a program method using a local self-boosting method.

4 is a waveform diagram illustrating a program method using a local self-boosting method.

5 is a block diagram schematically illustrating a nonvolatile memory device according to an exemplary embodiment of the present invention.

6 is a view for explaining a reference word line of the present invention.

7 is a diagram illustrating a program processing method in the case of storing 2-bit data per memory cell according to an embodiment of the present invention.

8 is a flowchart of a case of programming 2-bit data per memory cell according to an embodiment of the present invention.

9 is a diagram illustrating a program processing method when storing 3-bit data per memory cell according to another exemplary embodiment of the present invention.

10 is a block diagram schematically illustrating a computing system including a nonvolatile memory device according to the present invention.

Claims (10)

A program method of a nonvolatile memory device comprising a memory cell array consisting of a plurality of memory cells each storing at least 2-bit data, Determining whether data to be stored in the selected memory cell is LSB (Least Significant Bit) data; And When it is determined that the data to be stored in the selected memory cell is LSB data, the program operation may be performed by either a self-boosting method or a local self-boosting method according to whether a word line of the selected memory cell is located below a reference word line. Program method comprising the steps. According to claim 1, If the word line of the selected memory cell is located below the reference word line, the selected memory cell is programmed in the self-boosting manner. According to claim 1, If the word line of the selected memory cell is not located below the reference word line, the selected memory cell is programmed in the local self-boosting scheme. According to claim 1, The position of the reference word line is determined according to the boosting efficiency of the self-boosting scheme. A memory cell array composed of memory cells each storing at least 2-bit data; And And a controller for determining whether data to be stored in the selected memory cell of the memory cell array is LSB data. If it is determined that the data to be stored in the selected memory cell is LSB data, the controller determines whether the program operation of the selected memory cell is a self-boosting method and a local self-dependence according to whether a word line of the selected memory cell is located below a reference word line. A nonvolatile memory device which controls to be performed by any one of boosting methods. The method of claim 5, And when the word line of the selected memory cell is located below the reference word line, the selected memory cell is programmed in the self-boosting manner under control of the controller. The method of claim 5, And when the word line of the selected memory cell is not located below the reference word line, the selected memory cell is programmed in the local self-boosting manner under control of the controller. The method of claim 5, And the memory cells are arranged to form a plurality of NAND strings. The method of claim 5 When 3-bit data is stored in each of the memory cells, the controller is further configured to determine whether data to be stored in the selected memory cell of the memory cell array is Most Significant Bit (MSB) data. The method of claim 9, If the data to be stored in the selected memory cell of the memory cell array is not MSB data, the controller determines whether the program operation of the selected memory cell is performed according to whether the word line of the selected memory cell is located below the reference word line. The nonvolatile memory device of claim 1, wherein the self-boosting method and the local self-boosting method are controlled.

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