KR20090105052A - Clock synchronization circuit and operation method thereof - Google Patents

Abstract

PURPOSE: A clock synchronization circuit and a driving method thereof are provided to remove a jitter picking phenomenon by comprising the clock synchronization circuit of an injection locking type. CONSTITUTION: A clock synchronization circuit includes a phase locked loop(310) and an injection locking generator(330). The phase locked loop generates the oscillation control voltage by detecting phase/frequency difference between a reference clock signal and a feedback clock signal. The phase locked loop generates the source internal clock signal corresponding to the oscillation control voltage. A free running frequency is set in the injection locking oscillation unit in response to the oscillation control voltage. The injection locking oscillation unit receives the source internal clock signal and generates the internal clock signal.

Description

CLOCK SYNCHRONIZATION CIRCUIT AND OPERATION METHOD THEREOF

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor design techniques, and more particularly, to a clock synchronization circuit and a method of driving a clock synchronization circuit using an injection locking method.

In general, semiconductor devices, including DDR SDRAM (Double Data Rate Synchronous DRAM), receive an external clock signal to generate an internal clock signal and use it as a reference for matching various operation timings in the semiconductor device. Therefore, a clock synchronization circuit for synchronizing the operation timing of the external clock signal and the internal clock signal should be provided in the semiconductor device. Such clock synchronization circuits typically include a phase locked loop (PLL).

In the case of the phase locked loop (PLL), a voltage controlled oscillator (VCO) is used to generate an internal clock signal, which may be divided into analog and digital methods according to a method of controlling the phase locked loop.

1 is a block diagram illustrating a conventional phase locked loop.

Referring to FIG. 1, an analog phase locked loop includes a phase / frequency detector 110, a charge pump 130, a control voltage generator 150, a voltage controlled oscillator 170, and a divider 190. ).

The phase / frequency detector 110 generates an up detection signal DET_UP and a down detection signal DET_DN corresponding to a phase / frequency difference between the reference clock signal CLK_REF and the feedback clock signal CLK_FED fed back. . Here, the reference clock signal CLK_REF is a signal corresponding to an external clock signal, and the up detection signal DET_UP and the down detection signal DET_DN are phase / frequency relationships of the reference clock signal CLK_REF and the feedback clock signal CLK_FED. The pulse signal that is activated according to the above will be described again in the operation description to be described later.

The charge pumping unit 130 performs a positive charge pumping operation in response to the up detection signal DET_UP, and performs a negative charge pumping operation in response to the down detection signal DET_DN. That is, the charge pumping unit 130 supplies charge to the control voltage generation unit 150 in response to the up detection signal DET_UP and is charged in the control voltage generation unit 150 in response to the down detection signal DET_DN. Subtract the charge.

The control voltage generation unit 150 charges as much as the charge supplied by the positive charge pumping operation of the charge pumping unit 130 to generate the oscillation control voltage V_CTR corresponding thereto, and as much as the charge escaped by the negative charge pumping operation. Discharge to generate an oscillation control voltage V_CTR corresponding thereto. In other words, the oscillation control voltage V_CTR has a high voltage level due to the charging operation of the charge pumping unit 130 and a low voltage level due to the discharging operation.

The voltage controlled oscillator 170 generates a PLL clock signal CLK_PLL having a frequency corresponding to the voltage level of the oscillation control voltage V_CTR. For reference, the voltage controlled oscillator 170 includes a plurality of delay cells (not shown) to delay an internally differentially input signal by a delay time corresponding to the oscillation control voltage V_CTR and feed back the oscillator again. It is designed as an oscillator.

The clock divider 190 divides the PLL clock signal CLK_PLL at a predetermined frequency division ratio and outputs the feedback clock signal CLK_FED. Here, the division ratio of the clock divider 190 becomes an important factor in determining the frequency of the PLL clock signal CLK_PLL. For example, when the frequency of the reference clock signal CLK_REF is 2 GHz and the frequency division ratio is 1, the frequency of the PLL clock signal CLK_PLL is also 2 GHz. If the division ratio is 2, the frequency of the PLL clock signal CLK_PLL is 4 GHz, and if the division ratio is ½, the PLL clock signal CLK_PLL is 1 GHz.

The generated feedback clock signal CLK_FED is fed back to the phase / frequency detector 110, and the phase / frequency detector 110 corresponds to the phase / frequency difference between the feedback clock signal CLK_FED and the reference clock signal CLK_REF. The up detection signal DET_UP and the down detection signal DET_DN are generated.

The phase / frequency detection unit 110, the charge pumping unit 130, the control voltage generator 150, the voltage control oscillator 170, and the clock divider 190 constituting the phase locked loop are described in detail. The circuit configuration is already well known and will not be described in detail below.

Next, let's look at the operation of a simple phase locked loop.

The phase / frequency detector 110 detects a phase / frequency difference between the reference clock signal CLK_REF and the feedback clock signal CLK_FED to generate an up detection signal DET_UP and a down detection signal DET_DN. The up detection signal DET_UP is a signal having a pulse width corresponding to the phase difference when the phase of the feedback clock signal CLK_FED is later than the phase of the reference clock signal CLK_REF, and the down detection signal DET_DN is a feedback signal. When the phase of the clock signal CLK_FED is earlier than the phase of the reference clock signal CLK_REF, it is a signal having a pulse width corresponding to the phase difference.

The charge pumping unit 130 charges or discharges the control voltage generation unit 150 through a charge pumping operation corresponding to the up detection signal DET_UP and the down detection signal DET_DN, and thus the control voltage generation unit 150. The voltage level of the oscillation control voltage V_CTR that is outputted from V is changed. In other words, the voltage level of the oscillation control voltage V_CTR increases in response to the up detection signal DET_UP and the voltage level of the oscillation control voltage V_CTR decreases in response to the down detection signal DET_DN.

The voltage controlled oscillator 170 generates a low frequency PLL clock signal CLK_PLL in response to the oscillation control voltage V_CTR of a high voltage level and a high frequency PLL clock in response to the oscillation control voltage V_CTR of a low voltage level. Generate the signal CLK_PLL. The frequency relationship between the oscillation control voltage V_CTR and the PLL clock signal CLK_PLL may vary depending on the design. That is, the PLL clock signal CLK_PLL of low frequency is generated in response to the oscillation control voltage V_CTR of low voltage level, and the PLL clock signal CLK_PLL of high frequency in response to the oscillation control voltage V_CTR of high voltage level is generated. It is also possible to generate.

The clock divider 190 divides the PLL clock signal CLK_PLL at a predetermined divide ratio and outputs the feedback clock signal CLK_FED, and the phase / frequency detector 110 changes the frequency of the reference clock signal CLK_REF and the feedback clock. The phase / frequency difference of the signal CLK_FED is detected again.

The phase locked loop repeatedly performs the above operation and outputs the PLL clock signal CLK_PLL synchronized with the reference clock signal CLK_REF. This synchronization of the reference clock signal CLK_REF and the PLL clock signal CLK_PLL is referred to as "phase / frequency locking."

On the other hand, in recent years, the frequency of the external clock signal is increased to the gigahertz (GHz) band for the high speed of operation of the semiconductor device. Accordingly, the jitter component mixed with the external clock signal cannot be ignored. Therefore, the phase locked loop outputs the PLL clock signal CLK_PLL of low jitter, that is, filtering the jitter as well as the phase / frequency locking operation and the frequency synthesis operation, which are basic operations. It is designed.

FIG. 2 is a graph for explaining a jitter transfer function characteristic curve of the phase locked loop of FIG. 1.

Referring to FIG. 2, 'A' shows the jitter transfer function characteristic curve of an ideal low pass filter, and 'B' shows the jitter transfer function characteristic curve of a typical phase locked loop.

Because of the low frequency filtering operation characteristic of the phase locked loop, since the high frequency jitter component is filtered, the high frequency jitter component does not appear in the PLL clock signal CLK_PLL, which is an output signal of the voltage controlled oscillator 170. However, as can be seen in the graph, the input jitter around bandwidth is rather amplified. This jitter peaking phenomenon not only amplifies the jitter of the input signal, but also amplifies the jitter caused by power noise, thereby greatly deteriorating the jitter of the PLL clock signal CLK_PLL.

The reason why jitter peaking occurs is a closed-loop system where the phase locked loop has two poles at the origin in the frequency domain (s-domain). This is because they do not have a phase margin.

Here, the pole is the value that makes the denominator of the transfer function of a system zero. Then, zero, the opposite of the pole, is the value that makes the transfer function's molecule zero. The poles and zeros are factors that determine the system's phase margin, which is a measure of how stable or unstable the system is.

Next, let's look at the phase margin.

If the phase margin of a system is 60 °, the time taken for the oscillating signal to return to a steady state can be minimized. If the system's phase margin is less than 60 °, the response time can be fast, but it can take a long time for the oscillating signal to become normal due to the high degree of instability. Conversely, if the system's phase margin is greater than 60 °, the stability is high but the response speed is slow, so it may take a long time for the oscillating signal to become normal.

On the other hand, the phase locked loop may be able to have a desired phase margin value by generating a zero point by adjusting the resistances R and capacitors C of the control voltage generator 150. However, the design of a phase locked loop having a desired phase margin is difficult for the following reasons.

First of all, a general phase locked loop is a closed loop system having two poles as described above. Since the phase margin is low and jitter picking occurs, the jitter of the input signal is not only amplified but also caused by jitter caused by power noise. It also greatly amplifies the jitter of the PLL clock signal CLK_PLL.

To prevent this, if the resistance value of the resistor R is designed to be large (creating zero point), the phase margin of the phase locked loop can be increased, but in this case, ripple occurs in the oscillation control voltage V_CTR. Another problem arises in that the pattern jitter which occurs periodically becomes large.

In other words, in the phase locked loop, when the resistance value of the resistor R is increased to eliminate jitter peaking, the pattern jitter of the oscillation control voltage V_CTR increases, and the resistor R is used to eliminate the pattern jitter. If the resistance value is small, jitter peaking occurs. That is, the jitter picking phenomenon and the phenomenon in which the pattern jitter of the oscillation control voltage V_CTR becomes large have a trade off relationship.

As described above, the phase locked loop is designed to filter the jitter component and output the low jitter PLL clock signal CLK_PLL, but the jitter picking occurs in the jitter transfer function of the phase locked loop to perform a desired filtering operation. Can't. In addition, when the resistance value of the resistor R is adjusted in order to eliminate the jitter peaking phenomenon, the pattern jitter increases in the oscillation control voltage V_CTR, thereby preventing accurate phase / frequency locking operation.

SUMMARY OF THE INVENTION The present invention has been proposed to solve the problems of the prior art, and a clock capable of performing a desired phase / frequency locking operation without injection jitter peaking and pattern jitter in a control voltage using an injection locking scheme. It is an object of the present invention to provide a method of driving a synchronization circuit and a clock synchronization circuit.

A clock synchronization circuit according to an aspect of the present invention for achieving the above object detects the phase / frequency difference between the reference clock signal and the feedback clock signal to generate an oscillation control voltage corresponding thereto, and the source corresponding to the oscillation control voltage A phase locked loop for generating an internal clock signal, a free running frequency in response to the oscillation control voltage, and an injection locking oscillation means for generating an internal clock signal by receiving the source internal clock signal It may be provided.

According to another aspect of the present invention, a clock synchronization circuit includes: phase / frequency detection means for outputting a phase / frequency difference between a reference clock signal and a feedback clock signal fed back as a detection signal; Charge pumping means for performing a charge pumping operation in response to the detection signal; Control voltage generation means for generating an oscillation control voltage in response to the charge pumping operation; Voltage controlled oscillation means for generating a source internal clock signal having a frequency corresponding to the oscillation control voltage; Dividing means for dividing the source internal clock signal to generate the feedback clock signal; And a free running frequency is set in response to the oscillation control voltage, and an injection locking oscillation means for receiving the source internal clock signal to generate an internal clock signal.

According to another aspect of the present invention, there is provided a method of driving a clock synchronization circuit, the method comprising: generating a source internal clock signal through a phase / frequency locking operation of a reference clock signal and a feedback clock signal; And setting a free running frequency in response to the oscillation control voltage generated during the locking operation, and injecting the source internal clock signal to perform an injection locking operation for generating an internal clock signal. .

These days, the frequency of the external clock signal has increased so that the jitter component mixed with the external clock signal cannot be ignored. Therefore, the phase locked loop is designed to output the low jitter PLL clock signal by filtering the jitter component as well as the phase / frequency locking operation and the frequency combining operation, but the problem of the jitter peaking phenomenon of the phase locked loop and the control voltage pattern It is difficult to solve all the problems with jitter. In the present invention, by providing an injection locking oscillator which applies a general phase locking loop and an injection locking method, all of the above problems can be solved. Here, the phase locked loop may perform a phase / frequency locking operation and a frequency synthesis operation in a general configuration and generate a source internal clock signal. In addition, the injection locking oscillation unit, which is the core of the present invention, may set a free oscillation frequency using an oscillation control voltage generated in a phase locked loop, and may receive a source internal clock signal to generate a PLL clock signal, which is a substantial internal clock signal. . According to the present invention, it is possible to secure the general operating characteristics of the phase locked loop and to eliminate the jitter picking phenomenon caused by the problem. In addition, by using the filtered control voltage filtered by the oscillation control voltage, the pattern jitter of the oscillation control voltage is not reflected in the PLL clock signal. As a result, the clock synchronization circuit according to the present invention may output a filtering operation for jitter, that is, a low jitter PLL clock signal, and reduce power consumption, which is a unique characteristic of the injection locking method. Can improve the operating characteristics against jitter.

The present invention described above has an effect of eliminating jitter peaking by configuring an injection locking clock synchronization circuit.

In addition, the above-described present invention has an effect of performing a desired phase / frequency locking operation in which the pattern jitter of the control voltage is not reflected in generating the internal clock signal by using the filtered control voltage.

In addition, the above-described present invention has an effect of reducing the power consumption and improving the operation performance for jitter by using the injection locking method.

Hereinafter, the most preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the technical idea of the present invention. .

3 is a block diagram illustrating a clock synchronization circuit according to the present invention.

Referring to FIG. 3, the clock synchronization circuit may include a phase locked loop 310 and an injection locking oscillator 330.

The phase locked loop 310 includes a phase / frequency detector 311, a charge pump 312, a control voltage generator 313, a voltage controlled oscillator 314, and a clock divider 315 in a general configuration. It can be provided. Such a configuration of the phase locked loop 310 is already well known and a detailed circuit configuration will not be described. Hereinafter, a simple role and operation of each component will be described.

First, the phase / frequency detector 311 receives the up detection signal DET_UP and the down detection signal DET_DN corresponding to the phase / frequency difference between the reference clock signal CLK_REF and the feedback clock signal CLK_FED fed back. Create The up detection signal DET_UP and the down detection signal DET_DN are pulse signals that are activated according to the phase / frequency relationship between the reference clock signal CLK_REF and the feedback clock signal CLK_FED.

The charge pumping unit 312 performs a positive charge pumping operation in response to the up detection signal DET_UP, and performs a negative charge pumping operation in response to the down detection signal DET_DN. That is, the charge popping unit 312 supplies charge to the control voltage generator 313 in response to the up detection signal DET_UP and is charged in the control voltage generator 313 in response to the down detection signal DET_DN. Subtract the charge.

The control voltage generation unit 313 charges as much as the charge supplied by the positive charge pumping operation of the charge pumping unit 312 to generate the oscillation control voltage V_CTR corresponding thereto, and as much as the charge escaped by the negative charge pumping operation. Discharge to generate an oscillation control voltage V_CTR corresponding thereto. In other words, the oscillation control voltage V_CTR has a high voltage level due to the charging operation of the charge pumping unit 312 and a low voltage level due to the discharging operation.

The voltage controlled oscillator 314 generates the positive and negative source internal clock signals S_CLK_INN and / S_CLK_INN of the frequency corresponding to the voltage level of the oscillation control voltage V_CTR. For reference, the voltage controlled oscillator 170 may be designed as an oscillator having a plurality of delay cells (see FIG. 11). Here, the sub-source internal clock signal / S_CLK_INN is a clock signal having a phase opposite to that of the positive source internal clock signal S_CLK_INN.

The clock divider 315 divides the constant internal clock signal S_CLK_INN at a predetermined frequency division ratio and outputs it as a feedback clock signal CLK_FED. According to the division ratio of the clock divider 315, the positive / sub source internal clock signals S_CLK_INN and / S_CLK_INN have a frequency divided by 2 ^N relative to the reference clock signal CLK_REF (where N is an integer).

The generated feedback clock signal CLK_FED is fed back to the phase / frequency detector 311, and the phase / frequency detector 311 corresponds to the phase / frequency difference between the feedback clock signal CLK_FED and the reference clock signal CLK_REF. The up detection signal DET_UP and the down detection signal DET_DN are generated.

The phase locked loop 310 according to the present invention has a general configuration as described above, and provides the injection control oscillation unit 330 with the oscillation control voltage V_CTR and the positive / negative source internal clock signals S_CLK_INN and / S_CLK_INN. can do.

First, the operation of the simple phase locked loop 310 will be described.

The phase / frequency detector 311 generates the up detection signal DET_UP and the down detection signal DET_DN by detecting a phase / frequency difference between the reference clock signal CLK_REF and the feedback clock signal CLK_FED. The up detection signal DET_UP is a signal having a pulse width corresponding to the phase difference when the phase of the feedback clock signal CLK_FED is later than the phase of the reference clock signal CLK_REF, and the down detection signal DET_DN is a feedback signal. When the phase of the clock signal CLK_FED is earlier than the phase of the reference clock signal CLK_REF, it is a signal having a pulse width corresponding to the phase difference.

The charge pumping unit 312 charges and discharges the control voltage generator 313 through a charge pumping operation in response to the up detection signal DET_UP and the down detection signal DET_DN, and accordingly, the control voltage generator 313. The voltage level of the oscillation control voltage V_CTR that is outputted from V is changed. In other words, the voltage level of the oscillation control voltage V_CTR increases in response to the up detection signal DET_UP and the voltage level of the oscillation control voltage V_CTR decreases in response to the down detection signal DET_DN.

The voltage controlled oscillator 314 generates the low frequency positive and negative source internal clock signals S_CLK_INN and / S_CLK_INN in response to the oscillation control voltage V_CTR of the high voltage level and generates the oscillation control voltage V_CTR of the low voltage level. Correspondingly, a high frequency positive and negative source internal clock signals S_CLK_INN and / S_CLK_INN are generated. The voltage level of the oscillation control voltage V_CTR and the frequency relationship between the positive / negative source internal clock signals S_CLK_INN and / S_CLK_INN may vary depending on the design. That is, the positive / negative source clock signals S_CLK_INN and / S_CLK_INN of low frequency are generated in response to the oscillation control voltage V_CTR of low voltage level, and the high frequency is corresponding to the oscillation control voltage V_CTR of high voltage level. It is also possible to generate the positive / negative source internal clock signals S_CLK_INN and / S_CLK_INN.

The clock divider 315 divides the constant internal clock signal S_CLK_INN at a predetermined divide ratio and outputs it as the feedback clock signal CLK_FED, and the phase / frequency detector 311 changes the frequency with the reference clock signal CLK_REF. The phase / frequency difference of the feedback clock signal CLK_FED is detected again.

The phase locked loop 310 repeatedly performs such an operation and outputs a feedback clock signal CLK_FED synchronized with the reference clock signal CLK_REF. That is, the phase / frequency locking operation may be performed through such an operation.

On the other hand, the phase locked loop 310 according to the present invention may also occur a jitter peaking phenomenon and a large pattern jitter like the conventional phase locked loop. However, since the injection locking oscillator 330 to be described later prevents pattern jitter of the oscillation control voltage V_CTR, the phase locked loop 310 may be designed in consideration of the jitter peaking phenomenon. In other words, the control voltage generator 313 may be designed to secure a desired phase margin by adjusting a value of the resistor R and the capacitor C without considering a phenomenon in which the pattern jitter increases. If the phase lock loop 310 does not sufficiently remove the jitter peaking phenomenon, it is possible to remove the jitter peaking phenomenon of the entire clock synchronization circuit by adjusting the bandwidth of the injection locking oscillator 330 at the rear stage.

On the other hand, the injection locking oscillator 330 is set a free running frequency in response to the oscillation control voltage (V_CTR) generated in the phase locked loop 310, the positive / negative source internal clock signal (S_CLK_INN, / S_CLK_INN) is input to generate PLL clock signals CLK_PLL and / CLK_PLL synchronized thereto.

FIG. 4 is a block diagram illustrating the injection locking oscillator 330 of FIG. 3.

Referring to FIG. 4, the injection locking oscillator 330 may include a level shifting unit 410, an injection locking voltage controlled oscillator 430, and a filtering unit 450.

The level shifting unit 310 swings to the complementary metal oxide semiconductor (CMOS) level and shifts the input / sub source internal clock signals S_CLK_INN and / S_CLK_INN to the current mode logic level (CML). It is for outputting as the positive / negative input clock signals CLK_IN and / CLK_IN and may be provided to make the circuit operation faster and reduce the power consumption. Here, the positive input clock signal CLK_IN is a clock signal corresponding to the positive source internal clock signal S_CLK_INN, and the sub input clock signal / CLK_IN is a clock signal corresponding to the sub source internal clock signal / S_CLK_INN. . The level shifting unit 310 is already well known and a detailed circuit configuration will not be described.

The injection locking voltage control oscillator 430 receives the positive / negative input clock signals CLK_IN and / CLK_IN output from the level shifting unit 410 and receives the positive / negative PLL clock signals CLK_PLL and / CLK_PLL which are internal clock signals. Create In this case, the injection locking voltage control oscillator 430 is set to a free oscillation frequency by the filtered control voltage FL_V_CTR output from the filtering unit 450, and the positive / negative input clock using the injection locking method described below. The positive / negative PLL clock signals CLK_PLL and / CLK_PLL are synchronized with the signals CLK_IN and / CLK_IN. Here, the positive PLL clock signal CLK_PLL is a clock signal corresponding to the positive input clock signal CLK_IN, and the secondary PLL clock signal / CLK_PLL is a clock signal corresponding to the negative input clock signal / CLK_PLL.

The injection locking voltage control oscillator 430 according to the present invention uses an injection locking method. The injection locking method is, for example, injecting an oscillation signal output from a master oscillator to a slave oscillator, and the oscillation signal output from the slave oscillator is synchronized with the oscillation signal output from the master oscillator. Circuits designed with this injection-locking scheme typically reduce power consumption and improve jitter performance. For reference, if the injection locking voltage control oscillator 430 generating the positive / negative PLL clock signals CLK_PLL and / CLK_PLL is a slave oscillator, the positive / negative input clock signal CLK_IN injected into the injection locking voltage control oscillator 430 , The level shifting unit 410 for generating / CLK_IN) may be referred to as a master oscillator.

Thus, the injection locking voltage control oscillator 430 adopting the injection locking method generates the positive / negative PLL clock signals CLK_PLL and / CLK_PLL synchronized to the input positive / negative input clock signals CLK_IN and / CLK_IN. At this time, the phenomenon in which the positive / negative input clock signals CLK_IN and / CLK_IN and the positive / negative PLL clock signals CLK_PLL and / CLK_PLL are synchronized is referred to as "injection locking". Since the injection locking phenomenon is a general phenomenon of a circuit employing an injection locking method, a detailed description thereof will be omitted.

In general, the injection locking voltage control oscillator 430 using the injection locking method is a very efficient circuit in terms of reducing power consumption and improving operation performance on jitter. However, in order for injection locking to occur, the frequency of the injected oscillation signal, that is, the positive and negative input clock signals CLK_IN and / CLK_IN and the slave oscillator, that is, the free running frequency of the injection locking voltage control oscillator 430, are The condition must be satisfied.

Hereinafter, the relationship between these two frequencies will be described.

First, a free oscillation frequency of the injection locking voltage control oscillator 430 is required to cause injection locking, that is, to synchronize the positive and negative input clock signals CLK_IN and / CLK_IN and the positive and negative PLL clock signals CLK_PLL and / CLK_PLL. It should be located near the frequency of home / sub input clock signal (CLK_IN, / CLK_IN). Otherwise, injection locking does not occur in the injection locking voltage control oscillator 430, thereby preventing synchronization between the positive and negative input clock signals CLK_IN and / CLK_IN and the positive and negative PLL clock signals CLK_PLL and / CLK_PLL. . The reason for this is also a general phenomenon of the injection locking method, so a detailed description thereof will be omitted.

Here, the frequency range of the positive / negative input clock signals CLK_IN and / CLK_IN in which injection locking may occur is referred to as an “injection locking range”. In general, the injection locking range is a positive / negative input clock signal ( It has a very small range based on the frequency of CLK_IN, / CLK_IN). For convenience of explanation, it is assumed that the injection locking range is about 1/10 of the free oscillation frequency of the injection locking voltage controlled oscillator 430.

For example, if the frequencies of the positive and negative input clock signals CLK_IN and / CLK_IN are 4 GHz, the free oscillation frequency of the injection locking voltage control oscillator 430 should also be located near 4 GHz. That is, since the injection locking range has about 1/10 of 4 GHz, the condition in which the injection locking can occur is that the free oscillation frequency of the injection locking voltage control oscillator 430 is within 3.8 GHz to 4.2 GHz. In other words, in order for injection locking to occur, the frequencies of the positive / negative input clock signals CLK_IN and / CLK_IN and the free oscillation frequencies of the injection locking voltage control oscillator 430 should always be located at similar frequencies.

Therefore, in the situation where the operating frequency range in which the clock synchronization circuit must operate these days becomes wider, the circuit designer locks the injection according to the frequency of the positive and negative input clock signals CLK_IN and / CLK_IN having a wide operating frequency range. The free oscillation frequency of the voltage controlled oscillator 430 should also be designed to be variable.

In the present invention, the phase locked loop 310 of FIG. Oscillation control voltage V_CTR was used. That is, the oscillation control voltage V_CTR sets the free oscillation frequency of the injection locking voltage control oscillator 430 to correspond to the frequencies of the positive and negative input clock signals CLK_IN and / CLK_IN. Therefore, the clock synchronization circuit according to the present invention always satisfies the condition for injection locking to occur, and the positive / negative PLL clock signal CLK_PLL synchronized with the positive / negative input clock signals CLK_IN and / CLK_IN as a result of the injection locking. , / CLK_PLL) is possible.

The filtering unit 450 receives the oscillation control voltage V_CTR and filters the oscillation control voltage V_CTR to generate a filtered control voltage FL_V_CTR. In other words, since the phase locked loop 310 is designed to secure a desired phase margin, the pattern jitter increases in the oscillation control voltage V_CTR. The filtering unit 450 filters the enlarged pattern jitter to provide the filtered control voltage FL_V_CTR to the injection locking voltage control oscillator 430, whereby the injection locking voltage control oscillator 430 provides the positive / negative PLL clock signal CLK_PLL. , The influence of the oscillation control voltage V_CTR on the pattern jitter is not reflected in generating / CLK_PLL. Here, the filtering unit 450 may be configured as a low pass filter (LPF) composed of a capacitor connected in parallel with a resistor that receives the oscillation control voltage V_CTR in series. It is well known that a specific circuit configuration will not be described.

FIG. 5 is a waveform diagram illustrating the oscillation control voltage V_CTR and the filtered control voltage FL_V_CTR of FIG. 3.

As can be seen in FIG. 5, it can be seen that pattern jitter occurs in the oscillation control voltage V_CTR output from the phase locked loop 310. However, it can be seen that the pattern jitter disappeared in the filtered control voltage FL_V_CTR passed through the filtering unit 450 of FIG. 4. Therefore, the pattern jitter of the oscillation control voltage V_CTR is not reflected in the positive / negative PLL clock signals CLK_PLL and / CLK_PLL generated by the injection locking voltage control oscillator 430.

FIG. 6 is a diagram for describing the injection locking voltage control oscillator 430 of FIG. 4.

Referring to FIG. 6, the injection locking voltage control oscillator 430 receives the filtered control voltage FL_V_CTR and the positive / negative PLL clock signal CLK_PLL, which is synchronized with the positive / negative input clock signals CLK_IN and / CLK_IN. / CLK_PLL) and may include an injection locking delay cell 610, a first normal delay cell 630, a second normal delay cell 650, and a third normal delay cell 670. have. The injection locking voltage control oscillator 430 may set a free oscillation frequency in response to the filtered control voltage FL_V_CTR, and may perform an injection locking operation based on this. For example, when the voltage level of the filtered control voltage FL_V_CTR is increased, a low free oscillation frequency may be set. When the voltage level of the filtered control voltage FL_V_CTR is low, a high free oscillation frequency may be set. The relationship between the filtered control voltage FL_V_CTR and the free oscillation frequency may vary depending on the design.

The injection locking delay cell 610 is configured to generate the positive / negative output clock signals CLK_OUT and / CLK_OUT having the same frequency as the positive / negative input clock signals CLK_IN and / CLK_IN through the injection locking operation. The received control voltage FL_V_CTR and the positive input clock signal CLK_IN to the first positive input terminal IN1 of the sub input clock signal / CLK_IN to the first sub input terminal / IN1 of its own. The feedback PLL clock signal CLK_PLL is input to the second positive input terminal IN2 of the second PLL clock signal CLK_PLL to the second sub input terminal / IN2 of the second PLL clock signal CLK_PLL.

The first normal delay cell 630 delays the output clock signal of the injection locking delay cell 610 by a predetermined delay time corresponding to the filtered control voltage FL_V_CTR, and receives the filtered control voltage FL_V_CTR. The output signal of the injection locking delay cell 610 is input to its positive and negative input terminals (+,-), respectively.

The second normal delay cell 650 delays the output clock signal of the first normal delay cell 630 by a predetermined delay time corresponding to the filtered control voltage FL_V_CTR and inputs the filtered control voltage FL_V_CTR. Receives the output signal of the first normal delay cell 630 to its positive / negative input terminal (+,-), respectively.

The third normal delay cell 670 delays the output clock signal of the second normal delay cell 650 by a predetermined delay time corresponding to the filtered control voltage FL_V_CTR and thus, the positive and negative PLL clock signals CLK_PLL and / CLK_PLL. In order to generate the, the filtered control voltage FL_V_CTR is input and the output signal of the second normal delay cell 650 receives its positive / negative input terminal (+,-), respectively. Create CLK_PLL, / CLK_PLL).

Here, the bias voltage V_BN for controlling the injection locking delay cell 610 and the first to third normal delay cells 630, 650, and 670 is a reference voltage having a constant voltage level, and is a bandgap circuit. Alternatively, it may be generated using a widget generator.

Subsequently, the first to third normal delay cells 630, 650, and 670 are used to generate a multi phase clock. In the present invention, one injection locking delay cell 610 and an oscilation operation are performed. One normal delay cell for generating the positive / negative PLL clock signals CLK_PLL and / CLK_PLL may be provided. For reference, the multi-phase clock refers to a plurality of clock signals each having a predetermined phase difference. For example, the plurality of clock signals (signals output from each delay cell) output from the injection locking voltage control oscillator 430 may be 45 degrees. Phase difference can be as much as °. Multi-phase clocks not only provide different timings of operation, but also reduce power consumption.

FIG. 7 is a circuit diagram illustrating the injection locking delay cell 610 of FIG. 6.

6 and 7, the injection locking delay cell 610 may include an input / output unit 710, a loading unit 730, and a biasing unit 750.

The input / output unit 710 receives the positive / negative input clock signals CLK_IN and / CLK_IN and the positive / negative PLL clock signals CLK_PLL and / CLK_PLL and synchronizes them with the positive and negative input clock signals CLK_IN and / CLK_IN. For generating the positive / negative output clock signals CLK_OUT and / CLK_OUT, a source-drain path is formed between the output terminal of the negative output clock signal / CLK_OUT and the common node N and the first positive input terminal IN1 is generated. (See FIG. 6) between the first NMOS transistor NM1 receiving the positive input clock signal CLK_IN as a gate, the output terminal of the positive output clock signal CLK_OUT, and the common node N. The second NMOS transistor NM2 and the output terminal of the sub output clock signal / CLK_OUT having a drain path formed therein and receiving the sub input clock signal / CLK_IN input through the first sub input terminal / IN1 as a gate. A positive PLL clock signal is formed between a second node and a common node N and is input through the second positive input terminal IN2. A source-drain path is formed between the third NMOS transistor NM3, which receives the CLK_PLL as a gate, and the output terminal of the positive output clock signal CLK_OUT and the common node N, and the second negative input terminal / IN2. The fourth NMOS transistor NM4 may receive a negative PLL clock signal / CLK_PLL input through the gate.

The loading unit 730 has a loading value corresponding to the filtered control voltage FL_V_CTR, and a source-drain path is formed between the power supply voltage terminal VDD and the output terminal of the sub output clock signal / CLK_OUT and is filtered. A source-drain path is formed between the first PMOS transistor PM1 receiving the control voltage FL_V_CTR as a gate and the output terminal of the power supply voltage terminal VDD and the positive output clock signal CLK_OUT, and the filtered control voltage. Output terminals of the positive and negative output clock signals CLK_OUT and / CLK_OUT are connected in parallel with the second PMOS transistor PM2 and the first and second PMOS transistors PM1 and PM2 respectively receiving the FL_V_CTR as a gate. Third and fourth PMOS transistors PM3 and PM4 connected to the respective gates may be provided.

Here, when the voltage level of the filtered control voltage FL_V_CTR increases, the loading value of the loading unit 730 increases. When the voltage level of the filtered control voltage FL_V_CTR decreases, the loading value of the loading unit 730 is decreased. It becomes small. The relationship between the filtered control voltage FL_V_CTR and the loading value may vary depending on the design.

On the other hand, the biasing unit 750 is for flowing a predetermined operating current to the injection locking delay cell 610 in response to the bias voltage (V_BN), it is to flow a predetermined operating current in the current path including the common node (N). Can be. The biasing unit 750 may include a fifth NMOS transistor NM5 having a source-drain path formed between the common node N and the ground voltage terminal VSS and receiving the bias voltage V_BN as a gate. .

The injection locking delay cell 610 outputs the positive and negative output clock signals CLK_OUT and / CLK_OUT having the same frequency as the positive and negative input clock signals CLK_IN and / CLK_IN to be injected. The injection locking phenomenon is a general operation characteristic of a circuit adopting a general injection locking method, and thus detailed circuit operation thereof will be omitted.

For reference, injection locking is performed by adjusting the size ratio of the first NMOS transistor NM1 and the third NMOS transistor NM3 and the second NMOS transistor NM2 and the fourth NMOS transistor NM4. It is also possible to adjust the range.

8A and 8B are circuit diagrams for explaining any one of the first to third normal delay cells 630, 650, and 670.

In FIG. 8A, a control signal FL_V_CTR filtered by a general delay cell is controlled, and a clock signal output from a delay cell of a previous stage is input to each input terminal IN and / IN to be delayed by a predetermined delay time. OUT, / OUT). Here, the frequency input through the input terminal (IN, / IN) and the frequency output through the output terminal (OUT, / OUT) is the same.

8B is also controlled by the filtered control voltage FL_V_CTR, and receives the clock signal output from the delay cell of the previous stage to each input terminal IN, / IN, and delays it by a predetermined delay time. OUT) can be output. The delay cells of FIGS. 8A and 8B have different numbers of NMOS transistors constituting the input terminals IN and / IN, and their operations are the same. However, in order for the injection locking delay cell 610 and the normal delay cells 630, 650, and 670 to operate symmetrically, a configuration of FIG. 8B having the same physical layout may be preferable.

As described above, the clock synchronization circuit according to the present invention may include a phase locked loop 310 and an injection locking oscillator 330 to remove jitter picking and pattern jitter. In this case, the phase locked loop 310 may be designed by considering only the phase margin, and the pattern jitter phenomenon may be removed by the filtering unit 450 of the injection locking oscillator 330. In addition, for stable circuit operation, the bandwidth of the injection locking oscillator 330 may be smaller than the bandwidth of the phase locked loop 310.

9 is a simulation for explaining the transfer function characteristic curve of the clock synchronization circuit of the present invention.

(a) shows the transfer function special curve of the phase locked loop 310. In the present invention, the jitter picking phenomenon may occur in the vicinity of the bandwidth as in the prior art.

(b) shows a transfer function special curve of the injection locking oscillator 330, and the bandwidth of the injection locking oscillator 330 may be smaller than the bandwidth of the phase locked loop 310.

(c) shows the transfer function selection curve of the clock synchronization circuit of the present invention, and the bandwidth of the clock synchronization circuit according to the present invention is the transfer function selection curve (a) of the phase locked loop 310 and the injection locking oscillator 330. It is expressed as the product of the transfer function selection curve (b) of. As can be seen in the figure, it can be seen that the jitter picking phenomenon occurring in (a) is significantly reduced.

10 is a simulation for explaining the jitter according to the power noise frequency of the clock synchronization circuit according to the present invention.

Referring to FIG. 10, it can be seen that a large jitter is output when A is applied to power noise near a bandwidth in the conventional case. However, in the case of the present invention it can be seen that the jitter is significantly reduced. That is, the jitter is filtered.

As described above, the clock synchronization circuit according to the present invention secures the operation characteristics of the phase locked loop 310 through the general phase locked loop 310, and the jitter peaking phenomenon and the pattern jitter through the injection locking oscillator 330. It can eliminate the phenomenon.

Meanwhile, in order to understand another embodiment of the injection locking voltage controlled oscillator 430 of FIG. 4, a detailed circuit configuration of the voltage controlled oscillator 310 of FIG. 3 will be described with reference to FIG. 11.

Referring to FIG. 11, the voltage controlled oscillator 310 may include four normal delay cells 1110, 1130, 1150, and 1170. In general, the voltage controlled oscillator 310 may include a normal delay cell as shown in FIG. 8A, but the voltage controlled oscillator 310 may be configured as a delay cell as illustrated in FIG. 8B to be symmetrically configured with the injection locking voltage controlled oscillator 430 of another embodiment of FIG. 12. Configured. As will be described with reference to FIG. 12, when the voltage controlled oscillator 310 has such a configuration, each delay cell of the injection locking voltage controlled oscillator 430 may be configured as the injection locking delay cell of FIG. 7.

The voltage controlled oscillator 310 performs the first to fourth positive and negative phase clock signals M_CLK <1>, / M_CLK <1>, M_CLK <2>, / M_CLK <2>, and M_CLK <3> through the injection locking operation. , / M_CLK <3>, M_CLK <4>, / M_CLK <4>). Here, the first to fourth sub phase clock signals / M_CLK <1>, / M_CLK <2>, / M_CLK <3>, and / M_CLK <4> are the first to fourth positive phase clock signals M_CLK <, respectively. 1>, M_CLK <2>, M_CLK <3>, and M_CLK <4>, which are inverted clock signals, and the first to second positive phase clock signals M_CLK <1>, M_CLK <2>, M_CLK <3>, M_CLK <4>) are multi-phase clock signals each having a difference (eg, 45 °) by a predetermined phase.

12 is a view for explaining another embodiment of the injection locking voltage control oscillator 430 of FIG. 4.

The injection locking voltage control oscillator 430 of FIG. 12 includes the first to fourth positive / negative phase clock signals M_CLK <1>, / M_CLK <1>, M_CLK <2>, / M_CLK <2>, and M_CLK of FIG. Four injection locking delay cells 1210, 1230, 1250, and 1270 may be provided to correspond to <3>, / M_CLK <3>, M_CLK <4>, and / M_CLK <4>. Here, the four injection locking delay cells 1210, 1230, 1250, and 1270 may be configured as the injection locking delay cells of FIG. 7, and each injection locking delay cell corresponds to each output signal M_CLK <1>, / M_CLK. Injection lock operation may be performed by injection of <1>, M_CLK <2>, / M_CLK <2>, M_CLK <3>, / M_CLK <3>, M_CLK <4>, and / M_CLK <4>. Here, since the injection locking operation of each injection locking delay cell has been described, it will be omitted.

Meanwhile, in the embodiment of FIG. 12, a case in which clock signals corresponding to four injection locking delay cells 1210, 1230, 1250, and 1270 are injected is described as an example. May be injected, and the injected clock signal may be a clock signal having a phase corresponding to the reference clock signal CLK_REF.

As described above, the clock synchronization circuit according to the present invention configures the general phase locked loop 310 and the injection locking oscillator 330 to reduce power consumption as well as phase / frequency locking operation and frequency synthesis operation. It also improves the operating characteristics for jitter. In addition, by setting the bandwidth of the injection locking oscillator 330 to be smaller than the bandwidth of the phase locked loop 310, it is possible to eliminate a section in which jitter picking occurs.

Subsequently, the clock synchronization circuit according to the present invention uses the filtered control voltage FL_V_CTR so that the pattern jitter of the oscillation control voltage V_CTR is not reflected in the PLL clock signals CLK_PLL and / CLK_PLL.

Subsequently, the clock synchronization circuit according to the present invention can reduce injection power as well as stable phase / frequency locking operation by applying an injection locking scheme, and can improve operation characteristics for jitter.

Although the technical spirit of the present invention has been described in detail according to the above-described preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible with various substitutions, modifications, and changes within the scope of the technical idea of the present invention.

In addition, the logic gate and the transistor illustrated in the above embodiment should be implemented in different positions and types depending on the polarity of the input signal.

1 is a block diagram illustrating a conventional phase locked loop.

FIG. 2 is a graph for explaining a jitter transfer function characteristic curve of the phase locked loop of FIG. 1. FIG.

3 is a block diagram illustrating a clock synchronization circuit according to the present invention.

FIG. 4 is a block diagram illustrating the injection locking oscillator 330 of FIG. 3.

FIG. 5 is a waveform diagram illustrating the oscillation control voltage V_CTR and the filtered control voltage FL_V_CTR of FIG. 3.

6 is a view for explaining the injection locking voltage control oscillator 430 of FIG.

FIG. 7 is a circuit diagram illustrating the injection locking delay cell 610 of FIG. 6.

8A and 8B are circuit diagrams for explaining any one of the first to third normal delay cells (630, 650, 670).

9 is a simulation for explaining a jitter transfer function characteristic curve of a conventional phase locked loop.

10 is a simulation for explaining the jitter transfer function characteristic curve of the phase locked loop of the present invention.

FIG. 11 is a circuit diagram illustrating the voltage controlled oscillator 310 of FIG. 3.

12 is a view for explaining another embodiment of the injection locking voltage control oscillator 430 of FIG.

* Explanation of symbols for the main parts of the drawings

310: injection locking oscillator 330: phase locked loop

Claims (28)

A phase locked loop for detecting a phase / frequency difference between the reference clock signal and the feedback clock signal to generate an oscillation control voltage corresponding thereto, and for generating a source internal clock signal corresponding to the oscillation control voltage; A free running frequency is set in response to the oscillation control voltage, and an injection locking oscillation means for receiving the source internal clock signal and generating an internal clock signal Clock synchronization circuit having a. The method of claim 1, And the source internal clock signal has a frequency obtained by dividing the reference clock signal by 2 ^N (where N is an integer), and the internal clock signal has the same frequency as the source internal clock signal. The method of claim 1, The injection locking oscillation means, A filtering unit for filtering the oscillation control voltage and outputting a filtered control voltage; And an injection locking voltage control oscillator configured to receive the filtered control voltage and generate the internal clock signal having a frequency corresponding to the source internal clock signal. The method of claim 3, And the filtering unit comprises a low pass filter. The method of claim 2, The injection locking voltage control oscillator, An injection locking delay cell configured to receive the filtered control voltage, the source internal clock signal and the internal clock signal, and generate an output clock signal corresponding to the source internal clock signal; And a normal delay cell which delays the output clock signal by a predetermined delay time corresponding to the oscillation control voltage and outputs the internal clock signal as the internal clock signal. The method of claim 5, And the source internal clock signal and the output clock signal have the same frequency. The method of claim 5, The injection locking delay cell, An input / output unit configured to receive the reference clock signal and the internal clock signal and output a clock signal synchronized with the reference clock signal; A loading unit having a loading value corresponding to the filtered control voltage; And And a biasing portion configured to flow a predetermined operating current to the injection locking delay cell in response to a bias voltage. The method of claim 7, wherein The input / output unit, A first input unit inserted between the differential output terminal and the biasing unit and receiving the source internal clock signal differentially input; And a second input unit inserted between the differential output terminal and the biasing unit and receiving the internal clock signal which is differentially input. The method of claim 1, And a level shifting means for shifting the voltage level of the source reference clock signal to a predetermined voltage level to provide the injection locking oscillation means. The method of claim 1, And the bandwidth of the injection locking oscillation means is smaller than the bandwidth of the phase-locked loop. Phase / frequency detection means for outputting a phase / frequency difference between the reference clock signal and the feedback clock signal fed back as a detection signal; Charge pumping means for performing a charge pumping operation in response to the detection signal; Control voltage generation means for generating an oscillation control voltage in response to the charge pumping operation; Voltage controlled oscillation means for generating a source internal clock signal having a frequency corresponding to the oscillation control voltage; Dividing means for dividing the source internal clock signal to generate the feedback clock signal; And A free running frequency is set in response to the oscillation control voltage, and an injection locking oscillation means for generating an internal clock signal by receiving the source internal clock signal. Clock synchronization circuit having a. The method of claim 11, wherein The voltage controlled oscillation means, And a plurality of delay cells for generating a plurality of source internal clock signals having predetermined phase differences from each other. The method of claim 12, The injection locking oscillation means, A filtering unit for filtering the oscillation control voltage and outputting a filtered control voltage; And an injection locking voltage control oscillator configured to receive the filtered control voltage and generate the internal clock signals corresponding to the plurality of source internal clock signals. The method of claim 13, And the filtering unit comprises a low pass filter. The method of claim 13, The injection locking voltage control oscillator, And a plurality of injection locking delay cells corresponding to the plurality of source internal clock signals and generating a plurality of internal clock signals. The method of claim 13, The injection locking voltage control oscillator, A first injection locking delay cell configured to receive the filtered control voltage, the first source internal clock signal, and the internal clock signal to generate a first internal clock signal corresponding to the first source internal clock signal; And a second injection locking delay cell configured to receive the filtered control voltage, the second source internal clock signal, and the first internal clock signal to generate the internal clock signal corresponding to the second source internal clock signal. Clock synchronization circuit. The method of claim 16, And the first internal clock signal has the same frequency as the first source internal clock signal, and the internal clock signal has the same frequency as the second source internal clock signal. The method of claim 11, And a level shifting means for shifting the voltage level of the source reference clock signal to a predetermined voltage level. The method of claim 11, And the source internal clock signal has a frequency obtained by dividing the reference clock signal by 2 ^N (where N is an integer), and the internal clock signal has the same frequency as the source internal clock signal. The method of claim 11, And the bandwidth of the injection locking oscillation means is smaller than the bandwidth of the phase-locked loop. Generating a source internal clock signal through a phase / frequency locking operation of the reference clock signal and the feedback clock signal; Setting a free running frequency in response to the oscillation control voltage generated during the phase / frequency locking operation, and performing an injection locking operation for generating an internal clock signal by injecting the source internal clock signal; Method of driving a clock synchronization circuit comprising a. The method of claim 21, Performing the phase / frequency locking operation, Outputting a phase / frequency difference between the reference clock signal and the feedback clock signal fed back as a detection signal; Performing a charge pumping operation in response to the detection signal; Generating the oscillation control voltage in response to the charge pumping operation; Generating the source internal clock signal of a frequency corresponding to the oscillation control voltage; And And dividing the source internal clock signal to generate the feedback clock signal. The method of claim 21, The source internal clock signal has a frequency obtained by dividing the reference clock signal by 2 ^N (where N is an integer), and the internal clock signal has the same frequency as the source internal clock signal. Way. The method of claim 21, The performing of the injection locking operation may include: Low pass filtering the oscillation control voltage; And receiving the filtered oscillation control voltage and injecting the source internal clock signal to generate the internal clock signal having a frequency corresponding thereto. The method of claim 24, Generating the internal clock signal, Generating an output clock signal corresponding to the reference clock signal by receiving the internal clock signal fed back from the source internal clock signal; And delaying the output clock signal by a predetermined delay time corresponding to the filtered oscillation control voltage to generate the internal clock signal. The method of claim 22, And the source internal clock signal comprises a plurality of source internal clock signals having predetermined phase differences from each other. The method of claim 26, Generating the internal clock signal, And generating a plurality of internal clock signals corresponding to the plurality of source internal clock signals. The method of claim 21, And the internal clock signal has the same frequency as the source internal clock signal.

Images