KR20090095912A - Liquid Crystal Display And Driving Method Thereof - Google Patents

Abstract

A liquid crystal display and a driving method thereof are provided to reduce power consumption by automatically selecting a driving mode according to image quality. In a liquid crystal display and a driving method thereof, a plurality of data lines(D1-Dm) and plurality of gate lines(G1-Gn) are crossed with each other at an LCD panel(20). Liquid crystal cells are formed at the intersection, and It is determines whether an image which is displayed on the liquid crystal panel requires high power consumption or not. A driving mode selecting circuit(21a) generates a driving section mode differently according to determination results.

Description

Liquid Crystal Display And Driving Method Thereof

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device and a driving method thereof which reduce power consumption and improve display quality.

The liquid crystal display device displays an image by adjusting light transmittance of liquid crystal cells according to a video signal. The active matrix type liquid crystal display device actively converts data by switching data voltages supplied to the liquid crystal cells by using a thin film transistor (TFT) formed for each liquid crystal cell (Clc) as shown in FIG. 1. By controlling, the display quality of a moving image can be improved. In FIG. 1, reference numeral “Cst” denotes a storage capacitor Cst for maintaining the data voltage charged in the liquid crystal cell Clc, “D1” denotes a data line to which a data voltage is supplied, and “G1”. Denotes a gate line to which a scan voltage is supplied.

In order to reduce the DC offset component and reduce the deterioration of the liquid crystal, the liquid crystal display device is driven in an inversion method in which polarities are inverted between neighboring liquid crystal cells and polarities are inverted in units of frame periods. . However, in the inversion driving method, when the polarity of the data voltage is changed, the swing width of the data voltage supplied to the data lines is increased, and a lot of current is generated in the data driving circuit, so that the heating temperature of the data driving circuit is increased and the power consumption is rapidly increased. There is a problem. In order to reduce the swing width of the data voltage supplied to the data lines, and to reduce the heat generation temperature and power consumption of the data driving circuit, the charge share control using the charge share circuit employed in the data driving circuit as shown in FIG. Charge Share Control (hereinafter referred to as "CSC") has been proposed, but the effect has not reached a satisfactory level. This is because the CSC method of FIG. 2A can reduce the swing width of the data voltage, but increases the number of transitions of the data voltage by unconditionally performing charge sharing between the data and the data. Accordingly, in order to further reduce the heat generation temperature and power consumption of the data driving circuit, a dynamic CSC method of performing charge sharing only when the polarity of the data voltage is inverted as shown in FIG. 2B reduces the number of transitions of the data voltage. In addition, a power control method for controlling the output buffer side power of the data driving circuit has been proposed. Dynamic CSC and PWRC are typically applied to Lusem's model number LS0608D1, as well as to Magnachip and OKI. This low consumption driving method shown in FIG. 2B is fixed after being selected by setting an option pin by a set maker when manufacturing a data driving circuit (D-IC circuit) as shown in FIG. 3. Meanwhile, the set maker may drive the data driving circuit in the normal driving method as shown in FIG. 2A by changing the option pin setting in FIG. 3 when manufacturing the data driving circuit. The data driving circuit is selected and driven in either a normal driving mode or a low consumption driving mode by an option pin set at the beginning of manufacturing, including a charge share circuit and a power control circuit. For example, when the switch SW of the pull-up equivalent circuit is opened by the option pin setting, the data driving circuit is in the normal driving mode as shown in FIG. 2A by the high level CSC signal and the PWRC signal. It works. On the other hand, when the switch SW of the pull-up equivalent circuit is shorted by the option pin setting, the data driving circuit is operated in the low consumption driving mode as shown in FIG. 2B by the low level CSC signal and the PWRC signal.

As described above, the conventional liquid crystal display device is continuously operated in a low power consumption mode selected and fixed by an option pin to reduce the heat generation temperature and power consumption of the data driving circuit, thereby making it difficult to respond flexibly to an image. In other words, the conventional liquid crystal display device causes the display quality to be unnecessarily deteriorated by operating in the same low power consumption mode even for all the displayed images, i.e., images requiring small power consumption of the data driving circuit. The low power consumption mode focuses on reducing power consumption, because display quality is inferior to that of the normal mode. For example, in the liquid crystal display device driven in the vertical two-dot inversion method and the low consumption driving mode as shown in FIG. Is generated largely, resulting in a 2-line horizontal line defect.

Accordingly, an object of the present invention is to automatically select the driving mode according to the attributes of the displayed image, thereby reducing power consumption in images requiring large power consumption and increasing display quality in images requiring small power consumption. A liquid crystal display device and a driving method thereof are provided.

In order to achieve the above object, a liquid crystal display device according to an embodiment of the present invention comprises a liquid crystal display panel in which a plurality of data lines and a plurality of gate lines intersect, and the liquid crystal cells are formed in the intersection area; By using the digital value of the input digital video data, it is determined whether the image to be displayed on the liquid crystal display panel by the digital video data requires a large power consumption or a small power consumption. A driving mode selection circuit for generating a driving mode selection signal differently; And a low power consumption mode in response to a low power consumption selection signal corresponding to the case where the image to be displayed among the drive mode selection signals requires a large power consumption, and wherein the image to be displayed among the drive mode selection signals has a small power consumption. And a data driving circuit configured to operate in the normal driving mode in response to the normal power selection signal corresponding to the request.

The driving mode selection circuit may include a first data pattern in which a digital value difference between data to be displayed adjacent to each other in a horizontal or vertical direction is greater than or equal to a first reference value, or a second in which digital values of RGB data to be displayed on one pixel are greater than or equal to a second reference value, respectively. Detects the ratio of the data pattern within one screen, and generates the low power consumption selection signal instructing the operation of the low power consumption mode when the detected ratio is equal to or greater than a third reference value, while the detected ratio is the third reference value. If less, the normal power selection signal for instructing the normal driving mode is generated.

The driving mode selection circuit may include a memory configured to store digital video data of one input frame; A first data pattern detector for detecting a first data pattern whose digital value difference between data to be displayed adjacent to each other in a horizontal or vertical direction is equal to or greater than the first reference value; A second data pattern detector for detecting a second data pattern in which digital values of RGB data to be displayed on one pixel are each greater than or equal to the second reference value; The first data pattern detection signal from the first data pattern detection unit is counted on the one frame of digital video data to generate a first count signal, and the second data pattern detection unit detects the second data pattern from the second data pattern detection unit. An adder for counting the signals and generating a second count signal; The first count signal and the second count signal are compared with the third reference value to detect a percentage (%) of the first and second data patterns of the entire screen, and based on the detection result, the digital for one frame An image attribute determiner which determines whether the image implemented by the video data is an image requiring large power consumption or an image requiring small power consumption; And a mode selection signal generator for generating the low power consumption selection signal or the normal power selection signal based on the image attribute determination signal from the image attribute determiner.

The data driving circuit includes a charge share circuit, a power control circuit for controlling its output buffer power, and a pull-up equivalent circuit; The charge share circuit is controlled by a charge share control signal generated by the pull-up equivalent circuit, and the power control circuit is controlled by a power control signal generated by the pull-up equivalent circuit.

The data driving circuit performs charge sharing only when the polarity of the data voltage charged in the liquid crystal cells is inverted by the low level charge share control signal generated in response to the low power consumption selection signal. Reduce the number of times; A low level power control signal generated in response to the low power consumption selection signal smoothes the data voltage rising slope to a target point when charging the data voltage to the liquid crystal cells.

The data driving circuit performs unconditional charge sharing between data voltages charged in the liquid crystal cells by a high level charge share control signal generated in response to the normal power selection signal; When the data voltage is charged to the liquid crystal cells by the high level power control signal generated in response to the normal power selection signal, the slope of the data voltage increase to the target point is urgent.

According to an exemplary embodiment of the present invention, a liquid crystal display panel includes a liquid crystal display panel in which a plurality of data lines and a plurality of gate lines intersect and liquid crystal cells are formed in an intersection area thereof, and a data driving circuit for supplying a data voltage to the liquid crystal cells. The driving method of determines whether the image to be displayed on the liquid crystal display panel by the digital video data requires a large power consumption or a small power consumption by using the digital value of the input digital video data. A first step of generating a driving mode selection signal differently according to the attributes of the displayed image; And operating the data driving circuit in a low power consumption mode in response to a low power consumption selection signal corresponding to a case in which the image to be displayed among the drive mode selection signals requires a large power consumption. And a second step of operating the data driving circuit in the normal driving mode in response to the normal power selection signal corresponding to the case where the image requires small power consumption.

The liquid crystal display device and the driving method thereof according to the present invention allow the selection of the driving mode to be automatically made according to the property of the image, so that the image requiring a large power consumption is operated in a low power consumption mode to reduce the power consumption and to reduce the power consumption. In the image that needs to be operated in the normal driving mode, the display quality can be improved.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 4 to 7.

4 shows a liquid crystal display according to an embodiment of the present invention.

Referring to FIG. 4, a liquid crystal display according to an exemplary embodiment of the present invention includes a liquid crystal display panel 20, a timing controller 21, a driving mode selecting circuit 21a, a data driving circuit 22, and a gate driving circuit ( 23).

The liquid crystal display panel 20 includes liquid crystal molecules dropped between two glass substrates. In the liquid crystal display panel 20, m × n liquid crystal cells Clc are arranged in a matrix form by the cross structure of the data lines D1 to Dm and the gate lines G1 to Gn.

The lower glass substrate of the liquid crystal display panel 20 has m data lines D1 to Dm, n gate lines G1 to Gn, TFTs, and pixel electrodes of the liquid crystal cell Clc connected to the TFTs. 1), and a storage capacitor Cst and the like are formed.

The black matrix, the color filter, and the common electrode 2 are formed on the upper glass substrate of the liquid crystal display panel 20. The common electrode 2 is formed on the upper glass substrate in a vertical electric field driving method such as twisted nematic (TN) mode and vertical alignment (VA) mode, and has an in plane switching (IPS) mode and a fringe field switching (FFS) mode. In the same horizontal electric field driving method, the pixel electrode 1 is formed on the lower glass substrate.

A polarizing plate having an optical axis orthogonal to each other is attached to each of the upper and lower glass substrates of the liquid crystal display panel 20, and an alignment layer for setting the pretilt angle of the liquid crystal is formed on an inner surface of the liquid crystal display panel 20 in contact with the liquid crystal.

The timing controller 21 receives timing signals such as vertical / horizontal synchronization signals (Vsync, Hsync), data enable, clock signal (CLK), and the like, and the data driver circuit 22 and the gate driver circuit 23. Generate control signals for controlling the operation timing of the signal. These control signals include a gate start pulse (GSP), a gate shift clock signal (GSC), a gate output enable signal (GOE), and a source start pulse (SSP). , A source sampling clock (SSC), a source output enable signal (SOE), and a polarity control signal (POL). In addition, the timing controller 21 realigns the input digital video data RGB to the liquid crystal display panel 20 and supplies the digital video data RGB to the data driving circuit 22.

The driving mode selection circuit 21a detects a digital value of the input digital video data RGB and generates a driving mode selection signal MDS based on the detected information. In other words, the driving mode selection circuit 21a may include a first data pattern in which the digital value difference between the data to be displayed adjacent to each other in the horizontal or vertical direction is greater than or equal to the first reference value, or the digital values of the RGB data to be displayed in one pixel are respectively second. A ratio of the second data pattern that is greater than or equal to the reference value is detected in one screen, and when the detected ratio is greater than or equal to the third reference value, a low power consumption selection signal for instructing operation of the low power consumption mode is generated. On the other hand, the driving mode selection circuit 21a generates a normal power selection signal for instructing the operation of the normal driving mode when the detected ratio is less than the third reference value. The driving mode selection circuit 21a may be integrated in the timing controller 21 as shown, or may be disposed outside the timing controller 21. The driving mode selection circuit 21a will be described in detail with reference to FIG. 5.

The data driver circuit 22 is composed of a plurality of gate drive integrated circuits including a shift register, first and second latches, a digital-to-analog converter, and an output buffer that are connected dependently between the input line and the data line. The data driving circuit 22 latches the digital video data RGB under the control of the timing controller 21 and converts the digital video data into an analog positive / negative gamma compensation voltage to convert the positive / negative data voltage. Is generated and the data voltage is supplied to the data lines D1 to Dm. In particular, the data driving circuit 22 includes a charge share circuit and a power control circuit, in response to the driving mode selection signal MDS from the driving mode selection circuit 21a, either the low consumption driving mode or the normal driving mode. Is operated. In other words, the data driving circuit 22 performs charge sharing only when the polarity of the data voltage is reversed in response to the low power consumption selection signal applied in response to the display image requiring a large power consumption, so that the number of transitions of the data voltage is performed. The power consumption on the output buffer side is controlled and the data voltage rising slope to the target point is smoothed to reduce power consumption. In addition, the data driving circuit 22 performs charge sharing between the data and the data unconditionally and controls the power at the output buffer side in response to the normal power selection signal applied in response to the display image requiring small power consumption. In this way, the slope of the data voltage rising to the target point is made to be sharp, thereby improving display quality.

The gate driving circuit 23 has a shift register and a level shifter for converting the output signal of the shift register into a swing width suitable for driving the TFT of the liquid crystal cell, and an output buffer connected between the level shifter and the gate lines G1 to Gn, respectively. Comprising a plurality of gate drive integrated circuits comprising a sequentially output scan pulses having a pulse width of approximately one horizontal period.

5 shows a detailed configuration of the drive mode selection circuit 21a.

Referring to FIG. 5, the driving mode selection circuit 21a includes a memory 110, a data pattern detector 120, an adder 130, an image attribute determiner 140, and a mode selection signal generator 150.

The memory 110 stores digital video data RGB for one frame.

The data pattern detector 120 uses the digital video data RGB stored in the memory 110 to detect a first data pattern or a second data pattern that increases power consumption when the image is displayed on the display image. To this end, the data pattern detector 120 includes a first data pattern detector 120a and a second data pattern detector 120b.

The first data pattern detector 120a detects a first data pattern in which a digital value difference between data to be displayed adjacent to each other in a horizontal or vertical direction is equal to or greater than a first predetermined reference value. This detection process is performed sequentially for all digital video data for one frame. Here, when the first data pattern is converted into the data voltage through the data driving circuit and then supplied to the liquid crystal display panel, the leakage current is increased by a large voltage difference in the horizontal direction, and the number of transitions of the data voltage in the vertical direction is increased. By increasing the power consumption means a pattern. In order to detect the first data pattern, the first data pattern detector 120a may compare only the most significant two bits of data to be displayed adjacent to each other in a horizontal or vertical direction. For example, when one data is implemented with 8 bits and the first reference value is 192, the first data pattern detection unit 120a may detect the first data pattern detection signal when the most significant two bits of the data to be compared are '11' and '00', respectively. Generate a call DS1. On the other hand, when the most significant two bits of the data to be compared are '11' and '01', the first data pattern detector 120a does not generate the first data pattern detection signal DS1. Meanwhile, the first data pattern detector 120a may compare the most significant 3 bits or the most significant 4 bits of data to be displayed adjacent to each other in the horizontal or vertical direction according to the size of the set first reference value.

The second data pattern detector 120b detects a second data pattern in which digital values of RGB data to be displayed on one pixel are each equal to or greater than a second predetermined reference value. This detection process is performed sequentially for all digital video data for one frame. Here, when the second data pattern is converted into the data voltage through the data driving circuit and displayed on the liquid crystal display panel, each of the RGB subpixels constituting one pixel is displayed close to the black gradation depending on how the liquid crystal behaves. In other words, the power consumption is increased by being displayed close to the white gradation. In the normally black mode in which the liquid crystal behaves, the light transmittance of the subpixel increases as the voltage charged in the subpixel increases, so that the RGB subpixels are displayed closer to the white gray levels as the digital values of the RGB data are larger. On the other hand, in the normally white mode, the light transmittance of a subpixel decreases as the voltage charged in the subpixel increases, so that the RGB subpixels are displayed closer to black gray levels as the digital values of the RGB data are larger. In order to detect the second data pattern, the second data pattern detector 120b may compare only the most significant three bits of the RGB data to be displayed on one pixel with the second reference value. For example, when one data is implemented with 8 bits and the second reference value is 224, when all the three most significant bits of the RGB data to be displayed on one pixel are '111', the second data pattern detection unit 120b may detect the second data pattern detection signal. (DS2) occurs. On the other hand, if any one of the three most significant bits of the RGB data to be displayed on one pixel is not '111', the second data pattern detector 120b does not generate the second data pattern detection signal DS2. Meanwhile, according to the size of the set second reference value, the second data pattern detector 120b may compare only the most significant four bits of the RGB data to be displayed on one pixel with the second reference value.

The adder 130 counts the first data pattern detection signal DS1 continuously supplied from the first data pattern detection unit 120a with respect to the digital video data RGB of one frame to obtain the first count signal CS1. Occurs. The adder 130 counts the second data pattern detection signal DS2 continuously supplied from the second data pattern detector 120b with respect to the digital video data RGB of one frame to generate the second count signal CS2. Will occur).

  The image attribute determiner 140 compares the first count signal CS1 and the second count signal CS2 from the adder 130 with a predetermined third reference value, so that the first and second data patterns occupy the entire screen. Detecting the ratio (%), and based on the detection result, it is determined whether the image embodied by the digital video data RGB for one frame is an image requiring large power consumption or an image requiring small power consumption. do. For example, when the ratio of the first data pattern or the second data pattern in the entire screen is 50% or more, the image property determiner 140 determines the image to be implemented as a large power consumption image. On the other hand, when the ratio of the first data pattern and the second data pattern occupies less than 50% of the entire screen, the image attribute determiner 140 determines that the image to be implemented is an image with low power consumption. Here, 50%, which is a criterion for determining image attributes, may vary depending on driving characteristics of the liquid crystal display panel.

The mode selection signal generator 150 generates a driving mode selection signal MDS in response to the image attribute determination signal PAttr from the image attribute determiner 140. That is, when the image attribute determination signal PAttr corresponding to the large power consumption is input, the mode selection signal generator 150 generates a low power consumption selection signal LPCM instructing the operation of the low power consumption mode. On the other hand, when the image attribute determination signal PAttr corresponding to the small power consumption is input, the mode selection signal generator 150 generates a normal power selection signal NPCM indicating the operation of the normal driving mode. The driving mode selection signals LPCM and NPCM generated from the mode selection signal generator 150 may be connected to a data driving circuit and used to pull-up or pull-down to determine a logic state of the CSC signal and the PWRC signal. Pull-Down) is used to control the equivalent circuit switch.

6A and 6B show that the switch of the pull-up equivalent circuit connected to the data driving circuit is controlled by the driving mode selection signals.

6A and 6B, a pull-up equivalent circuit P connected to the charge share circuit and the power control circuit of the data driving circuit 22 includes a high potential voltage source VCC and a ground voltage source GND. ) Consists of a resistor (R) and a switch (SW) connected in series. The charge share circuit and the power control circuit of the data driving circuit 22 are electrically connected to the output node Nout formed between the resistor R and the switch SW and are in a low logic state by a switching action of the switch SW. The CSC signal and the PWRC signal or the CSC signal and the PWRC signal in the high logic state are respectively supplied. In other words, the data driving circuit 22 responds to the low level CSC signal and the PWRC signal when the switch SW of the pull-up equivalent circuit is shorted by the input low power selection signal LPCM. As shown in FIG. 6A, the device operates in a low power consumption mode. On the other hand, the data driving circuit 22 is driven by the high-level CSC signal and the PWRC signal when the switch SW of the pull-up equivalent circuit is opened by the input normal power selection signal NPCM. In normal driving mode as shown in FIG. Meanwhile, instead of using the pull-up equivalent circuit P as shown in FIGS. 6A and 6B, a pull-down equivalent circuit may be used in the liquid crystal display of the present invention. In this case, since the positions of the switches and resistors are reversed relative to the pull-up equivalent circuit P around the output node, the switch of the pull-down equivalent circuit is a low power selection signal LPCM. It should be designed to open in response to), while it should be designed to short in response to the normal power select signal (NPCM).

7 is a flowchart illustrating a method of driving a liquid crystal display according to an exemplary embodiment of the present invention.

The driving method of the liquid crystal display according to the exemplary embodiment of the present invention will be described with reference to FIG. 7.

One frame of digital video data RGB is stored in the memory (S10).

The digital video data RGB stored in the memory is used to detect a first data pattern or a second data pattern that increases power consumption when the display image is implemented. Specifically, a first data pattern having a digital value difference (De-Do) between data to be displayed adjacent to each other in a horizontal or vertical direction is equal to or greater than a first predetermined reference value R1. In operation S20, a second data pattern in which the digital values PD of the RGB data to be displayed on one pixel is equal to or greater than a second predetermined reference value R2 is detected.

For the digital video data RGB of one frame, the first data pattern detection signal DS1 continuously generated through the detection process is counted to generate the first count signal CS1. For the digital video data RGB of one frame, the second data pattern detection signal DS2 continuously generated through the detection process is counted to generate the second count signal CS2 (S30).

By comparing the first count signal CS1 and the second count signal CS2 with a predetermined third reference value R3, a ratio (%) of the first and second data patterns in the entire screen is detected, and the detection result thereof. Based on the above, it is determined whether the image implemented by the digital video data RGB for one frame is an image requiring large power consumption or an image requiring small power consumption.

 When it is determined that the image requires a large power consumption, the image attribute determination signal corresponding thereto is generated to generate a low power consumption selection signal LPCM indicating the operation of the low power consumption mode. Then, the low power consumption selection signal LPCM is used to short the switch of the pull-up equivalent circuit and to supply the low level CSC signal and the PWRC signal to the data driving circuit, thereby bringing the liquid crystal display to the low power consumption driving mode. Operate. (S50)

On the other hand, if it is determined that the image requires a small power consumption, the image attribute determination signal corresponding thereto is generated to generate a normal power selection signal NPCM indicating the operation of the normal driving mode. By using the normal power selection signal NPCM, a pull-up equivalent circuit is opened to supply a high level CSC signal and a PWRC signal to the data driving circuit, thereby bringing the liquid crystal display into the normal driving mode. Operate. (S60)

As described above, the liquid crystal display and the driving method thereof according to the present invention allow the selection of the driving mode to be automatically made according to the property of the image, so that the image is required to operate in a low power consumption mode to reduce power consumption. In addition, in an image requiring small power consumption, the image is operated in the normal driving mode, thereby improving display quality.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

1 is an equivalent circuit diagram of a pixel included in a liquid crystal display panel.

2A is an output waveform diagram of a data driving circuit during normal driving.

2B is an output waveform diagram of a data driving circuit during low consumption driving.

3 shows a pull-up equivalent circuit connected to a conventional data driving circuit.

4 is a block diagram illustrating a liquid crystal display according to an exemplary embodiment of the present invention.

FIG. 5 is a detailed configuration diagram of a drive mode selection circuit shown in FIG. 4.

6A and 6B show that the switch of the pull-up equivalent circuit connected to the data driving circuit is controlled by the driving mode selection signals.

7 is a flowchart illustrating a method of driving a liquid crystal display according to an exemplary embodiment of the present invention.

<Description of Major Symbols in Drawing>

20 liquid crystal display panel 21 timing controller

21a: drive mode selection circuit 22: data drive circuit

23: gate driving circuit 110: memory

120: data pattern detector 120a: first data pattern detector

120b: second data pattern detector 130: adder

140: image attribute determiner 150: mode selection signal generator

Claims (8)

A liquid crystal display panel in which a plurality of data lines and a plurality of gate lines cross each other, and liquid crystal cells are formed in the crossing area thereof; By using the digital value of the input digital video data, it is determined whether the image to be displayed on the liquid crystal display panel by the digital video data requires a large power consumption or a small power consumption. A driving mode selection circuit for generating a driving mode selection signal differently; And In response to a low power consumption selection signal corresponding to the case where the image to be displayed among the drive mode selection signals requires a large power consumption, the image to be displayed has a small power consumption. And a data driving circuit operating in the normal driving mode in response to the normal power selection signal corresponding to the request. The method of claim 1, The drive mode selection circuit, The first data pattern in which the digital value difference between the data to be displayed adjacent to each other in the horizontal or vertical direction is equal to or greater than the first reference value, or the second data pattern in which the digital values of the RGB data to be displayed in one pixel are equal to or greater than the second reference value, respectively, are displayed in one screen. Detects the occupied ratio and generates the low power consumption selection signal indicative of the operation of the low power consumption mode when the detected ratio is greater than or equal to a third reference value, while the low power consumption selection signal indicates the operation of the low power consumption mode. And generating the normal power selection signal instructing an operation. The method of claim 2, The drive mode selection circuit, A memory for storing the input digital video data for one frame; A first data pattern detector for detecting a first data pattern whose digital value difference between data to be displayed adjacent to each other in a horizontal or vertical direction is equal to or greater than the first reference value; A second data pattern detector for detecting a second data pattern in which digital values of RGB data to be displayed on one pixel are each greater than or equal to the second reference value; The first data pattern detection signal from the first data pattern detection unit is counted on the one frame of digital video data to generate a first count signal, and the second data pattern detection unit detects the second data pattern from the second data pattern detection unit. An adder for counting the signals and generating a second count signal; The first count signal and the second count signal are compared with the third reference value to detect a percentage (%) of the first and second data patterns of the entire screen, and based on the detection result, the digital for one frame An image attribute determiner which determines whether the image implemented by the video data is an image requiring large power consumption or an image requiring small power consumption; And And a mode selection signal generator for generating the low power consumption selection signal or the normal power selection signal based on the image attribute determination signal from the image attribute determination unit. The method of claim 3, wherein The data driving circuit, A charge share circuit, a power control circuit for controlling its output buffer power, and a pull-up equivalent circuit; And the charge share circuit is controlled by a charge share control signal generated by the pull-up equivalent circuit, and the power control circuit is controlled by a power control signal generated by the pull-up equivalent circuit. The method of claim 4, wherein The data driving circuit, Reducing the number of transitions of the data voltage by performing charge sharing only when the polarity of the data voltage charged in the liquid crystal cells is inverted by the low level charge share control signal generated in response to the low power consumption selection signal; And a data voltage rising slope to a target point when the data voltage is charged to the liquid crystal cells by a low level power control signal generated in response to the low power consumption selection signal. The method of claim 4, wherein The data driving circuit, Performing charge sharing between data voltages charged in the liquid crystal cells by a high level charge share control signal generated in response to the normal power selection signal; And an inclination of the data voltage rise to a target point when charging the data voltage to the liquid crystal cells by a high level power control signal generated in response to the normal power selection signal. A method of driving a liquid crystal display device having a liquid crystal display panel having a plurality of data lines and a plurality of gate lines intersecting and having liquid crystal cells formed at an intersection thereof, and a data driving circuit supplying data voltages to the liquid crystal cells. By using the digital value of the input digital video data, it is determined whether the image to be displayed on the liquid crystal display panel by the digital video data requires a large power consumption or a small power consumption. A first step of generating a driving mode selection signal differently accordingly; And The data driving circuit is operated in a low power consumption mode in response to a low power consumption selection signal corresponding to a case where the image to be displayed among the drive mode selection signals requires a large power consumption, and the image to be displayed among the drive mode selection signals. And a second step of operating the data driving circuit in the normal driving mode in response to the normal power selection signal corresponding to the case where the small power consumption is required. The method of claim 7, wherein The first step, Storing the input one-digit digital video data; Detecting a first data pattern in which a digital value difference between data to be displayed adjacent to each other in a horizontal or vertical direction is equal to or greater than a first reference value; Detecting a second data pattern in which digital values of RGB data to be displayed on one pixel are each equal to or greater than a second reference value; The digital video data of one frame is counted to generate a first count signal by counting the detected first data pattern detection signal, and to generate a second count signal by counting the detected second data pattern detection signal. Doing; The first count signal and the second count signal are compared with a third reference value to detect a percentage (%) of the first and second data patterns of the entire screen, and based on the detection result, the digital video of the one frame Determining whether the image implemented by the data is an image requiring large power consumption or an image requiring small power consumption; And And generating the low power consumption selection signal or the normal power selection signal based on the image determination result.

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