KR20090095086A - Flash memory device and erase method thereof - Google Patents

Abstract

A flash memory device and an erasing method thereof are provided to perform a 1 bit erasing operation by changing a state of a memory cell designated by a row address and a column address. A memory cell array(110) comprises a plurality of blocks having memory cells arranged in a cross region of rows and columns. A row selection circuit(120) selects a block in response to a first row address. A page buffer circuit(130) senses data stored to the memory cells of the selected block, or writes the data to the memory cells. A data buffer circuit(170) stores data sensed through the page buffer circuit in 1 bit erasing operation. The data buffer circuit changes the data of the memory cell in which the 1 bit erasing operation among stored data is performed into an erasing state in response to a second row address and a column address. The data of the data buffer circuit is written to the memory cells corresponding to the block selected by the page buffer circuit.

Description

Flash memory device and its erasing method {FLASH MEMORY DEVICE AND ERASE METHOD THEREOF}

The present invention relates to a flash memory device, and more particularly to a flash memory device capable of selectively erasing specific bits.

Flash memory is nonvolatile memory and is electrically erasable programmable read-only memory (EEPROM). Since flash memory devices can be electrically erased and written, applications to system programming or auxiliary storage devices requiring continuous updating are expanding. In addition, flash memories are widely used in computers, memory cards, and the like because they have a function of electrically erasing data of cells collectively. The flash memory device is a nonvolatile memory device. Even when the drive power is not supplied, the data written to the cell is not lost.

Flash memory is divided into NOR type and NAND type according to the connection state of cells and bit lines. In general, NOR-type flash memory is disadvantageous for high integration, but there is an advantage that it can easily cope with high speed. NAND flash memory uses less cell current than NOR flash memory, and thus has an advantage of high integration. NAND flash memory, which is useful for high-density and large capacity, is widely used in mobile communication environments, set-top boxes, and game machines, and its application range is increasing.

As is well known, memory cells of a NAND flash memory are erased and programmed using F-Nordheim tunneling current. NOR flash memory cells, as is well known, are programmed using a channel hot electron scheme and erased using F-N tunneling current.

Flash memory includes a memory cell array consisting of a plurality of blocks or sectors. Blocks or sectors include a plurality of memory cells arranged in the intersection of rows (or wordlines) and columns (or bitlines). A row consists of one or more pages. Hereinafter, the programmed memory cell is defined as storing data '0' and the erased memory cell storing data '1'.

A general flash memory first erases memory cells to perform a program operation. After the flash memory erases the memory cells, the erased memory cells maintain or program the data '1' state to maintain the data '0' state. The erase operation is performed in units of blocks or sectors, and the program and read operations are performed in units of pages. The data states of the memory cells of the selected page may be changed during the page-based program operation. That is, since the data state of any memory cell can be changed from data '1' to '0', program operation in units of 1 bit is possible. Therefore, the flash memory may perform a program operation of changing 1-bit information from data '1' to '0'.

However, when the 1-bit information is changed from '0' to '1', since the erase operation is performed in units of blocks or sectors, a complicated operation is required. For example, data in a block or sector containing any memory cell on which a one bit erase operation is to be performed is copied to any other area. Thereafter, the erase operation is performed in units of blocks or sectors. Through the erase operation, memory cells of a block or sector are changed to a data '1' state. Data copied to any other area is programmed in the remaining memory cells except the memory cell in which the 1-bit erase operation is to be performed. Therefore, the 1 bit erase operation is inconvenient and requires complicated work. Although there is an E2PROM capable of 1-bit erasing among nonvolatile memories, the unit cell has a larger size than the flash memory, which is disadvantageous in terms of integration.

An object of the present invention is to provide a flash memory device capable of performing a 1-bit erase operation and an erase method thereof.

A flash memory device according to an aspect of the present invention comprises: a memory cell array consisting of a plurality of blocks having memory cells arranged in an intersection region of rows and columns; A row selection circuit for selecting a block in response to the first row address; A page buffer circuit for sensing data stored in memory cells of the selected block or writing data to the memory cells; And a data buffer circuit for storing data sensed through the page buffer circuit during a 1-bit erase operation, wherein the data buffer circuit erases one bit of the stored data in response to a second row address and a column address. The data of the memory cell in which the operation is to be performed is changed to the erased state, and the data of the data buffer circuit is written to corresponding memory cells of the selected block by the page buffer circuit, respectively.

In this embodiment, after the data of the selected memory block is stored in a data buffer, the cells of the selected block are erased.

In this embodiment, the first row address is an address for selecting the block, and the second row address is an address for selecting the row.

In this embodiment, the first row address and the second row address constitute a row address.

In this embodiment, the data buffer circuit is a volatile memory device.

In this embodiment, the data buffer circuit is composed of an ESRAM or a DRAM.

In this embodiment, the data buffer circuit comprises: a data buffer having cells arranged in an intersection region of rows and columns; A row decoder for driving a row of the data buffer in response to the second row address; And a column decoder for driving a column of the data buffer in response to the column address, wherein the data buffer corresponds to the size of the block.

In this embodiment, the memory cells of the memory cell array designated by the row address and the column address correspond to the cells of the data buffer designated by the second row address and the column address.

According to another aspect of the present invention, there is provided a memory cell array including a plurality of blocks having memory cells arranged in an intersection area of rows and columns, and cells corresponding to a size of the block and arranged in an intersection area of rows and columns. A one-bit erase operation of a flash memory device including a data buffer circuit having: includes dividing a row address into a first row address and a second row address; Selecting a block of the memory cell array by the first address; Copying data stored in memory cells of the selected block to cells of a corresponding data buffer circuit; Changing data of a cell of a data buffer specified by the second address and a column address to an erase state; Performing an erase operation on cells of a selected block of the memory cell array; And writing data stored in cells of the data buffer circuit into corresponding memory cells of the selected block, respectively.

In this embodiment, the first row address is an address for selecting the block, the second row address is an address for selecting the row, and the first row address and the second row address are row addresses. Configure

In this embodiment, the memory cells of the memory cell array designated by the row address and the column address correspond to the cells of the data buffer designated by the second row address and the column address.

In this embodiment, the data buffer circuit is composed of an SRAM or a DRAM.

The flash memory device according to the present invention can perform a 1 bit erase operation.

Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention.

1 is a block diagram of a flash memory device according to an embodiment of the present invention.

Referring to FIG. 1, a flash memory device 100 according to an exemplary embodiment may include a memory cell array 110, a row select circuit (X-SEL) 120, a page buffer circuit 130, and a column select circuit ( Y-SEL) 140, a voltage generation circuit 150, a control logic 160, and a data buffer circuit 170.

The memory cell array 110 is composed of a plurality of blocks (or sectors) (described in FIG. 2). Each of the plurality of blocks includes a plurality of memory cells arranged in an intersection area of the rows (ie, word lines) WL1 to WLm and the columns (ie, bit lines) BL1 to BLn.

Memory cells are similar to standard MOSFET transistors except that they have two gates. That is, the memory cells of the memory cell array 110 are each a P-type semiconductor substrate, an N-type source and drain regions, a channel region between the source and drain regions, a floating gate for storing charge, and on the gate. It consists of a control gate located.

The row address X_Addr includes a first row address X_AddrM and a second address X_AddrL. In a 1-bit erase operation, the first row address X_AddrM is used to erase a block including memory cells for performing 1-bit erase. The second address X_AddrL is used when reading data of the selected block of the memory cell array 110 and as a row address of the data buffer 171 for temporarily storing the data. In addition, the second row address X_AddrL is used to write data from the data buffer 171 to the selected block of the memory cell array 110.

In the program operation, the row selection circuit 120 selects an arbitrary word line in response to an externally provided row address X_Addr and provides a word line voltage corresponding to the selected word line. In the 1-bit erase operation, the row select circuit 120 selects an arbitrary block in response to the first row address X_AddrM of the row address X_Addr. In addition, the row selection circuit 120 applies a voltage necessary for the erase voltage generated by the voltage generation circuit 150 to the word lines of the selected block.

The page buffer circuit 130 temporarily stores external data provided through the column selection circuit 140 during a program operation. The page buffer circuit 130 sets bit lines of the memory cell array 110 to a specific voltage (for example, a power supply voltage Vcc or a ground voltage GND) according to the stored data. The page buffer circuit 130 senses data stored in selected memory cells through bit lines in a read or verify operation. Data sensed by the page buffer circuit 130 is output to the outside by the column select circuit 140. The page buffer circuit 130 senses data of the selected block in the 1-bit erase operation. The column select circuit 140 provides the data buffer circuit 170 with data of a block sensed by the page buffer circuit 130 in response to the column address Y-Addr during a 1-bit erase operation. In addition, the page buffer circuit 130 writes data provided from the data buffer 171 into the selected block during the 1-bit erase operation.

The voltage generation circuit 150 is controlled by the control logic 160 and generates voltages required for program, erase, and read operations of the flash memory device 100. The control logic 160 controls all operations related to program, erase, read, and 1-bit erase operations of the flash memory device 100.

The data buffer circuit 170 includes a data buffer 171, a row decoder 172, and a column decoder 173. The data buffer 171 is a size corresponding to any one block of the memory cell array 110 and includes cells arranged in an intersection area of rows and columns. The data buffer 171 stores data of the selected block of the memory cell array 110 provided through the column select circuit 140. The row decoder 172 drives an arbitrary row in response to the second row address X_AddrL of the row address X_Addr. The column decoder 173 drives any one column in response to the column address Y_Addr.

The control logic 160 performs a 1-bit erase operation in response to an externally provided 1-bit erase command. When performing a 1 bit erase operation, the control logic 160 divides the row address X_Addr from the externally provided address information Address into a first row address X_AddrM and a second row address X_AddrL. The first row address X_AddrM and the second row address X_AddrL are provided to the row selection circuit 120. The second row address X_AddrL is provided to the row decoder 173 of the data buffer circuit 17. The column address Y_Addr among the addresses is provided to the column decoder 173 of the column select circuit 130 and the data buffer circuit 17.

In the 1-bit erase operation, one block of the memory cell array 110 including the memory cell to which the 1-bit erase operation is to be performed is selected. Data of the selected block is copied to the data buffer 171 of the data buffer circuit 170. The row decoder 172 drives the corresponding row in response to the second row address X_AddrL, and the column decoder 173 drives the corresponding column in response to the column address Y_Addr. Therefore, the data state of the cell of the data buffer 171 designated by the second row address X_AddrL and the column address Y_Addr is changed to '1'. Thereafter, the memory cells of the selected block of the memory cell array 110 are erased. After the memory cells of the selected block are erased, the data of the data buffer 171 is written to the selected sector of the memory cell array 110. The cells of the data buffer 171 designated by the second row address X_AddrL and the column address Y_Addr correspond to the memory cells of the memory cell array 110 on which the 1-bit erase operation is to be performed. By this operation, the flash memory device 100 may perform a 1-bit erase operation.

The data buffer circuit 170 may be implemented as a memory capable of changing 1 bit data into data '1'. For example, the data buffer circuit 170 may be implemented as a volatile memory device such as an SRAM or a DRAM capable of converting 1 bit data into data '1'.

2 to 6 are diagrams illustrating changes in data states of cells of a memory cell array and cells of a data buffer in a 1-bit erase operation.

The exemplary memory cell array 110 shown in FIGS. 2 to 6 is composed of eight rows X and eight columns Y, and address information corresponding to each row and column is shown in parentheses. have. Blocks consist of two rows each. Rows may consist of one or more pages. The rows exemplarily shown in FIGS. 2 to 6 will be organized into one page for ease of description. In such a case, the row may be called a page. Rows (0, 1) constitute a zero block, rows (2, 3) constitute a first block, rows (4, 5) constitute a second block, and rows (6, 7) constitute a third block. Since the rows and columns are composed of eight, the row and column address information is each composed of three bits. The upper two bits of the three-bit row address X_Addr are the first row address X_AddrM, and the lower one bit is the second row address X_AddrL. For example, the row address 010 points to the row 2 of the first block, the upper two bits 01 of the row address 010 are the first row address X_AddrM, and the lower one bit 0 is Second row address X_AddrL. In an exemplary embodiment, blocks are composed of two rows, but the sizes of the blocks may be set differently. In this case, the number of bits constituting the second row address X_AddrL will vary. For example, if the blocks each consist of eight rows, the second row address X_AddrL may consist of three bits.

The exemplary data buffers 171 shown in FIGS. 2 through 6 are sizes corresponding to the blocks of the memory cell array 110. Accordingly, the data buffer 171 is composed of two rows X and eight columns Y, and an address corresponding to each row and column is indicated in parentheses. The row of the data buffer 171 will be selected by the second row address X_AddrL.

Hereinafter, a 1-bit erase operation for changing the data of the memory cells indicated by the row 2 and the third column 011 of the first block from the data '0' to the data '1' will be described.

2 illustrates a data state of exemplary memory cells of a memory cell array 110 of a flash memory device.

Referring to FIG. 2, in a 1-bit erase operation, a first block including a memory cell in which a 1-bit erase operation is to be performed is selected by the first row address 01 of the row address 010.

FIG. 3 shows that data stored in memory cells of the selected first block of the memory cell array 110 illustrated in FIG. 2 is copied to the data buffer 171.

Referring to FIG. 3, data stored in memory cells of the selected first block of the memory cell array 110 are copied to corresponding cells of the data buffer 171.

4 shows that the cell of the data buffer 171 corresponding to the memory cell of the selected block in which the 1-bit erase operation is to be performed is changed to data '1'.

Referring to FIG. 4, the cell of the data buffer 171 selected by the second row address 0 and the column address 011 of the row address 010 is changed to data '1'. The cells of the memory cell array 110 indicated by the row address 010 and the column address 011 are selected from the data buffer 171 selected by the second row address 0 and the column address 011 of the row address 010. Corresponds to the cell.

5 shows a state in which memory cells of a selected block of the memory cell array 110 are erased.

Referring to FIG. 5, the memory cells of the first block selected by the first row address 01 of the row address information 010 are erased. Thus, the memory cells of the first block each store a data '1' state.

6 illustrates a state in which data stored in cells of the data buffer 171 are written to memory cells of a selected block.

Referring to FIG. 6, data stored in cells of the data buffer 171 are written to corresponding memory cells of the selected first block, respectively.

As a result, the memory cell designated by the row address 010 and the column address 011 changes from the data '0' to the data '1' state. Therefore, the flash memory device 100 may perform a 1 bit erase operation.

The flash memory device 100 of the present invention has been described as a NAND flash memory device including a page buffer 130 as an embodiment. However, the flash memory device 100 may be applied to a Noah flash memory device including a data input / output circuit instead of the page buffer 130. The data input / output circuitry includes a write driver for writing data and a sense amplifier for sensing data stored in the cell. In the NOR flash memory device, a sector composed of a plurality of rows may be selected instead of the aforementioned block.

The erase operation of the cells of the selected block may be performed in parallel with the operation of changing the data of the cells of the data buffer selected by the second row address X_AddrL and the column address Y_Addr to '1', or may be performed first or later. have.

7 is a flowchart illustrating an erase operation of a flash memory device according to an embodiment of the present invention.

In step S10, when the 1-bit erase operation is performed, the row address X_Addr is divided into a first row address X_AddrM and a second row address X_AddrL by the control logic 160.

In step S20, an arbitrary block of the memory cell array 110 is selected by the first row address X_AddrM among the row addresses X_Addr. Data stored in the memory cells of the block selected in step S30 is copied to the corresponding cells of the data buffer 171, respectively.

In step S40, the data of the cell of the data buffer 171 designated by the second row address X_AddrL and the column address Y_Addr of the row address X_Addr is changed to '1'. The cells of the memory cell array 110 indicated by the row address X_Addr and the column address Y_Addr are connected to the data buffer 171 selected by the second row address X_AddrL and the column address Y_Addr among the row addresses X_Addr. Corresponds to the cell.

In step S50, an erase operation is performed on the cells of the selected block of the memory cell array 110. In operation S60, the data stored in the cells of the data buffer 171 are written into corresponding memory cells of the selected block.

As a result, the memory cell designated by the row address X_Addr and the column address Y_Addr is changed from the data '0' to the data '1' state. Therefore, the flash memory device 100 may perform a 1 bit erase operation.

The erase operation of the cells of the selected block may be performed in parallel with the operation of changing the data of the cells of the data buffer selected by the second row address X_AddrL and the column address Y_Addr to '1', or may be performed first or later. Thus, step S50 may be performed in parallel with step S40 or may be performed first or later.

8 is a schematic diagram of a computing system including a flash memory device according to the present invention.

The semiconductor memory device is a nonvolatile memory device capable of retaining stored data even when power is cut off. With the increasing use of mobile devices such as cellular phones, PDA digital cameras, portable game consoles, and MP3Ps, semiconductor memory devices are becoming more widely used as code storage as well as data storage. Semiconductor memory devices may also be used in home applications such as HDTV, DVD, routers, and GPS. A computing system including the semiconductor memory device 100 according to the present invention is schematically illustrated in FIG. 8.

The computing system according to the present invention includes a microprocessor 400 electrically connected to a bus 30, a user interface 500, a modem 300 such as a baseband chipset, a memory controller 200, and a semiconductor memory. Device 100. The memory controller 200 and the semiconductor memory device 100 constitute a memory system. The semiconductor memory device 100 may be configured substantially the same as that shown in FIG. 4. In the semiconductor memory device 100, N-bit data (N is an integer of 1 or larger) to be processed / processed by the microprocessor 400 may be stored through the memory controller 200.

When the computing system according to the present invention is a mobile device, a battery 600 for supplying an operating voltage of the computing system will be further provided. Although not shown in the drawings, the computing system according to the present invention may further be provided with an application chipset, a camera image processor (CIS), a mobile DRAM, and the like. Self-explanatory to those who have learned.

As described above, the best embodiment has been disclosed in the drawings and the specification. Although specific terms have been used herein, they are used only for the purpose of describing the present invention and are not used to limit the scope of the present invention as defined in the meaning or claims. Therefore, those skilled in the art will understand that various modifications and equivalent other embodiments are possible. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

1 is a block diagram of a flash memory device according to an embodiment of the present invention;

2 to 6 show changes in data states of cells of a memory cell array and cells of a data buffer shown in FIG. 1 during a 1-bit erase operation;

7 is a flowchart illustrating an erase operation of a flash memory device according to an embodiment of the present disclosure; And,

8 is a schematic diagram of a computing system including a flash memory device according to the present invention.

<Description of Signs for Main Parts of Drawings>

100: flash memory device 110: memory cell array

120: row selection circuit 130: page buffer circuit

140: column selection circuit 150: voltage generation circuit

160: control logic 170: data buffer circuit

171: data buffer 172: row decoder

173: thermal decoder

Claims (14)

A memory cell array composed of a plurality of blocks having memory cells arranged in an intersection region of rows and columns; A row selection circuit for selecting a block in response to the first row address; A page buffer circuit for sensing data stored in memory cells of the selected block or writing data to the memory cells; And A data buffer circuit for storing data sensed through the page buffer circuit in a 1-bit erase operation, The data buffer circuit changes the data of the memory cell in which the 1-bit erase operation is to be performed to the erase state in response to the second row address and the column address, and the data of the data buffer circuit is stored in the page buffer circuit. And write to corresponding memory cells of the selected block, respectively. The method of claim 1, And after the data of the selected memory block is stored in a data buffer, the cells of the selected block are erased. The method of claim 1, And the first row address is an address for selecting the block, and the second row address is an address for selecting the row. The method of claim 3, wherein And the first row address and the second row address constitute a row address. The method of claim 1, And the data buffer circuit is a volatile memory device. The method of claim 5, wherein And the data buffer circuit is composed of an ESRAM or a DRAM. The method of claim 1, The data buffer circuit is A data buffer having cells arranged in an intersection region of rows and columns; A row decoder for driving a row of the data buffer in response to the second row address; And A column decoder for driving a column of the data buffer in response to the column address; And the data buffer corresponds to the size of the block. The method of claim 4, wherein And a memory cell of a memory cell array designated by said row address and said column address corresponds to a cell of a data buffer designated by said second row address and said column address. A memory cell array comprising a plurality of blocks having memory cells arranged in an intersection area of rows and columns and a data buffer circuit corresponding to the size of the block, the data buffer circuit having cells arranged in an intersection area of rows and columns In a 1 bit erase operation of a flash memory device: Dividing the row address into a first row address and a second row address; Selecting a block of the memory cell array by the first address; Copying data stored in memory cells of the selected block to cells of a corresponding data buffer circuit; Changing data of a cell of a data buffer specified by the second address and column address to an erase state; Performing an erase operation on cells of a selected block of the memory cell array; And And writing data stored in cells of the data buffer circuit to corresponding memory cells of the selected block, respectively. The method of claim 9, The first row address is an address for selecting the block, the second row address is an address for selecting the row, and the first row address and the second row address constitute a row address. 1 bit erase method. The method of claim 9, And a memory cell of a memory cell array designated by said row address and said column address corresponds to a cell of a data buffer designated by said second row address and said column address. The method of claim 9, And the data buffer circuit is composed of an SRAM or a DRAM. A flash memory device; And A memory controller configured to control the flash memory device, Wherein said flash memory device comprises the one as claimed in claim 1. A microprocessor; A flash memory device; A memory controller configured to control the flash memory device at the request of the microprocessor, The flash memory device comprising the one of claim 1.

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