KR101598379B1 - Non-volatile Memory Device - Google Patents

Abstract

Provided is a nonvolatile semiconductor memory device capable of speeding up the writing and reading operations of data and minimizing the influence on the already established low threshold voltage. A multi-bit data memory cell array including a multi-level cell divided into two groups and configured to allocate and store one multi-bit data among the groups, a read operation for reading data from the multi-bit data memory cell array, A control circuit including a data processing circuit for performing a program operation for writing data in the data memory cell array and a control circuit for controlling the operation of the data processing circuit, Level cell and the data corresponding to the threshold voltage distribution of the multilevel cell so that the shift of the threshold voltage due to the writing of the data is the same regardless of the writing order.

Nonvolatile semiconductor memory device, multilevel cell, write count, write order

Description

[0001] Non-volatile memory device [0002]

The present invention relates to a nonvolatile semiconductor memory device, and more particularly, to a nonvolatile semiconductor memory device capable of improving a write speed and a read speed of a memory.

The nonvolatile semiconductor memory device, particularly the flash memory, is capable of electrically modifying the data and can keep the data even when the power is turned off. Therefore, for example, for data storage of portable devices such as mobile phones and digital cameras And is widely used as a memory device. In order to realize a larger capacity and a lower cost, research and development of a flash memory for storing multi-bit data of two or more bits in one memory cell has been actively carried out. For example, a nonvolatile semiconductor memory device has been proposed in which two bits of data are stored in one memory cell, that is, four memory cells have different threshold voltages.

6A and 6B are diagrams showing a relation between a threshold voltage distribution of a memory cell of the nonvolatile semiconductor memory device and data and a method of writing and reading. Referring to FIGS. 6A and 6B, a unit of data to be written at one time is divided into a first page and a second page so that any page can be written first. Further, information on the presence / absence of writing on the first page is stored in another memory device, thereby speeding up the read operation.

In the above invention, the method of shifting the threshold voltage is changed according to the order of the write page. The shift amount of the threshold voltage of the program from the first page to the second page shown in Fig. 6B differs greatly with respect to the shift of the threshold voltage of the program from the second page to the first page shown in Fig. 6A. Thus, the writing speed becomes maximum at the time of the second writing in the case of FIG. 6B. Therefore, even if the average writing speed is improved, there is a problem that the writing speed on the specification is not improved so much.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a nonvolatile semiconductor memory device capable of reducing a shift amount of a threshold voltage and improving writing speed on a spec. It is another object of the present invention to provide a nonvolatile semiconductor memory device capable of preventing other low threshold voltage fluctuations which have already been established at the time of writing a larger threshold voltage, by the process miniaturization.

According to an embodiment of the present invention, there is provided a multi-bit data memory cell array including a multi-level cell divided into two groups and configured to allocate and store one multi-bit data among the groups, Level memory cell array, a write-number-of-memory cell array for storing the number of times of writing into the multi-level cell, a read operation for reading data from the multi-bit data memory cell array And a data processing circuit for performing a program operation for writing data into the multi-bit data memory cell array, and a control circuit for controlling the operation of the data processing circuit.

The control circuit performs data allocation corresponding to the threshold voltage distribution of the multilevel cell so that the movement of the threshold voltage by the first writing and the movement of the threshold voltage by the second writing are the same regardless of the writing order And the correcting program operation is controlled. By constituting in this way, the movement amount of the threshold voltage is averaged and the writing speed is improved.

In an exemplary embodiment, each of the groups is capable of storing data equal to or larger than the maximum number of words that can be written at one time. With this configuration, data can be written in units of words for each group.

According to another embodiment of the present invention, the threshold voltages of the "state 0", "state 1", "state 2", and "state 3" A memory cell array for storing a write sequence for storing a write sequence in which one of said two groups has previously written data, and a multi-bit cell array including a multi-level cell configured to store and store one multi- An array, a write-number storing memory cell array for storing the number of times of writing to the multi-level cell, a read operation for reading data from the multi-bit data memory cell array, and a program operation for writing data to the multi- And a control circuit for controlling the operation of the data processing circuit.

The control circuit sets the width of the target threshold voltage at the time of the first writing to be larger than the width of the threshold voltage of the "state 1" and the "state 2" at the time of the second writing, The threshold voltage of the " state 2 "is set lower than the threshold voltage of the " state 2 " so that the threshold voltage of the" state 2 "does not move at the time of writing into the state 3 ". By constituting in this manner, the first writing can be written faster than the conventional writing method. Also, by the refinement of the process, it is possible to solve the problem that the threshold voltage of the "state 2" fluctuates at the time of writing to the "state 3 ".

In the exemplary embodiment, the second writing is performed in the order of "state 3", "state 2", and "state 1". With this structure, it is possible to prevent the destruction of data in the memory cell having a low threshold voltage.

In the exemplary embodiment, the write data is logic "11" to "state 0", logic "01" to "state 1", logic "00" "10" By doing so, the shift amount of the threshold voltage can be reduced.

According to the embodiment of the present invention, it is possible to increase the speed of data write and read operations, and to minimize the influence on the already low threshold voltage at the time of the second maximum voltage writing.

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

1 is a diagram showing a schematic configuration of a nonvolatile semiconductor memory device 100 according to an embodiment of the present invention.

The multi-bit data memory cell array 102 includes a plurality of word lines (Word Line) and a plurality of bit lines, and a plurality of multi-level cells are formed in a matrix at intersections of a plurality of word lines and a plurality of bit lines . A word line control circuit 110 and a bit line control circuit 108 are connected to the multi-bit data memory cell array 102.

The multi-bit data memory cell array 102 is divided into a plurality of groups, and is configured to allocate and store one multi-bit data among corresponding multi-level cells of each group. In the case of four multi-bit data, two groups are divided and an identification address for selecting a group is attached.

In the nonvolatile semiconductor memory device of the present invention, the memory cell array 106 for storing the write sequence for storing the order for each write unit and the memory cell array 104 for storing the write number for storing the write number in the multi-level cell Are arranged adjacent to the multi-bit data memory cell array 102. The word line control circuit 110 is a circuit for selecting a predetermined word line in the memory cell array 102 and applying voltages required for reading (reading), writing (programming), and erasing. The decoder 112 controls the word line control circuit 110 to select a predetermined word line. The bit line control circuit 108 includes a plurality of data latch circuits (not shown), reads data of the multi-level cells in the memory cell array 102 through the bit lines, or reads the data of the multi-level cells in the memory cell array 102 (Verify) or applies a write voltage to the multi-level cell in the memory cell array 102 through the bit line to perform the write operation.

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A column gate 114, a column decoder 116, and a data input / output circuit 118 are connected to the bit line control circuit 108. The data latch circuit in the bit line control circuit 108 selects the data of the multi-level cell selected by the column decoder 116 and read to the data latch circuit via the column gate 114 and the data input / output circuit 118, And is output to the outside from the terminal I / O.

The write data input from the outside to the data input / output terminal I / O is input to the data latch circuit selected by the column gate 114 and the column decoder 116 via the data input / output circuit 118. The control circuit 120 is a circuit for controlling the entire nonvolatile semiconductor memory device 100 and includes a word line control circuit 110, a row decoder 112, a bit line control circuit 108, a column gate 114, The column decoder 116, the data input / output circuit 118, and the high voltage generation circuit 122 to perform various controls such as reading, writing, and erasing operations.

The control circuit 120 writes the number of times of writing into the multi-level cells in the memory cell array 102 into the memory cell array 104. [ In addition, the order of writing from which group of the multi-bit data memory cell array 102 divided into a plurality of groups is written in the memory cell array 106 is also written. In addition, the multi-bit data of each group is read with reference to the write sequence stored in the memory cell array 106 and the write sequence stored in the memory cell array 104 in the read operation.

The control circuit 120 is supplied with a chip enable signal / CE, a write enable signal / WE, a read enable signal / RE, A command latch enable signal CLE, an address latch enable signal ALE and a write protect signal / WP are input and ready / The signal RY / BY is outputted.

Also, the address, data, and commands input from the data input / output terminal I / O are input to the control circuit 120 through the data input / output circuit 118. The high voltage generating circuit 122 is a circuit for generating a voltage necessary for the nonvolatile semiconductor memory device 100 to perform the read, write, and erase operations. In the nonvolatile semiconductor memory device 100, when data is programmed and stored in the multi-level cell in the memory cell array 102, electrons are injected into the floating gate of the memory cell. In this case, a state in which no electrons are collected in the floating gate is recognized as a logic "1", and a state in which electrons are collected by injection as a logic "0".

In the case of multi-bit data, for example, four data, four "state 0", "state 1", "state 2" Quot; to " state 1 ", logic "01 ", " state 2 ", and logic" 00 " In addition, the allocation of the state and the logic is not limited to the above-described allocation, and it is also possible to appropriately change the allocation.

Next, a method of writing (programming) to the nonvolatile semiconductor memory device of the present invention will be described.

First, the memory cell array 102, which holds multi-bit data (for example, four), is divided into two groups, and one multi-bit data group is allocated and stored. In this case, each group is allowed to store data of a maximum number of words or more that can be written at one time. That is, the memory cells of each physically separated group can store one multi-bit data. In this case, each group is made to be able to store data of a maximum number of words which can be written at one time. Here, the two divided groups are referred to as a group A and a group B, respectively.

FIG. 2 is a diagram showing variations in threshold voltage due to writing. FIG. There are two cases of writing in the order of writing from the group A to the group B and writing in the order of the group A to the group A. The writing of the threshold voltage by the first writing and the writing of the second The shift of the threshold voltage by the writing of the threshold voltage is the same as shown in Fig.

In Fig. 2, R1 to R3 indicate the level of the read voltage, and V1 to V4 indicate the level of the verify voltage, respectively. The state in which the first writing is performed and the writing is performed is set as the logic "10 ". The verify voltage of logic "10 " at this time is V2. The width of the threshold voltage to be the target of the first writing is set to be larger than the width of the threshold voltage of the "state 1" and the "state 2" at the time of the second writing. In this way, since the width of the threshold voltage in the state in which the logic "10" in the first writing is written is not difficult to compare with the width of the threshold voltages in the logic "01" and "00" in the second writing, Is not necessary, and it can be written in a bad shape. Therefore, the first writing can be performed faster than the conventional writing as described in Patent Document 1.

The target threshold voltage is set to V2 lower than the threshold voltage V3 of "state 2 " so that the threshold voltage of the" state 2 "does not move at the time of writing to the second state 3. This is to prevent the data of the memory cell having a low threshold voltage from being destroyed by the writing of the adjacent memory cell.

This problem can be solved by using the writing method of the present invention because the distance between the memory cells is shortened due to the miniaturization of the process.

The verify voltage at the time of writing the data of logic "01" to the " state 1 "is V1, the verify voltage at the time of writing the logical" 00 & 3 ", the verify voltage when writing the logic "10" data is V4. The second write time is slower than the conventional write time, but the sum of the first and second write times becomes the same as in the conventional write. In the second write, the logic "10" having the first highest threshold voltage is written so as to be assigned to "state 3", and then writing is performed in the order of logic "00" and logic "01".

This is because, as described above, it prevents the destruction of data in memory cells of low threshold voltages. The control circuit 120 writes the logic "11" when writing from the group A to the writing sequence memory cell array 106, and the logic "10" when writing from the group B, respectively. In the case where only the first data is written in the memory cell array 104 for storing the write number, the logic "11" is written. When the second data is written, the logic "10" or the logic "00" is written .

Next, the reading of multi-bit data will be described. Four cases of reading are described as a plurality. In the case of the present invention, when data of the same address is stored as four, three times of reading are required. In the conventional reading method as described in Patent Document 1, since data of addresses other than the writing unit is stored as four pieces, the upper part of the address is judged to be read once, and the lower part of the address is judged to be outputted twice I can do it.

However, in the present invention, the number of readings is determined by the number of writings irrespective of the read address. That is, the number of times of reading after the first writing is one time, and the reading after the second writing is two times. The read data of the two groups A and B are judged by the difference between the read group, the write order, and the write number. The first read voltage is determined by R1, and in the case of write once, the output data is determined by reading one time. In the case of the write twice, when the group to be read is written first, it is read with the second read voltage R3 and the output data is judged from the first and second data. In the case of writing twice, when the group to be read is written later, it is read with the second read voltage R2, and the output data is judged by the second data. The method of discriminating the output data by the difference between the reading group, the writing order, and the writing number is summarized in Fig.

Figures 4 and 5 are flow charts that describe the reading method in more detail.

Fig. 4 shows the read flow of the group A, and Fig. 5 shows the read flow of the group B, respectively. When reading of the group A starts (step 400), reading is performed with the voltage R1 (step 402). Then, the memory cell array 104 for storing the number of times of writing is accessed and checked (step 404). If the number of times is one, the process proceeds to step 406, and if two times, the process proceeds to step 416. Then, in step 406, access is made to the write sequence memory cell array 106 to check which of the group A and the group B has written first.

When writing is performed first from the group B, a logic 1 (H) is output (step 408). When writing is performed from the group A, H and L are read according to the logic read in the first reading (step 410) (steps 412 and 414). If it is determined in step 404 that the number of times of writing is two, the writing order is determined in step 416. When writing is performed from the group B, the reading is performed with the voltage R2 to step 418. [

Then, in response to the logic of the second read result (step 420), the logic H and the logic L are respectively read (steps 422 and 424). If it is determined in step 416 that a write has been made from group A, a read is performed with voltage R3 to step 426, and if it is the first read (step 428), a logic H is output (step 430). When the logic L is read by the first reading, the second reading is performed (step 432). When the logic H is read, it is recognized as the logic L (step 434). When the logic L is read, it is recognized as logic H (step 436).

Reading of the group B shown in Fig. 5 is also carried out in accordance with the steps 500 to 536 as in the case of Fig. In addition, as for the reading method of the group B shown in FIG. 5, the group A and the group B are the same as the reading method of the group A in FIG. 4, and a detailed description thereof will be omitted.

The method of reading the logical "00" data in "state 2" according to the embodiment of the present invention will be described with reference to FIGS. Logic "00" data can be stored by assigning a lower logic "0" for group A and a higher logic "0" for group B.

Referring to FIG. 3 and FIG. 4, when writing is performed from the group A, in step 400, reading of the group A starts. In step 402, reading is performed with voltage R1. In step 404, the memory cell array 104 for storing the number of times of writing is accessed and it is confirmed how many times it has been written. Since the logical "00" data is written in the "state 2 ", the number of times of writing is two because the second data is written.

In step 416, access is made to the memory cell array 106 for storing the write sequence in which the write sequence is written, and it is confirmed which of the group A and the group B is written first. Since the writing from the group A has been performed, the process proceeds to step 426. [ In step 426, reading is performed with voltage R3. In step 428, since the first read value that is read by the voltage R1 in step 402 is logic 0 (L), the process proceeds to step 432. In step 432, since the second read value that is read by the voltage R3 in step 426 is logic 1 (H), the process proceeds to step 434. In step 434, the read value of group A is a logic 0 (L).

Referring to Figures 3 and 5, at step 500, reading of group B begins. In step 502, reading is performed with voltage R1. In step 504, the memory cell array 104 for storing the number of times of writing is accessed and it is confirmed how many times it has been written. Since the logical "00" data is written in the "state 2 ", the number of times of writing is two because the second data is written.

In step 516, the memory cell array 106 for storing the write sequence in which the write sequence is written is accessed to determine which of the group A and the group B has been written first. Since the writing from the group A has been performed, the process proceeds to step 518. [ In step 518, reading is performed with voltage R2. In step 520, since the second read value that is read with the voltage R2 in step 518 is logical 0 (L), the process proceeds to step 524. [ In step 524, the read value of group B is a logical 0 (L).

As described above, since the group A is assigned with logic "0" and the group B is assigned with logic "0", the multi-bit data stored in the memory cells becomes logic "00".

3 to 5, a read operation will be described when logical "00" data is written from group B to "state 2".

Referring to Figures 3 and 4, in step 400, reading of group A begins. In step 402, reading is performed with voltage R1. In step 404, the memory cell array 104 for storing the number of times of writing is accessed and it is confirmed how many times it has been written. Since the logical "00" data is written in the "state 2 ", the number of times of writing is two because the second data is written.

In step 416, access is made to the memory cell array 106 for storing the write sequence in which the write sequence is written, and it is confirmed which of the group A and the group B is written first. Since the writing from the group B has been performed, the processing proceeds to step 418. [ In step 418, reading is performed with voltage R2. In step 420, since the second read value that is read by the voltage R2 in step 418 is logic 0 (L), the process proceeds to step 424. In step 424, the read value of group A is a logic 0 (L).

Referring to Figures 3 and 5, at step 500, reading of group B begins. In step 502, reading is performed with voltage R1. In step 504, the memory cell array 104 for storing the number of times of writing is accessed and it is confirmed how many times it has been written. Since the logical "00" data is written in the "state 2 ", the number of times of writing is two because the second data is written.

In step 516, the memory cell array 106 for storing the write sequence in which the write sequence is written is accessed to determine which of the group A and the group B has been written first. Since the writing from the group B has been performed, the processing proceeds to step 526. [ In step 526, reading is performed with voltage R3. In step 528, since the first read value which is read by the voltage R1 in step 502 is logical 0 (L), the process proceeds to step 532. In step 532, since the second read value that is read by the voltage R3 in step 526 is logic 1 (H), the process proceeds to step 534. In step 534, the read value of group B is a logic 0 (L).

As described above, since the group A is assigned with logic "0" and the group B is assigned with logic "0", the multi-bit data stored in the memory cells becomes logic "00".

As described in detail above, according to the present invention, by providing two groups of units capable of writing upper and lower assignments of multi-bit data at one time and providing a memory cell array for storing the order and number of writing, The writing speed can be improved regardless of the order. It is also possible to improve the write speed of the first write operation by lowering the threshold voltage of the first write operation. Moreover, it is possible to prevent the destruction of the data due to the second writing, thereby improving the reliability of the memory cell. Further, the memory cell array has a memory cell array for storing the order and the number of write operations, and the output data can be discriminated by one or two read operations by the number of write operations.

1 is a diagram showing a schematic configuration of a nonvolatile semiconductor memory device according to an embodiment of the present invention.

2 is a diagram showing shift of a threshold voltage by writing.

Fig. 3 shows a method of discriminating output data by a difference in reading group, writing order, and writing times.

Figure 4 is a flow chart illustrating the reading method in more detail.

Figure 5 is a flow chart illustrating the reading method in more detail.

6A and 6B are diagrams showing the relationship between the data of the conventional memory cell and the threshold voltage distribution of the memory cell.

Description of the Related Art [0002]

102: Multi-bit data memory cell array

104: Memory cell array for storing write-in number

106: memory cell array for writing order

120: control circuit

Claims (5)

A memory cell array for storing multi-bit data, the memory cell array including multi-level cells divided into two groups, each storing multi-bit data in the multi-level cells of each group; A memory cell array for storing a write sequence for storing a write sequence indicating which one of the two groups indicates whether the multi-bit data is first written; A memory cell array for storing a writing number of times storing the number of writing operations performed in the multi-level cells; And And a control circuit for controlling a read operation of reading data from the multi-bit data storage memory cell array and a program operation of writing data into the multi-bit data storage memory cell array, The control circuit comprising: Level cells and the corresponding data so that the movement of the threshold voltage by the first writing operation and the movement of the threshold voltage by the second writing operation become the same regardless of the writing order, A nonvolatile semiconductor memory device for controlling operations. The method according to claim 1, Wherein each group is capable of recording data of a maximum number of words or more which can be written at one time. The threshold voltages of the "state 0", "state 1", "state 2", and "state 3" set to sequentially increase the threshold voltage are different from each other and divided into two groups. A memory cell array for storing multi-bit data including multi-level cells; A memory cell array for storing a write sequence for storing a write sequence indicating which one of the two groups indicates whether the multi-bit data is first written; A memory cell array for storing a writing number of times storing the number of writing operations performed in the multi-level cells; And And a control circuit for controlling a read operation of reading data from the multi-bit data storage memory cell array and a program operation of writing data into the multi-bit data storage memory cell array, The control circuit comprising: The width of the target threshold voltage at the time of the first writing operation is set to be larger than the width of the threshold voltage of the "state 1" and the "state 2" at the time of the second writing operation, Volatile semiconductor memory device for controlling the program operation by setting the target threshold voltage to be lower than the threshold voltage of the "state 2 " so that the threshold voltage of the" state 2 " Device. The method of claim 3, The second write operation is performed in the order of "state 3", "state 2", and "state 1". The method according to claim 3 or 4, The logic "11" is assigned to the "state 0", the logic "01" is assigned to the "state 1", the logic "00" is assigned to the "state 2" and the logic "10" A nonvolatile semiconductor memory device.

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