KR20090092484A - Organic Light Emitting Display - Google Patents

Abstract

An organic electro luminescent display device is provided to prevent the drop of a common voltage supplied to an electrode using a dummy electrode in contact with the electrode. A transistor array(120) is positioned on a substrate(110). An insulating layer(130) is positioned on a transistor array. An insulating layer has a contact hole. The contact hole exposes the source or drain of the transistor array. A first electrode(140) is positioned on the insulating layer. A first electrode is connected to the source or drain of the transistor array through a contact hole. A dummy electrode(150) is positioned between the adjacent first electrodes. A bank layer(160) has a first opening and a second opening. The first opening exposes the first electrode. The second opening exposes the dummy electrode. The light emitting layer is positioned on the first electrode. The second electrode contacts with the dummy electrode.

Description

Organic Light Emitting Display

The present invention relates to an organic light emitting display device.

An organic light emitting display device used in an organic light emitting display device is a self-light emitting device in which a light emitting layer is formed between two electrodes positioned on a substrate.

In addition, the organic light emitting display device may include a top-emission method, a bottom-emission method, or a dual-emission method according to a direction in which light is emitted. According to the driving method, it is divided into a passive matrix type and an active matrix type.

The conventional organic light emitting display device may include a transistor array, a first electrode connected to a source or a drain of the transistor array, an organic light emitting layer formed on the first electrode, and a second electrode formed on the organic light emitting layer.

In the organic light emitting display device having such a structure, when a scan signal, a data signal, a power supply voltage, and the like are supplied to a plurality of sub pixels arranged in a matrix form, the selected sub pixel emits light, thereby displaying an image.

On the other hand, the conventional organic light emitting display device has a problem that a resistance difference occurs depending on the position of the panel due to the resistance characteristics of the electrode material to which the common voltage is supplied. This resistance difference drops the common voltage supplied to each sub-pixel. In this case, the display quality is degraded. Such a problem causes a lot of difficulties in realizing the large area of the panel, so it is urgent to prepare a way to solve the problem.

SUMMARY OF THE INVENTION An object of the present invention is to provide an organic light emitting display device which can improve display quality by preventing a drop of voltage supplied to an electrode and solving a problem in which a luminance difference occurs in a panel. It is.

The present invention as a problem solving means described above, the substrate; A transistor array located on the substrate; An insulating film disposed on the transistor array and having a plurality of contact holes exposing a source or a drain of the transistor array; A plurality of first electrodes on the insulating film and connected to the source or the drain of the transistor array through a plurality of contact holes; A plurality of dummy electrodes positioned between the plurality of first electrodes on the insulating film; A bank layer having a first opening exposing a plurality of first electrodes and a second opening exposing a plurality of dummy electrodes on the insulating film; A light emitting layer on the plurality of first electrodes; And a second electrode formed on the light emitting layer and in contact with the plurality of dummy electrodes.

The plurality of dummy electrodes may be positioned in a stripe form parallel to one direction on the insulating film.

The plurality of dummy electrodes may be positioned in a net shape on the insulating film.

The display device may include a display area and a non-display area defined on the substrate, and the second opening may expose the plurality of dummy electrodes on the display area, and the second electrode may contact the plurality of dummy electrodes through the second opening.

A display area and a non-display area defined on the substrate, wherein the second opening exposes the plurality of dummy electrodes on the non-display area adjacent to the display area, and the second electrode contacts the plurality of dummy electrodes through the second opening. can do.

The plurality of dummy electrodes may be the same as the material of the first electrode.

The second electrode may be formed in multiple layers.

The second electrode includes a first layer on the light emitting layer and a second layer on the first layer, and the thicknesses of the first layer and the second layer may be the same or different.

The present invention has an effect of providing an organic light emitting display device which can improve display quality by preventing a drop of voltage supplied to an electrode by using a dummy electrode in contact with the electrode and solving a problem in which a luminance difference occurs in a panel. have. In addition, the present invention has an effect suitable for large area panel implementation.

1A is a schematic plan view of an organic light emitting display device according to a first embodiment of the present invention;

FIG. 1B is a cross-sectional view of the region X-X in FIG. 1A. FIG.

1C is another sectional view of the X-X region of FIG. 1A;

2A is a schematic plan view of an organic light emitting display device according to a second embodiment of the present invention;

FIG. 2B is a cross-sectional view of the Y-Y region of FIG. 2A; FIG.

3A is a schematic plan view of an organic light emitting display device according to a third embodiment of the present invention;

3B is a cross-sectional view of the Z-Z region of FIG. 3A.

<Explanation of symbols on main parts of the drawings>

110 substrate 120 transistor array

130: insulating film 140: first electrode

150 dummy electrode 160 bank layer

161: first opening 162: second opening

Hereinafter, with reference to the accompanying drawings, the specific content for the practice of the present invention will be described.

First Embodiment

FIG. 1A is a schematic plan view of an organic light emitting display device according to a first embodiment of the present invention, FIG. 1B is a cross-sectional view of the XX region of FIG. 1A, and FIG. 1C is another cross-sectional view of the XX region of FIG. 1A. to be.

Referring to FIG. 1A, the organic light emitting display device may include a plurality of sub pixels P positioned on the substrate 110. The plurality of sub pixels P positioned on the substrate 110 may be driven by the driver 150 to represent an image.

The plurality of sub pixels P may be located in the display area AA defined on the substrate 110. The display area AA is an area where an image is displayed, and the non-display area NA is an area where an image is not displayed.

Referring to FIG. 1B, a plurality of sub pixels P positioned on the substrate 110 will be described in more detail.

The transistor array 120 may be located on the substrate 110. The transistor array 120 may include a semiconductor layer, an interlayer insulating layer, a gate, a gate insulating layer, a source, and a drain. The transistor array 120 will be described in more detail as follows.

The semiconductor layer may be located on the substrate 110. The semiconductor layer may comprise amorphous silicon or crystallized polycrystalline silicon. In addition, the semiconductor layer may include a source region and a drain region including p-type or n-type impurities, and may include channel regions other than the source region and the drain region.

An interlayer insulating layer may be positioned on the semiconductor layer. The interlayer insulating film may be a silicon oxide film (SiOx), a silicon nitride film (SiNx), or a multilayer thereof, but is not limited thereto.

A gate may be positioned on the interlayer insulating layer corresponding to the semiconductor layer. The gate is any one selected from the group consisting of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu) It may be made of an alloy of, but is not limited thereto. In addition, the gate is any one selected from the group consisting of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu). Or it may be a multilayer consisting of alloys thereof, but is not limited thereto. In addition, the gate may be a double layer of molybdenum / aluminum-neodymium or molybdenum / aluminum, but is not limited thereto.

On the other hand, the scan wiring to which the scan signal is supplied and the lower electrode of the capacitor to store the data voltage may be located on the same layer as the gate, but is not limited thereto. Scan wiring is any one selected from the group consisting of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu) or It may be made of an alloy thereof, but is not limited thereto. In addition, the scan wiring is any one selected from the group consisting of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu). It may be, but is not limited to, multiple layers of one or an alloy thereof. In addition, the scan wiring may be a double layer of molybdenum / aluminum-neodymium or molybdenum / aluminum, but is not limited thereto.

The gate insulating layer may be located on the substrate 110 including the gate. The gate insulating layer may have a via hole through which a portion of the semiconductor layer may be exposed. The gate insulating layer may be, but is not limited to, a silicon oxide layer (SiOx), a silicon nitride layer (SiNx), or a multilayer thereof. When the scan wiring and the lower electrode of the capacitor are positioned on the same layer as the gate, the gate insulating layer may be positioned on the substrate 110 including the gate, the scan wiring and the lower electrode of the capacitor.

The source and drain may be located on the gate insulating film. The source and the drain are in contact with the source region and the drain region of the semiconductor layer through via holes formed in the gate insulating film. Electrode " 121 " shown in Fig. 1B represents a source or a drain.

The source or drain 121 may be made of a single layer or multiple layers. When the source or drain 121 is a single layer, molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) It may be made of any one or alloy thereof selected from the group consisting of, but is not limited thereto. In addition, when the source or drain 121 is a multilayer, it may be composed of a double layer of molybdenum / aluminum-neodymium, molybdenum / aluminum / molybdenum, or a triple layer of molybdenum / aluminum-neodymium / molybdenum. On the other hand, the data wiring and the upper electrode and the power wiring of the capacitor may be located on the same layer as the source or drain 121, but is not limited thereto.

The insulating layer 130 may be positioned on the source or drain 121 of the transistor array 120 described above. The insulating layer 130 may have a plurality of contact holes 135 exposing the source or drain 121 of the transistor array 120. The insulating layer 130 may be a planarization layer or a protective layer to alleviate the step difference of the underlying structure. In the case where the insulating layer 130 is a planarization layer, the SOG may be coated with an organic material such as polyimide, benzocyclobutene series resin, acrylate, or silicon oxide in a liquid form and then hardened. spin on glass), but is not limited thereto. On the other hand, when the insulating film 130 is a protective film, this may be a silicon nitride film (SiNx), a silicon oxide film (SiOx) or a multilayer thereof, but is not limited thereto.

A plurality of first electrodes 140 connected to the source or drain 121 of the transistor array 120 may be disposed on the insulating layer 130 through the plurality of contact holes 135. The first electrode 140 may be an anode or a cathode, or may be a transparent electrode or a reflective electrode. The material of the first electrode 140 may be selected according to the light emitting direction. For example, when the emission direction is the rear or double-sided light emission, the first electrode 140 may be a transparent electrode, and may be any one of indium tin oxide (ITO), indium zinc oxide (IZO), or zinc oxide (ZnO). However, the present invention is not limited thereto.

A plurality of dummy electrodes 150 may be located between the plurality of first electrodes 140 positioned on the insulating layer 130. The plurality of dummy electrodes 150 may be positioned in a stripe form parallel to one direction on the insulating layer 130. The plurality of dummy electrodes 150 may be formed by selecting a material according to the material of the second electrode to be formed later. For example, when the material of the second electrode is ITO, the material of the dummy electrode 150 may be a material in which aluminum is selected and a drop occurs in a common voltage (eg, VDD voltage or GND voltage) supplied to the second electrode. Can be prevented. Here, if the first electrode 140 is formed of aluminum, since the plurality of dummy electrodes 150 may also be formed of aluminum, it may also bring an effect of providing convenience (process number reduction effect) of the process. That is, the dummy electrode 150 may be formed at the same time as the first electrode 140.

Therefore, the plurality of dummy electrodes 150 may be formed of a material having a high work function or a low work function depending on the material of the second electrode to be formed later. In addition, the plurality of dummy electrodes 150 may have a relatively lower resistivity than the material of the second electrode to be formed later. As a result, the common voltage supplied to the second electrode may exhibit a compensation effect by the plurality of dummy electrodes 150.

The bank layer 160 may be positioned on the insulating layer 130. The bank layer 160 may have a first opening 161 exposing the plurality of first electrodes 140 and a second opening 162 exposing the plurality of dummy electrodes 150. The first opening 161 and the second opening 162 may be positioned on the display area AA. However, although only one second opening portion 162 is illustrated for convenience, two or more openings 162 may be selectively formed as needed, if it can be formed in the display area AA.

The light emitting layers 170, 171, and 172 may be positioned on the plurality of first electrodes 140 exposed through the first openings 161 formed in the bank layer 160. The emission layers 170, 171, and 172 are disposed on the lower common layer 170 and the organic emission layer 171 and the organic emission layer 171 positioned on the lower common layer 170 on the plurality of first electrodes 140. It may include an upper common layer 172 located in.

On the bank layer 160 including the light emitting layers 170, 171, and 172, the second electrode 180 may contact the plurality of dummy electrodes 150 through the second opening 162. Here, since the second opening 162 is located in the display area AA, the plurality of dummy electrodes 150 and the second electrode 180 contact each other in the display area AA. The second electrode 180 may be a cathode or an anode. For example, when the second electrode 180 is a cathode, the second electrode 180 may be formed of magnesium (Mg), calcium (Ca), aluminum (Al), silver (Ag), or an alloy thereof having a low work function, but is not limited thereto.

Meanwhile, referring to FIG. 1A, it can be seen that the bank layer 160 is positioned in the non-display area NA. However, this may include not only the bank layer 160 but also an insulating material formed in each layer, for example, an interlayer insulating film, a gate insulating film, or the like, during the process of forming the transistor array 120 and the process of forming the light emitting layers 170, 171, and 172. May contain one or more. However, in the first embodiment of the present invention, only the bank layer 160 is positioned in the non-display area NA as an example.

Here, referring to FIG. 1C, the second electrode 180 may be formed of a multilayer, unlike FIG. 1B. For example, assuming that the second electrode 180 is formed in a two-layer structure, the first layer 181 may be positioned on the light emitting layers 170, 171, and 172, and the second layer 182 may be the first layer. May be located on layer 181. In such a structure, the thicknesses of the first layer 181 and the second layer 182 may be the same or different.

Second Embodiment

FIG. 2A is a schematic plan view of an organic light emitting display device according to a second embodiment of the present invention, and FIG. 2B is a cross-sectional view of the Y-Y region of FIG. 2A.

Referring to FIG. 2A, the organic light emitting display device may include a plurality of sub pixels P positioned on the substrate 210. The plurality of sub pixels P positioned on the substrate 210 may be driven by the driver 250 to represent an image.

The plurality of sub pixels P may be located in the display area AA defined on the substrate 210. The display area AA is an area where an image is displayed, and the non-display area NA is an area where an image is not displayed.

Referring to FIG. 2B, the plurality of sub pixels P positioned on the substrate 210 will be described in more detail.

The transistor array 220 may be located on the substrate 210. The transistor array 220 may include a semiconductor layer, an interlayer insulating layer, a gate, a gate insulating layer, a source, and a drain. The transistor array 220 will be described in more detail as follows.

The semiconductor layer may be located on the substrate 210. The semiconductor layer may comprise amorphous silicon or crystallized polycrystalline silicon. In addition, the semiconductor layer may include a source region and a drain region including p-type or n-type impurities, and may include channel regions other than the source region and the drain region.

An interlayer insulating layer may be positioned on the semiconductor layer. The interlayer insulating film may be a silicon oxide film (SiOx), a silicon nitride film (SiNx), or a multilayer thereof, but is not limited thereto.

A gate may be positioned on the interlayer insulating layer corresponding to the semiconductor layer. The gate is any one selected from the group consisting of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu) It may be made of an alloy of, but is not limited thereto. In addition, the gate is any one selected from the group consisting of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu). Or it may be a multilayer consisting of alloys thereof, but is not limited thereto. In addition, the gate may be a double layer of molybdenum / aluminum-neodymium or molybdenum / aluminum, but is not limited thereto.

On the other hand, the scan wiring to which the scan signal is supplied and the lower electrode of the capacitor to store the data voltage may be located on the same layer as the gate, but is not limited thereto. Scan wiring is any one selected from the group consisting of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu) or It may be made of an alloy thereof, but is not limited thereto. In addition, the scan wiring is any one selected from the group consisting of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu). It may be, but is not limited to, multiple layers of one or an alloy thereof. In addition, the scan wiring may be a double layer of molybdenum / aluminum-neodymium or molybdenum / aluminum, but is not limited thereto.

The gate insulating layer may be located on the substrate 210 including the gate. The gate insulating layer may have a via hole through which a portion of the semiconductor layer may be exposed. The gate insulating layer may be, but is not limited to, a silicon oxide layer (SiOx), a silicon nitride layer (SiNx), or a multilayer thereof. When the scan wiring and the lower electrode of the capacitor are positioned on the same layer as the gate, the gate insulating layer may be positioned on the substrate 210 including the gate, the scan wiring and the lower electrode of the capacitor.

The source and drain may be located on the gate insulating film. The source and the drain are in contact with the source region and the drain region of the semiconductor layer through via holes formed in the gate insulating film. Electrode " 221 " shown in Fig. 2B represents a source or a drain.

The source or drain 221 may be made of a single layer or multiple layers. When the source and drain 221 are a single layer, molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) It may be made of any one or alloy thereof selected from the group consisting of, but is not limited thereto. In addition, when the source or drain 221 is a multilayer, it may be composed of a double layer of molybdenum / aluminum-neodymium, molybdenum / aluminum / molybdenum or a triple layer of molybdenum / aluminum-neodymium / molybdenum. On the other hand, on the same layer as the source or drain 221, the data line to which the data signal is supplied, the upper electrode of the capacitor, and the power line may be located, but are not limited thereto.

The insulating layer 230 may be positioned on the source or drain 221 of the transistor array 220 described above. The insulating layer 230 may have a plurality of contact holes 235 exposing the source or drain 221 of the transistor array 220. The insulating layer 230 may be a planarization layer or a protective layer to alleviate the step difference of the underlying structure. When the insulating film 230 is a planarization film, SOG (coated with polyimide, benzocyclobutene series resin, acrylate, etc.) is coated with SOG (organic material or silicon oxide) in a liquid form and then cured. spin on glass), but is not limited thereto. On the other hand, when the insulating film 230 is a protective film, this may be a silicon nitride film (SiNx), a silicon oxide film (SiOx) or a multilayer thereof, but is not limited thereto.

A plurality of first electrodes 240 connected to the source or drain 221 of the transistor array 220 may be disposed on the insulating layer 230 through a plurality of contact holes 235. The first electrode 240 may be an anode or a cathode, or may be a transparent electrode or a reflective electrode. The material of the first electrode 240 may be selected according to the light emitting direction. For example, when the emission direction is the rear or double-sided light emission, the first electrode 240 may be a transparent electrode, and may be any one of indium tin oxide (ITO), indium zinc oxide (IZO), or zinc oxide (ZnO). However, the present invention is not limited thereto.

A plurality of dummy electrodes 250 may be positioned between the plurality of first electrodes 240 positioned on the insulating layer 230. The plurality of dummy electrodes 250 may be positioned in a net shape on the insulating film 230. The plurality of dummy electrodes 250 may be formed by selecting a material according to the material of the second electrode to be formed later. For example, when the material of the second electrode is ITO, the material of the dummy electrode 250 may be a material in which aluminum is selected and a drop occurs in a common voltage (eg, VDD voltage or GND voltage) supplied to the second electrode. Can be prevented. Here, if the first electrode 240 is formed of aluminum, since the plurality of dummy electrodes 250 may also be formed of aluminum, it may also bring about an effect of providing convenience of a process (reducing the number of masks used). That is, the dummy electrode 250 may be formed at the same time as the first electrode 240.

Therefore, the plurality of dummy electrodes 250 may be formed of a material having a high work function or a low work function depending on the material of the second electrode to be formed later. In addition, the plurality of dummy electrodes 250 may have a relatively lower resistivity than the material of the second electrode to be formed later. As a result, the common voltage supplied to the second electrode may exhibit a compensation effect by the plurality of dummy electrodes 250.

The bank layer 260 may be positioned on the insulating layer 230. The bank layer 260 may have a first opening 261 exposing a plurality of first electrodes 240 and a second opening 262 exposing a plurality of dummy electrodes 250. Here, the first opening 261 and the second opening 262 may be located in the display area AA. However, although only one second opening portion 262 is illustrated for convenience, two or more openings 262 may be selectively formed as needed, if it can be formed in the display area AA.

The emission layers 270, 271, and 272 may be positioned on the plurality of first electrodes 240 exposed through the first openings 261 formed in the bank layer 260. The emission layers 270, 271, and 272 are disposed on the lower common layer 270 and the organic emission layer 271 and the organic emission layer 271 disposed on the lower common layer 270. It may include an upper common layer 272 located in.

On the bank layer 260 including the light emitting layers 270, 271, and 272, a second electrode 280 may contact the plurality of dummy electrodes 250 through the second opening 262. Here, since the second opening 262 is positioned in the display area AA, the plurality of dummy electrodes 250 and the second electrode 280 are in contact with the display area AA. The second electrode 280 may be a cathode or an anode. For example, when the second electrode 280 is a cathode, the second electrode 280 may be made of magnesium (Mg), calcium (Ca), aluminum (Al), silver (Ag), or an alloy thereof having a low work function, but is not limited thereto. Here, the second electrode 280 may be formed in multiple layers as in the first embodiment.

Meanwhile, referring to FIG. 2A, it can be seen that the bank layer 260 is positioned in the non-display area NA. However, the insulating material formed in each layer during the process of forming not only the bank layer 260 but also the transistor array 220 through the process of forming the light emitting layers 270, 271, and 272, for example, an interlayer insulating film, a gate insulating film, and the like, may be used. May contain one or more. However, in the second embodiment of the present invention, only the bank layer 260 is positioned in the non-display area NA as an example.

Third Embodiment

3A is a schematic plan view of an organic light emitting display device according to a third embodiment of the present invention, and FIG. 3B is a cross-sectional view of the Z-Z region of FIG. 3A.

Referring to FIG. 3A, the organic light emitting display device may include a plurality of sub pixels P positioned on the substrate 310. The plurality of sub pixels P positioned on the substrate 310 may be driven by the driver 350 to represent an image.

The plurality of sub pixels P may be located in the display area AA defined on the substrate 310. The display area AA is an area where an image is displayed, and the non-display area NA is an area where an image is not displayed.

Referring to FIG. 3B, a plurality of sub pixels P positioned on the substrate 310 will be described in more detail.

The transistor array 320 may be located on the substrate 310. The transistor array 320 may include a semiconductor layer, an interlayer insulating layer, a gate, a gate insulating layer, a source, and a drain. The transistor array 320 will be described in more detail as follows.

The semiconductor layer may be located on the substrate 310. The semiconductor layer may comprise amorphous silicon or crystallized polycrystalline silicon. In addition, the semiconductor layer may include a source region and a drain region including p-type or n-type impurities, and may include channel regions other than the source region and the drain region.

An interlayer insulating layer may be positioned on the semiconductor layer. The interlayer insulating film may be a silicon oxide film (SiOx), a silicon nitride film (SiNx), or a multilayer thereof, but is not limited thereto.

A gate may be positioned on the interlayer insulating layer corresponding to the semiconductor layer. The gate is any one selected from the group consisting of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu) It may be made of an alloy of, but is not limited thereto. In addition, the gate is any one selected from the group consisting of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu). Or it may be a multilayer consisting of alloys thereof, but is not limited thereto. In addition, the gate may be a double layer of molybdenum / aluminum-neodymium or molybdenum / aluminum, but is not limited thereto.

On the other hand, the scan wiring to which the scan signal is supplied and the lower electrode of the capacitor to store the data voltage may be located on the same layer as the gate, but is not limited thereto. Scan wiring is any one selected from the group consisting of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu) or It may be made of an alloy thereof, but is not limited thereto. In addition, the scan wiring is any one selected from the group consisting of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu). It may be, but is not limited to, multiple layers of one or an alloy thereof. In addition, the scan wiring may be a double layer of molybdenum / aluminum-neodymium or molybdenum / aluminum, but is not limited thereto.

The gate insulating layer may be located on the substrate 310 including the gate. The gate insulating layer may have a via hole through which a portion of the semiconductor layer may be exposed. The gate insulating layer may be, but is not limited to, a silicon oxide layer (SiOx), a silicon nitride layer (SiNx), or a multilayer thereof. When the scan wiring and the lower electrode of the capacitor are positioned on the same layer as the gate, the gate insulating layer may be positioned on the substrate 310 including the gate, the scan wiring and the lower electrode of the capacitor.

The source and drain may be located on the gate insulating film. The source and the drain are in contact with the source region and the drain region of the semiconductor layer through via holes formed in the gate insulating film. Electrode “321” shown in FIG. 3B represents a source or a drain.

The source or drain 321 may be made of a single layer or multiple layers. When the source or drain 321 is a single layer, molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) It may be made of any one or alloy thereof selected from the group consisting of, but is not limited thereto. In addition, when the source or drain 321 is a multilayer, it may be composed of a double layer of molybdenum / aluminum-neodymium, molybdenum / aluminum / molybdenum or a triple layer of molybdenum / aluminum-neodymium / molybdenum. On the other hand, the data line to which the data signal is supplied, the upper electrode of the capacitor, and the power line may be located on the same layer as the source or drain 321, but is not limited thereto.

The insulating layer 330 may be positioned on the source or drain 321 of the transistor array 320 described above. The insulating layer 330 may have a plurality of contact holes 335 exposing the source or drain 321 of the transistor array 320. The insulating layer 330 may be a planarization layer or a protective layer to alleviate the step difference of the underlying structure. When the insulating layer 330 is a planarization layer, SOG (coated with polyimide, benzocyclobutene series resin, acrylate, etc.) in which an organic material or silicon oxide is coated in a liquid form and then cured spin on glass), but is not limited thereto. On the other hand, when the insulating film 330 is a protective film, this may be a silicon nitride film (SiNx), a silicon oxide film (SiOx) or a multilayer thereof, but is not limited thereto.

A plurality of first electrodes 340 connected to the source or drain 321 of the transistor array 320 may be disposed on the insulating layer 330 through a plurality of contact holes 335. The first electrode 340 may be an anode or a cathode, or may be a transparent electrode or a reflective electrode. The material of the first electrode 340 may be selected according to the light emitting direction. For example, when the emission direction is the rear or double-sided light emission, the first electrode 340 may be a transparent electrode, and may be any one of indium tin oxide (ITO), indium zinc oxide (IZO), or zinc oxide (ZnO). However, the present invention is not limited thereto.

A plurality of dummy electrodes 350 may be located between the plurality of first electrodes 340 on the insulating layer 330. The plurality of dummy electrodes 350 may be positioned on the insulating film 330 in the form of stripes or a net in parallel with one direction. The plurality of dummy electrodes 350 may be formed by selecting a material according to the material of the second electrode to be formed later. For example, when the material of the second electrode is ITO, the material of the dummy electrode 350 may be a material in which aluminum is selected and a drop occurs in a common voltage (eg, VDD voltage or GND voltage) supplied to the second electrode. Can be prevented. Here, if the first electrode 340 is formed of aluminum, since the plurality of dummy electrodes 350 may also be formed of aluminum, it may also bring an effect of providing convenience (process number reduction effect) of the process. That is, the dummy electrode 350 may be formed at the same time as the first electrode 340.

Therefore, the plurality of dummy electrodes 350 may be formed of a material having a high work function or a low work function according to the material of the second electrode to be formed later. In addition, the plurality of dummy electrodes 350 may have a relatively low resistivity than the material of the second electrode to be formed later. As a result, the common voltage supplied to the second electrode may exhibit a compensation effect by the plurality of dummy electrodes 350.

The bank layer 360 may be positioned on the insulating layer 330. The bank layer 360 may have a first opening 361 exposing the plurality of first electrodes 340 and a second opening 362 exposing the plurality of dummy electrodes 350. The first opening 361 may be positioned on the display area AA, and the second opening 362 may be positioned on the non-display area NA adjacent to the display area AA.

The emission layers 370, 371, and 372 may be positioned on the plurality of first electrodes 340 exposed through the first opening 361 formed in the bank layer 360. The emission layers 370, 371, and 372 are disposed on the lower common layer 370 disposed on the plurality of first electrodes 340, and the organic emission layer 371 and the organic emission layer 371 disposed on the lower common layer 370. It may include an upper common layer 372 located in.

On the bank layer 360 including the emission layers 370, 371, and 372, a second electrode 380 may be positioned to contact the plurality of dummy electrodes 350 through the second opening 362. Here, since the second opening 362 is positioned on the non-display area NA, the plurality of dummy electrodes 350 and the second electrode 380 are in contact with the non-display area NA. The second electrode 380 may be a cathode or an anode. For example, when the second electrode 380 is a cathode, the second electrode 380 may be formed of magnesium (Mg), calcium (Ca), aluminum (Al), silver (Ag), or an alloy thereof having a low work function, but is not limited thereto. Here, the second electrode 380 may be formed in multiple layers as in the first embodiment.

Meanwhile, referring to FIG. 3A, it can be seen that the bank layer 360 is positioned in the non-display area NA. However, this may include insulating materials, such as an interlayer insulating film and a gate insulating film, formed in each layer during the process of forming not only the bank layer 360 but also the transistor array 320 and the process of forming the light emitting layers 370, 371, and 372. May contain one or more. However, in the third embodiment of the present invention, only the bank layer 360 is positioned in the non-display area NA as an example.

Each embodiment of the present invention is an organic light emitting display device which can improve display quality by preventing a drop of a common voltage supplied to an electrode by using a dummy electrode in contact with an electrode, and solving a problem in which a luminance difference occurs in a panel. Has the effect of providing. In addition, there is an effect to provide a large area organic light emitting display device having a uniform display quality.

Although the embodiments of the present invention have been described above with reference to the accompanying drawings, the technical configuration of the present invention described above may be modified in other specific forms by those skilled in the art to which the present invention pertains without changing its technical spirit or essential features. It will be appreciated that it may be practiced. Therefore, the embodiments described above are to be understood as illustrative and not restrictive in all aspects. In addition, the scope of the present invention is shown by the claims below, rather than the above detailed description. Also, it is to be construed that all changes or modifications derived from the meaning and scope of the claims and their equivalent concepts are included in the scope of the present invention.

Claims (8)

Board; A transistor array positioned on the substrate; An insulating layer disposed on the transistor array and having a plurality of contact holes exposing a source or a drain of the transistor array; A plurality of first electrodes on the insulating layer and connected to the source or the drain of the transistor array through the plurality of contact holes; A plurality of dummy electrodes positioned between the plurality of first electrodes on the insulating layer; A bank layer having a first opening exposing the plurality of first electrodes and a second opening exposing the plurality of dummy electrodes on the insulating film; A light emitting layer on the plurality of first electrodes; And And a second electrode formed on the emission layer and in contact with the plurality of dummy electrodes. The method of claim 1, The plurality of dummy electrodes, The organic light emitting display device of claim 1, wherein the organic light emitting display device is positioned in a stripe form on the insulating layer. The method of claim 1, The plurality of dummy electrodes, The organic light emitting display device of claim 1, wherein the organic light emitting display device is positioned in a net shape on the insulating layer. The method of claim 1, The substrate includes a display area and a non-display area, And the second opening exposes the plurality of dummy electrodes on the display area, and the second electrode contacts the plurality of dummy electrodes through the second opening. The method of claim 1, The substrate includes a display area and a non-display area, And the second opening exposes the plurality of dummy electrodes on the non-display area adjacent to the display area, and the second electrode contacts the plurality of dummy electrodes through the second opening. Display. The method of claim 1, The plurality of dummy electrodes, And an organic light emitting display device, the same as the material of the first electrode. The method of claim 1, The second electrode, An organic light emitting display device comprising a multilayer. The method of claim 7, wherein The second electrode, A first layer on the light emitting layer and a second layer on the first layer, And the thickness of the first layer and the second layer is the same or different.