KR20090091956A - Method of forming patterns in semiconductor device - Google Patents

Method of forming patterns in semiconductor device

Info

Publication number
KR20090091956A
KR20090091956A KR1020080017200A KR20080017200A KR20090091956A KR 20090091956 A KR20090091956 A KR 20090091956A KR 1020080017200 A KR1020080017200 A KR 1020080017200A KR 20080017200 A KR20080017200 A KR 20080017200A KR 20090091956 A KR20090091956 A KR 20090091956A
Authority
KR
South Korea
Prior art keywords
pattern
phase separation
semiconductor device
hard mask
phase
Prior art date
Application number
KR1020080017200A
Other languages
Korean (ko)
Inventor
권혜진
Original Assignee
주식회사 하이닉스반도체
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR1020080017200A priority Critical patent/KR20090091956A/en
Publication of KR20090091956A publication Critical patent/KR20090091956A/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0332—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their composition, e.g. multilayer masks, materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks

Abstract

A pattern formation method of semiconductor device is provided to omit the exposure and the development processes using the phase separation membrane instead of the photoresist film. A hard mask film(108) is formed on a semiconductor substrate(100). A phase separation membrane is formed on the top of the hard mask film. The thermal process is performed in order to separate the phase from the phase separation membrane to the different pattern. Some patterns in which the etching selectivity is identical are removed, and the other patterns are remained. The hard mask film is patterned by the remained pattern. The phase separation membrane uses the polymer capable of being separated.

Description

Method of forming patterns in semiconductor device

The present invention relates to a method of forming a pattern of a semiconductor device, and more particularly, to a pattern forming method of a semiconductor device capable of forming a hard mask pattern using a phase separation film capable of separating phases.

The manufacturing process of the semiconductor device may be formed by a deposition process and an etching process. The forming process refers to a process of depositing or filling a material, and is performed by physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD). can do. The etching process refers to a process of removing part or all of the formed material (or film) or forming a trench, and may be performed by a dry etching process or a wet etching process.

In particular, a patterning process for forming a gate pattern or a metal layer in the etching process may be a process directly related to the integration of semiconductor devices.

In general, in the patterning process, after forming a photoresist pattern on the hard mask layer, an etching process is performed according to the photoresist pattern to form a hard mask pattern. However, as the degree of integration of semiconductor devices increases, an exposure process for forming a photoresist pattern becomes increasingly difficult. Specifically, as the degree of integration increases, interference of the light source may occur during the exposure process, so a light source having a high resolution should be used. However, in order to use a high resolution light source for the exposure process, expensive equipment needs to be replaced, thereby increasing manufacturing costs. In addition, since there is a limit to increasing the resolution of the light source, it is not easy to increase the integration degree of the semiconductor device.

The problem to be solved by the present invention, it is possible to omit the exposure and development process using a material capable of phase separation in place of the photoresist film. To this end, a diblock copolymer may be used as a material capable of phase separation, and one of the materials separated from the phase separation may be removed, and another remaining material may be used as a hard mask pattern.

In the method of forming a pattern of a semiconductor device according to an embodiment of the present disclosure, a semiconductor substrate on which a hard mask film is formed is provided. A phase separation film is formed on the hard mask film. In order to separate the phase separation membrane into patterns having different phases, a heat treatment process is performed. Of the patterns having different phases, some patterns having the same etching selectivity are removed and the remaining patterns are left. The patterning method of the semiconductor device includes the step of patterning the hard mask film according to the remaining pattern remaining.

The phase separation membrane uses a polymer capable of phase separation, and the polymer capable of phase separation is formed of a diblock copolymer.

The diblock polymer compound is formed of a mixture of polystyrene (hereinafter, PS) and polymethyl methacrylate (PMMA) (PS-b-PMMA).

The patterns with different phases are separated by polystyrene (PS) and polymethylmethacrylate (PMMA).

The heat treatment step is performed by applying a temperature of 100 ℃ to 200 ℃, the hard mask film is formed by laminating an amorphous carbon film (amorphous carbon) and an oxide film.

Removing the some patterns having the same etching selectivity and leaving the remaining patterns is performed by a wet etching process.

The wet etching process is performed using heptane, and the wet etching process is performed using an etchant including C 7 H 18 as heptane.

In the method of forming a pattern of a semiconductor device according to another embodiment of the present disclosure, a semiconductor substrate on which an etching target layer is formed is provided. A hard mask layer is formed on the etching target layer. A phase separation film is formed on the hard mask film. The phase separation membrane is phase separated into a first phase separation pattern and a second phase separation pattern. The second phase separation pattern is removed. The hard mask layer is patterned according to the first phase separation pattern to form a hard mask pattern. The pattern forming method of the semiconductor device comprising the step of etching the etching target film according to the hard mask pattern.

The phase separation membrane is formed of a diblock copolymer, and the diblock polymer compound is a mixture of polystyrene (PS) and poly methyl methacrylate (PMMA) (PS-b-). PMMA).

The molecular weight ratio of polymethyl methacrylate (PMMA) and polystyrene (PS) is adjusted to 1: 0.4 to 0.6, and the first phase separation pattern 112a and the second phase separation pattern 112b have the same width (1). It is formed by the line pattern of (1).

When the first phase separation pattern is phase separated with polystyrene (PS), the second phase separation pattern is phase separated with polymethylmethacrylate (PMMA), and the first phase separation pattern is polymethyl methacrylate (PMMA). When phase separated, the second phase separation pattern is phase separated with polystyrene (PS). At this time, the step of removing the second phase separation pattern is performed by a wet etching process using heptane (heptane).

The wet etching process is performed using an etchant containing C 7 H 18 as heptane.

Phase separation is carried out by a heat treatment process, the heat treatment process is carried out by applying a temperature of 100 ℃ to 200 ℃.

The present invention uses a phase separation film capable of phase separation instead of the photoresist film, so that the exposure and development processes can be omitted. In addition, since the width to be separated by adjusting the mixing ratio of the phase separation membrane may be adjusted, the hard mask pattern may be easily formed. Accordingly, a narrow width pattern can be formed without replacing the exposure equipment, and the manufacturing cost and time of the semiconductor device can be reduced.

1A to 1F are cross-sectional views illustrating a method of forming a pattern of a semiconductor device in accordance with an embodiment of the present invention.

<Description of the symbols for the main parts of the drawings>

100 semiconductor substrate 102 first interlayer insulating film

104: etch stop film 106: second interlayer insulating film

108: first hard mask film 110: second hard mask film

112: phase separation membrane 112a: first phase separation pattern

112b: second phase separation pattern

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, the present invention is not limited to the embodiments disclosed below, but can be implemented in various forms, and only the present embodiments are intended to complete the disclosure of the present invention and to those skilled in the art. It is provided for complete information.

1A to 1F are cross-sectional views illustrating a method of forming a pattern of a semiconductor device in accordance with an embodiment of the present invention.

Referring to FIG. 1A, a manufacturing method of forming a pattern for a metal layer in a method of manufacturing a semiconductor device will be described below.

The first interlayer insulating layer 102 is formed on the semiconductor substrate 100 on which the substructure (eg, the gate pattern, the lower metal wiring, or the contact plug) is formed so as to cover the substructure. The first interlayer insulating film 102 may be formed of an oxide film. An etch stop layer 104 is formed on the first interlayer insulating layer 102, and the second interlayer insulating layer is an etch target layer for electrically insulating between metal wires to be subsequently formed on the etch stop layer 104. Form 106. The etch stop layer 104 and the second interlayer insulating layer 106 may be formed of layers having different etch selectivity. For example, the etch stop layer 104 may be formed of a nitride layer. The interlayer insulating film 106 can be formed of an oxide film. In this case, the etch stop layer 104 and the second interlayer insulating layer 106 may have different thicknesses according to the degree of integration. For example, the etch stop layer 104 may be formed to have a thickness of 230 kPa to 260 kPa. The two interlayer insulating film 106 can be formed to a thickness of 1000 kPa to 1200 kPa.

Referring to FIG. 1B, the first hard mask layer 108, the second hard mask layer 110, and the phase separation layer 112 are sequentially formed on the second interlayer insulating layer 106. The first hard mask film 108 may be formed of an amorphous carbon film, and may be formed to have a thickness of 1400 mm to 1600 mm. The second hard mask film 110 may be formed of an oxide film in order to easily perform a wet etching process of the phase separation film 112 to be subsequently performed. The phase separation membrane 112 may be formed of a polymer capable of phase separation. Hereinafter, the phase separation membrane 112 will be described in detail.

The polymer for the phase separation membrane 112 is preferably formed of a diblock copolymer. The diblock polymer compound may be formed of a mixture of polystyrene (hereinafter, referred to as PS) and polymethyl methacrylate (hereinafter referred to as PMMA) (PS-b-PMMA).

Referring to FIG. 1C, a heat treatment process is performed on the semiconductor substrate 100 on which the phase separation film 112 of FIG. 1B is formed in order to phase separate the phase separation film 112 of FIG. 1B. The heat treatment step is preferably performed by applying a temperature of 100 ° C to 200 ° C.

In particular, the phase separation membrane 112 is subjected to a heat treatment process to generate a repulsion force between the polystyrene (PS) and polymethyl methacrylate (PMMA), the thermodynamic equilibrium between the two materials (PS and PMMA) to reach the equilibrium state Will occur. Due to this property, the phase separation layer 112 may be separated into phases by the first phase separation pattern 112a and the second phase separation pattern 112b. For example, the first phase separation pattern 112a may be phase-separated with polymethylmethacrylate (PMMA) and the second phase separation pattern 112b may be polystyrene (PS).

As such, due to phase separation of polymethylmethacrylate (PMMA) and polystyrene (PS), the first phase separation pattern 112a and the second phase separation pattern 112b may have a specific structure having a nano size. Can be formed. That is, various structures may be formed according to the composition ratio of the polymethyl methacrylate (PMMA) and the polystyrene (PS), the molecular weight, or the temperature of the heat treatment process. For example, a case in which the first phase separation pattern 112a and the second phase separation pattern 112b are formed in a line form will be described below. It is formed by adjusting the molecular weight ratio of polymethyl methacrylate (PMMA) and polystyrene (PS) included in the phase separation membrane 112 to 1: 0.4 to 0.6. When the heat treatment process is performed, the first phase separation pattern 112a and the second phase separation pattern 112b may be formed in a line pattern having the same width (1: 1).

Referring to FIG. 1D, a residual pattern is formed by removing the first phase separation pattern 112a or the second phase separation pattern 112b of FIG. 1C. Specifically, an etching process having a large etching selectivity with respect to any one of the first phase separation pattern 112a and the second phase separation pattern 112b is performed. For example, when the second phase separation pattern 112b is removed to leave the first phase separation pattern 112a, since the second phase separation pattern 112b is polystyrene (PS), the etching selectivity with respect to the polystyrene (PS) as an etching solution is increased. Preference is given to using large heptanes. At this time, heptane (heptane) can be used as an etchant containing C 7 H 18 .

As such, the first phase separation pattern 112a of the phase separation layer 112 of FIG. 1B may be left without using the photoresist pattern to be used as a hard mask pattern. For example, in order to form a highly integrated semiconductor device having a class of 40 nm or less, an exposure apparatus having a resolution NA of a light source higher than 1.35 is required. However, since the exposure process can be omitted, manufacturing cost and time can be reduced, and high integration can be easily performed.

Referring to FIG. 1E, the second hard mask layer 110 (in FIG. 1D) and the first hard mask layer 108 (in FIG. 1D) may be patterned according to the first phase separation pattern 112a of FIG. 1D. 110a and the first hard mask pattern 108a are formed. In this case, since the etching process for forming the second hard mask pattern 110a is formed of an oxide film that may remain during the wet etching process of the second phase separation pattern 112b of FIG. 1C, the etching process may be performed by a dry etching process. Do.

After the patterning process is performed such that the second interlayer insulating layer 106 is exposed, all of the first phase separation patterns 112a may be removed or partially remain. In the drawings, all of them are removed.

Referring to FIG. 1F, the second interlayer insulating layer 106 (in FIG. 1E) and the etch stop layer (104 in FIG. 1E) may be patterned according to the second hard mask pattern (FIG. 1E) and the first hard mask pattern 108a. The two interlayer insulating pattern 106a and the etch stop pattern 104a are formed.

In a subsequent process, a metal film may be formed between the second interlayer insulating patterns 106a to form a metal wiring.

As such, since the phase separation film (112 of FIG. 1B) is used instead of the photoresist film, the exposure and development processes can be omitted, and the hard mask pattern can be easily formed according to the remaining first phase separation pattern (112a of FIG. 1D). can do. The hard mask pattern thus formed may be used to form a metal wiring pattern or a gate line pattern.

Although the technical spirit of the present invention described above has been described in detail in a preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, the present invention will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

Claims (21)

Providing a semiconductor substrate having a hard mask film formed thereon; Forming a phase separation layer on the hard mask layer; Performing a heat treatment process to separate the phase separation membrane into patterns having different phases; Removing some patterns having the same etching selectivity among the patterns having different phases and leaving the remaining patterns; And Patterning the hard mask layer according to the remaining pattern. The method of claim 1, The phase separation membrane is a pattern forming method of a semiconductor device using a polymer capable of phase separation (phase). The method of claim 2, The method of forming a pattern of a semiconductor device, wherein the phase-separable polymer is formed of a diblock copolymer. The method of claim 3, wherein The diblock polymer compound is a pattern forming method of a semiconductor device formed of a mixture of polystyrene (PS) and poly methyl methacrylate (PMMA) (PS-b-PMMA). The method of claim 4, wherein The pattern formation method of the semiconductor device which separates the pattern from which a phase differs with the said polystyrene (PS) and polymethyl methacrylate (PMMA). The method of claim 1, The heat treatment step is a pattern forming method of a semiconductor device performed by applying a temperature of 100 ℃ to 200 ℃. The method of claim 1, The hard mask layer may be formed by laminating an amorphous carbon layer and an oxide layer. The method of claim 1, Removing the partial patterns having the same etching selectivity and leaving the remaining patterns by a wet etching process. The method of claim 8, The wet etching process is a pattern formation method of a semiconductor device performed using heptane (heptane). The method of claim 9, The wet etching process is a pattern forming method of a semiconductor device using an etching solution containing C 7 H 18 as the heptane (heptane). Providing a semiconductor substrate on which an etch target layer is formed; Forming a hard mask layer on the etching target layer; Forming a phase separation layer on the hard mask layer; Phase separating the phase separation membrane into a first phase separation pattern and a second phase separation pattern; Removing the second phase separation pattern; Patterning the hard mask layer according to the first phase separation pattern to form a hard mask pattern; And And etching the etching target layer according to the hard mask pattern. The method of claim 11, The phase separation membrane is a pattern forming method of a semiconductor device formed of a diblock copolymer. The method of claim 12, The diblock polymer compound is a pattern forming method of a semiconductor device formed of a mixture of polystyrene (PS) and poly methyl methacrylate (PMMA) (PS-b-PMMA). The method of claim 13, The molecular weight ratio of the polymethyl methacrylate (PMMA) and polystyrene (PS) is controlled to 1: 0.4 to 0.6 pattern forming method of a semiconductor device. The method of claim 14, And forming the first phase separation pattern (112a) and the second phase separation pattern (112b) in a line pattern having a same width (1: 1). The method of claim 13, When the first phase separation pattern is phase-separated with the polystyrene (PS), the second phase separation pattern is phase-separated with the polymethyl methacrylate (PMMA). The method of claim 13, And when the first phase separation pattern is phase separated with the polymethylmethacrylate (PMMA), the second phase separation pattern is phase separated with the polystyrene (PS). The method of claim 17, The removing of the second phase separation pattern may be performed by a wet etching process using heptane. The method of claim 18, The wet etching process is a pattern forming method of a semiconductor device using an etching solution containing C 7 H 18 as the heptane (heptane). The method of claim 11, The phase separation may be performed by a heat treatment process. The method of claim 20, The heat treatment step is a pattern forming method of a semiconductor device performed by applying a temperature of 100 ℃ to 200 ℃.
KR1020080017200A 2008-02-26 2008-02-26 Method of forming patterns in semiconductor device KR20090091956A (en)

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KR1020080017200A KR20090091956A (en) 2008-02-26 2008-02-26 Method of forming patterns in semiconductor device

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20150122658A (en) * 2013-02-27 2015-11-02 린텍 가부시키가이샤 Thermoelectric conversion material, method for producing same, and thermoelectric conversion module

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20150122658A (en) * 2013-02-27 2015-11-02 린텍 가부시키가이샤 Thermoelectric conversion material, method for producing same, and thermoelectric conversion module

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