KR20090088669A - Operational transconductance amplifier circuit of being bulk-driven - Google Patents

Abstract

A bulk-driven operational transconductance amplifier circuit is provided to secure a wide input swing range without a burden of a threshold voltage by securing high input impedance through an input terminal which performs a bulk drive. A bulk-driven operational transconductance amplifier circuit includes a bulk driving part(100), an active load part(120), and a self-cascode output part(140). The bulk driving part applies an input signal to a body of input transistors, and increases a voltage regardless of a threshold voltage. The active load part performs a positive feedback operation in order to accelerate increase or decrease of an output signal of the bulk driving part. The self-cascode output part performs a high output resistor through a transistor which is operated in a weak inversion region. A first transistor forms a bias current corresponding to a first bias. A second transistor receives a first input signal through the body, and outputs an amplified voltage to a first node. A third transistor receives a second input signal through the body, and outputs the amplified voltage to a second node.

Description

Operational Transconductance Amplifier Circuit of being bulk-driven}

FIELD OF THE INVENTION The present invention relates to OTAs and, more particularly, to OTI circuits that do not limit input and output swing even in low voltage designs.

OTI is short for Operational Transconductance Amplifier. In particular, OTI is a circuit that converts voltage into current and amplifies it. This is an accurate expression that means that the output appearing in the output stage does not mean current, but when there is a change in voltage at the input, the appearance appears as a change in current at the output.

1 is a circuit diagram illustrating an OTI circuit that is conventionally used.

Referring to FIG. 1, the OTI circuit has a folded cascode structure. In general, the cascode structure refers to a structure in which a common source and a common gate are connected in series. That is, transistors M1 and M2 have a common source structure, and transistors M5 and M6 have a common gate structure.

This cascode structure can achieve high voltage gain and excellent frequency characteristics. That is, the cascode structure has an advantage that it is suitable for high speed operation as a one pole system having one pole.

In addition, the transconductance of the OTC circuit _shown in FIG. ₁ becomes g _{m1 , 2} of M1 and M2, which are input terminal transistors. At this time, the output resistance r _out is represented by the following Equation 1 due to the cascode configuration.

[Equation 1]

In Equation 1, gm3 is a transconductance of transistor M3, gmb3 is a transconductance according to the influence of the body of transistor M3, ro5 is an output resistance of transistor M5, ro3 is an output resistance of transistor M3, gm9 is a transconductance of transistor M9, gmb9 represents the transconductance according to the body of transistor M9, ro7 represents the output resistance of transistor M7, and ro9 represents the output resistance of transistor M9.

In addition, in Equation 1, [(gm3 + gmb3) ro5ro3] is an output resistance viewed from the output terminal toward the transistor M5, and [(gm9 + gmb9) ro7ro9] is an output resistance viewed from the output terminal facing the transistor M7.

When evaluating the output resistance, it can be seen that it has a relatively large value. This indicates that the OTI circuit has a high DC gain. The overall voltage gain is based on Equation 2 below.

[Equation 2]

In Equation 2, descriptions for gm, gmb, and ro are the same as shown in Equation 1 above. That is, gm1 represents the transconductance of transistor M1, and ro7 represents the output resistance of transistor M7. The description of the remaining symbols is interpreted in the same sense.

The operation of the circuit disclosed in FIG. 1 is as follows.

When the signals V _IP and V _IN are applied to the input terminal, the transistors M1 and M2 operate in the saturation region and form a common mode current. The sum of the currents flowing through the two transistors M1 and M2 becomes Itail.

The current generated by the transistor M1 flows into the transistor M3, and the current generated by the transistor M9 also flows into the transistor M3. That is, transistors M3 and M4 are current sources and operate as current sources in which currents generated through two paths are sinked. For this purpose, transistors M3 and M4 are set to a predetermined bias Vb1.

In addition, transistors M7 to M10 serve as current sources, and the gate terminals are set to predetermined biases Vb3 and Vb4. Current generated in transistors M9 and M10 flows into transistors M3 and M4.

In addition, transistors M5 and M6 are cascoded to transistors M1 and M2 at the input stage, respectively.

If a change occurs in the input signal V _IP or V _IN , the current generated in the transistors M1 and M2 varies. This fluctuation is represented by a change in current flowing out or flowing in the output terminal Voutn or Voutp. That is, since a constant current must flow through the transistor M3, when the amount of current is insufficient at the node X, a current must flow from the outside through the output terminal Voutn. In the opposite situation, current flows out through the output terminal Voutn.

In the above-described conventional OTC circuit, due to the limiting factor due to the threshold voltage of the input transistors M1 and M2, the input voltage does not have a wide range of input voltages. In addition, Vdd set as the power supply voltage must satisfy Equation 3 below.

[Equation 3]

Vdd = Vgs + 2V _{DS , sat}

In Equation 3, Vgs represents the absolute value of the gate-source voltage difference of the transistor M1 or M2, and 2V _{DS and sat} represent the absolute value of the voltage difference between the drain-source when the transistors M0 and M3 operate in the saturation region.

In addition, the common mode range in the input transistors M1 and M2 is according to Equation 4 below.

[Equation 4]

Vin (max) = Vdd-2V _{SDsat ( PMOS )} -| V _{T ( PMOS )} |

Vin (min) = Vss-V _{DSsat ( NMOS )} + V _{T ( NMOS )}

In Equation 4, | V _{T ( PMOS )} | represents an absolute value of the threshold voltage of the PMOS, and V _{T ( NMOS )} represents the threshold voltage of the NMOS.

In Equation 4, Vin (max) refers to the maximum input level at which the input transistor M1 or M3 and the bias transistor M0 can operate in the saturation region. Vin (min) also refers to the minimum input level at which transistor M3 can operate in the saturation region.

In addition, the output swing range of the _OTI circuit disclosed in FIG. 1 is between Vdd-2V _{SDsat (PMOS)} and Vss + 2V _{DSsat ( NMOS )} .

This swing range is a significant obstacle to the operation of the circuit during low voltage driving.

Therefore, there is a need for an OTC circuit having a wide input range and a large output swing range and capable of smoothly driving even at a low voltage.

An object of the present invention for solving the above problems is to provide an OTC circuit having a wide input range and a large output swing width, suitable for low power driving.

The present invention for achieving the above object, the input signal is applied to the body of the input transistors, the bulk driver for increasing the voltage regardless of the threshold voltage; An active rod unit configured to perform a positive feedback operation to further accelerate the increase or decrease of the output signal of the bulk driver; And a self-cascode output that implements high output resistance through transistors operating in the weak inversion region.

According to the present invention, the OTI circuit can secure a high input impedance due to the input stage performing bulk driving, and can secure a wide input swing range without burdening a threshold voltage. Also, the output impedance seen at the output stage is increased by the transistor operating in the weak inversion region. Therefore, a wide output swing width can be obtained.

As the inventive concept allows for various changes and numerous embodiments, particular embodiments will be illustrated in the drawings and described in detail in the text. However, this is not intended to limit the present invention to the specific disclosed form, it should be understood to include all modifications, equivalents, and substitutes included in the spirit and scope of the present invention. In describing the drawings, similar reference numerals are used for similar elements.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art. Terms such as those defined in the commonly used dictionaries should be construed as having meanings consistent with the meanings in the context of the related art and shall not be construed in ideal or excessively formal meanings unless expressly defined in this application. Do not.

Hereinafter, with reference to the accompanying drawings, it will be described in detail a preferred embodiment of the present invention.

Example

2 is a circuit diagram illustrating a bulk-driven OTC circuit in accordance with a preferred embodiment of the present invention.

Referring to FIG. 2, the bulk-driven OTC circuit has a bulk driver 100, an active rod 120, and a self-cascode output 140.

The bulk driver 100 includes a transistor Q1 which is a constant current source, a transistor Q2 and Q3 connected to a common source. In addition, the bulk driver 100 is connected between the positive power supply voltage Vdd and the active load unit 120.

First, the first bias Vb1 is applied to the gate terminal of the transistor Q1 which is a constant current source. In addition, transistor Q1 produces a bias current Itail corresponding to first bias Vb1. The bias current Itail is fed to the common source connected transistors Q2 and Q3.

The transistors Q2 and Q3 have a structure in which gate terminals are connected to each other, and a first input signal Vip and a second input signal Vin are applied through a body. In other words, the input signal is applied to the bulk of the transistor. Hereinafter, the bulk and the body of the transistor refer to the same component and are used interchangeably in the same sense. When an input signal is applied to the body of the transistor, the absolute value of the threshold voltages of the corresponding transistors Q2 and Q3 rises. This results in a decrease in the current flowing through the transistor with the voltage applied to the body increased. In the present invention, in order to operate the two input terminal transistors Q2 and Q3 in the active region, a second bias Vb2 suitable for causing strong inversion of the PMOS transistor is applied to the gate terminal of both transistors.

Strong inversion refers to a state in which a channel is formed substantially below the gate. The current flowing through the channel is due to the voltage difference between the source and the drain. This means that the gate voltage controls the charge in the inversion region. In addition, the concentration of charge formed across the channel is nearly constant. Thus, the drift current due to the electric field applied between the source-drain terminals is dominant.

The second bias Vb2 is applied to the gate terminals of the transistors Q2 and Q3, and the input signals Vin and Vip are applied between the body and the source terminal of each transistor. The current flowing between the drain and the source changes due to the voltage applied to the body, which is similar to the operating characteristics of the junction field effect transister (FET). As a result, the characteristics of the depletion element having a high input impedance can be obtained at the input terminal.

The biggest advantage of the bulk-driven approach is that there is no limit on the threshold voltage, since a signal is input to the bulk and the signal can be applied in both the positive and negative directions with respect to the source voltage.

Thus, an input range without limiting the threshold voltage can be obtained. That is, a wide range of inputs is possible.

Subsequently, an active rod 120 is provided at the lower end of the bulk driver 100. That is, the active rod 120 is connected between the bulk driver 100 and the negative power supply voltage Vss.

The active load unit 120 forms a voltage corresponding to a current generated by the application of the first input signal Vip and the second input signal Vin. In addition, the active rod 120 serves to quickly increase the level of the output voltage of the bulk driver 100 through positive feedback.

The active rod unit 120 includes a first rod 121, a second rod 123, and a positive feedback unit 125.

The first rod 121 is a diode-connected structure of the fourth transistor Q4. The first rod 121 is connected to the drain terminal of the second transistor Q2. In addition, the second load 123 is a diode-connected structure of the fifth transistor Q5. The second rod 123 is connected to the drain terminal of the third transistor Q3.

The positive feedback unit 125 includes a sixth transistor Q6 connected between the second node N2 and the negative power supply voltage Vss and a seventh transistor Q7 connected between the first node N1 and the negative power supply voltage Vss. In addition, the gate terminal of the seventh transistor Q7 is connected to the gate terminal of the diode-connected Q5. In addition, the gate terminal of the sixth transistor Q6 is connected to the gate terminal of the diode-connected fourth transistor Q4.

When the voltage of the first node N1 or the second node N2 rises or falls, the operation of the positive feedback unit 125 raises or lowers it more quickly. For example, when the voltage of the first node N1 rises due to a change in the input signal Vin or Vip, the current passing through the fourth transistor Q4 rises. In addition, since the voltage between the gate and the source of the sixth transistor Q6 operating in the active region increases, the current flowing through the sixth transistor Q6 also increases. This means that the current flowing through the diode-connected fifth transistor Q5 is reduced. Thus, the voltage at the second node N2 is reduced. That is, when the voltage of the first node N1 rises, the voltage of the second node N2 falls faster. In addition, when the voltage of the second node N2 increases, the voltage of the first node N1 decreases more quickly.

Accordingly, it can be seen that the sixth transistor Q6 performs the positive feedback operation on the voltage of the second node N2, and the seventh transistor Q7 performs the positive feedback operation on the voltage of the first node N1.

Subsequently, the self cascode output unit 140 includes an output stage 141 and a current mirror 143.

The output stage 141 is connected between the output terminals Voutn and Voutp and the negative power supply voltage Vss. The output stage 141 is composed of four transistors of the eighth transistor Q8 to the eleventh transistor Q11. Gates of the eighth transistor Q8 and the tenth transistor Q10 are commonly connected, and the commonly connected gate terminal is connected to the second node N2.

In addition, the gates of the ninth transistor Q9 and the eleventh transistor Q11 are commonly connected to each other, and the commonly connected gate terminal is connected to the first node N1.

Some of the transistors of the output stage 141 having the above-mentioned connection operate in the weak inversion region. That is, the tenth transistor Q10 and the eleventh transistor Q11 operate in the weak inversion region. On the other hand, it is preferable that the eighth transistor Q8 and the ninth transistor Q9 operate in the active region.

The weak inversion occurs when a channel is not substantially formed in the transistor, and a voltage below a threshold voltage is also applied to the gate terminal. In addition, it refers to a case where the substrate surface under the gate insulating film is inverted weakly.

In the weak inversion region, the drift current is nearly insignificant, resulting in a concentration gradient of charge in the channel. Therefore, a current occurs due to the diffusion of the charge, which is called a subthreshold current. This is due to the diffusion phenomenon of the carrier occurring in the cut-off region in the operating aspect of the transistor.

In order to operate with weak inversion, the tenth and eleventh transistors Q10 and Q11 increase the aspect ratio W / L (W: channel width, L: channel length) of the corresponding transistors Q10 and Q11 compared with other transistors. . Operation in the weak inversion region causes the transistors to be modeled as a transistor together. That is, transistor Q8 and transistor Q10 can be modeled as one transistor, and the modeled transistor has a common source structure. The same applies to the transistors Q9 and Q11.

Due to transistors Q10 and Q11 operating in the weak inversion region, the output resistance facing the output stage 141 at the output terminals Voutn and Voutp has a very large value. This is due to the fact that transistors operating in the weak inversion region operate in the DC cut-off region.

The current mirror 143 is then connected between the positive supply voltage Vdd and the output terminals Voutn, Voutp. The current mirror 143 is composed of twelfth transistors Q12 to 15th transistor Q15. The twelfth transistor Q12 is connected to the fourteenth transistor Q14, and the gate terminals are commonly connected to each other. In addition, the gate terminals of the twelfth transistors Q12 to 15th transistor Q15 are commonly connected to each other, which is biased by the third bias Vb3. Thus, the twelfth transistor Q12 and the thirteenth transistor Q13 generate a predetermined biasing current, and the biasing currents flowing through both transistors Q12 and Q13 are equal to each other.

In the current mirror 143, the fourteenth transistor Q14 and the fifteenth transistor Q15 operate in a weak inversion region. To this end, W / L, which is an aspect ratio of the fourteenth and fifteenth transistors Q14 and Q15, is designed to be higher than that of other transistors. In addition, the transistors Q12 and Q14 constituting the current mirror by the transistor operating in the weak inversion region can be modeled as one transistor, which applies equally to the transistors Q13 and Q15.

By the transistors Q14 and Q15 operating in the weak inversion region, the output resistance facing the current mirror 143 at the output terminals Voutn and Voutp becomes very large. Therefore, the output resistance looking at the circuit at the output stage as a whole has a very large value.

In addition, the swing widths of the output signals Voutn and Voutp increase compared with the conventional OTI circuit shown in FIG. That is, Vdd- | V _{DS ( PMOS )} | and Vss + | V _{T ( NMOS )} | You can swing between them.

The transconductance of the OTI circuit using the bulk-drive shown in FIG. 2 is given by Equation 5 below.

[Equation 5]

는 몸체효과계수로서 0.2 내지 0.4 V^1/2를 가지며, K'는 트랜지스터의 이동도와 게이트 커패시턴스 C_ox와의 곱이다. 또한, V_s,tail은 입력단 소스의 전압값이며, V_i는 벌크로 인가되는 입력 전압을 지칭하고,

는 트랜지스터의 페르미 전위를 나타낸다.In Equation 5 n is 1 + g _mb / g _m ,

Has a body effect coefficient of 0.2 to 0.4 V ^1/2 , and K 'is the product of the transistor mobility and the gate capacitance C _ox . In addition, V _{s, tail} is the voltage value of the input terminal source, V _i refers to the input voltage applied in bulk,

Denotes the Fermi potential of the transistor.

The gain of the OTI circuit using the transconductance obtained in Equation 5 is given by Equation 6 below.

[Equation 6]

In Equation 6, B is (W / L) _8,9 / (W / L) _5,6 as a gain of the current mirror, and r _out represents total output resistance of the output terminal. Denotes the aspect ratio of the transistors Q5 and Q7 as positive feedback factors. That is, α is (W / L) _6,7 / (W / L) _4,5 .

The value of α is set to 0.5 to 0.9. Preferably α is set to 2/3. If the value of α is above 0.9, the high gain allows the OTI circuit to operate as a Schmitter or comparator, and below 0.5 the low gain causes problems in its native operation as an amplifier.

If the load capacitance of the OT circuit of FIG. 2 is C _L , the gain-bandwidth (GBW) of the OT circuit is expressed by Equation 7 below.

[Equation 7]

In Equation 7, GBW is affected by α, and α is affected by the positive feedback of the active rod part. Therefore, GBW rises by appropriate selection of α. That is, the frequency band capable of maintaining the gain according to Equation 6 is expanded. This value of α is affected by the positive feedback circuit of the active rod portion. Accordingly, it can be seen that the frequency band of the OTI circuit is extended by the positive feedback of the active rod part, thereby improving the frequency characteristic.

As described above, the OTI circuit according to the present invention can obtain a wide input range and a high frequency characteristic, and can obtain a high voltage gain and a wide output swing range.

1 is a circuit diagram illustrating an OTI circuit that is conventionally used.

2 is a circuit diagram illustrating a bulk-driven OTC circuit in accordance with a preferred embodiment of the present invention.

Claims (7)

A bulk driver configured to apply an input signal to the bodies of the input transistors and increase the voltage regardless of the threshold voltage; An active rod unit configured to perform a positive feedback operation to further accelerate the increase or decrease of the output signal of the bulk driver; And Bulk drive OTC circuit comprising a self-cascode output that implements high output resistance through transistors operating in a weak inversion region. The method of claim 1, wherein the bulk drive unit, A first transistor forming a bias current corresponding to the first bias; A second transistor connected to the first transistor, receiving a first input signal through a body, and outputting an amplified voltage to the first node; And A third transistor having a common gate connected to the second transistor, receiving a second input signal through a body, and outputting an amplified voltage to a second node; The second transistor and the third transistor perform bulk-drive and receive a second bias through the gates. The method of claim 2, wherein the active rod unit, A first rod connected to the first node and having a fourth transistor having a diode-connected structure; A second rod connected to the second node and having a fifth transistor having a diode-connected structure; And And a positive feedback part connected to the first node or the second node and configured to perform a positive feedback operation on the first node or the second node voltage. The method of claim 3, wherein the positive feedback unit, A sixth transistor connected between the first node and a negative power supply voltage and configured to perform a positive feedback operation on the voltage of the second node; And And a seventh transistor connected between the second node and the negative power supply voltage, and configured to perform a positive feedback operation with respect to the voltage of the first node. The method of claim 2, wherein the self-cascode output unit, An output stage connected between the negative power supply voltage and the output terminal and configured to form an output signal; And And a current mirror coupled between a positive supply voltage and the output terminal, the current mirror for supplying a bias current to the output scale. 6. The bulk drive otie circuit of claim 5, wherein the output stage has a transistor operating in a weak inversion region and is modeled as a common source structure. 6. The bulk drive otie circuit of claim 5 wherein the current mirror has a transistor operating in a weak inversion region.

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