KR20090088038A - Method of forming the trench isolation layer for semiconductor device - Google Patents

Method of forming the trench isolation layer for semiconductor device Download PDF

Info

Publication number
KR20090088038A
KR20090088038A KR1020080013337A KR20080013337A KR20090088038A KR 20090088038 A KR20090088038 A KR 20090088038A KR 1020080013337 A KR1020080013337 A KR 1020080013337A KR 20080013337 A KR20080013337 A KR 20080013337A KR 20090088038 A KR20090088038 A KR 20090088038A
Authority
KR
South Korea
Prior art keywords
semiconductor device
device isolation
forming
trench
insulating film
Prior art date
Application number
KR1020080013337A
Other languages
Korean (ko)
Inventor
양인권
Original Assignee
주식회사 하이닉스반도체
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR1020080013337A priority Critical patent/KR20090088038A/en
Publication of KR20090088038A publication Critical patent/KR20090088038A/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02337—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour
    • H01L21/0234—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour treatment by exposure to a plasma
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02345—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to radiation, e.g. visible light
    • H01L21/02348—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to radiation, e.g. visible light treatment by exposure to UV light
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Element Separation (AREA)

Abstract

A method of forming the trench isolation layer for semiconductor device is provided to prevent the overhang formation of the insulating layer due to the deformation of the insulating layer. The trench(108) is formed on the device isolation region of the semiconductor substrate(102). The insulating layer is formed on the trench. The dopant gas removal process is performed on the insulating layer. The dopant gas removal process includes the cleaning process on the insulating layer. The anisotropic conductive film(104) for floating gate is formed on the tunnel insulation layer(103). The photoresist pattern is formed on the hard mask film(106).

Description

Method of forming the trench isolation layer for a semiconductor device

The present invention relates to a method of forming a device isolation film of a semiconductor device, and more particularly, to a method of forming a device isolation film of a semiconductor device using a shallow trench isolation (STI) method.

In general, a semiconductor device formed on a wafer includes a device isolation region for electrically separating each semiconductor device. In particular, as semiconductor devices have been highly integrated and miniaturized, research on not only reducing the size of each semiconductor device but also reducing the device isolation region has been actively conducted. This is because the formation of the device isolation region influences the size of the active region and the process margin of the post-process step as the initial step in all manufacturing steps.

A method of forming a shallow trench isolation (STI) method as described above is as follows. First, a nitride film having a different etching selectivity from the semiconductor substrate is formed on the semiconductor substrate, and the nitride film is patterned to form the nitride film in order to use the nitride film as a hard mask. A trench is formed by etching the device isolation region of the semiconductor substrate by an etching process using the nitride layer pattern as a hard mask. Subsequently, an insulating material is formed on the semiconductor substrate including the trench to fill the trench with the insulating material, and the insulating material is left in the trench by performing a planarization process such as chemical mechanical polishing (CMP). An element isolation film is formed.

Meanwhile, as the semiconductor manufacturing process technology becomes finer, the aspect ratio of the trench becomes larger.In this case, a process of gap-filling a portion of the trench, etching and then gap-filling a portion of the trench instead of gap-filling the trench with an insulating layer is performed several times. do. In this case, when a defect occurs in a part of the insulating film to be formed, voids may be continuously generated due to the defect in the subsequently formed insulating film.

FIG. 2 is a cross-sectional SEM (Scanning Electron Microscope) photograph of a device showing that a defect (reference numeral A) occurs in a device isolation film formed according to the prior art.

Referring to FIG. 2, when gap trenches are formed with a plurality of insulating films including an insulating film containing an impurity gas such as fume, the impurity gas expands inside the insulating film through a heat treatment process to improve the quality of the insulating film. To generate a defect (reference numeral A). Due to such a defect (reference numeral A), voids are generated in the device isolation layer, which lowers the insulating property of the semiconductor device, and the semiconductor device may fail. In addition, the active region and the stacked gate may be inclined to deteriorate characteristics of the semiconductor device. Therefore, it is important to prevent the formation of a cause such as impurity gas defects in the device isolation film.

The present invention removes the impurity gas by performing a cleaning process or a heat treatment process on the insulating film that can be formed by attaching the impurity gas, thereby preventing defects that may occur due to the expansion of the impurity gas in the insulating film during the subsequent heat treatment process. have.

An element isolation film forming method of a semiconductor device of the present invention includes forming a trench in an element isolation region of a semiconductor substrate, forming an insulating film in the trench, and performing an impurity gas removing process on the insulating film. It is characterized by.

The impurity gas removing process may include a cleaning process for the insulating film. The cleaning process may be performed with a BN solution (H 2 SO 4 + NH 4 OH). The washing step may be performed by adding mega sonic to a bath of a multi-tank type.

The impurity gas removing process may include a heat treatment process for the insulating film. The heat treatment process may include a plasma treatment method. The plasma processing method may be any one of a chamber using a microwave as a plasma source, an inductively coupled plasma (ICP), a capacitively coupled plasma (CCP), a transformer coupled plasma (TCP), and a magnetically enhanced reactive ion etching (MERIE). It can be carried out in a chamber using one. The plasma treatment method can be carried out at an oxygen gas or a mixed gas atmosphere of oxygen gas and nitrogen gas at a temperature of 230 ° C to 950 ° C. The heat treatment process may include a hard bake method. The hard baking method may be performed in a baking oven at a temperature of 150 ° C. to 450 ° C. for 10 minutes to 1 hour. The heat treatment process may include a UV erasing method. The UV erasing method may be performed for 30 seconds to 150 seconds in a UV chamber at a temperature of 150 ~ 450 ℃.

According to the device isolation film forming method of the semiconductor device of the present invention, it is possible to prevent a defect due to the impurity gas existing in the insulating film forming the device isolation film. As a result, a space is formed inside the device isolation layer, thereby preventing the insulating role from forming the device isolation layer or bending the active region. As a result, a single row fail can be prevented and the number of invalid blocks can be reduced to maximize the process yield. In addition, it is possible to prevent the problem that the sidewalls of the conductive film are removed during the insulating film forming and etching process, thereby preventing overhang formation of the insulating film due to deformation of the conductive film sidewall profile.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention.

However, the present invention is not limited to the embodiments described below, but may be implemented in various forms, and the scope of the present invention is not limited to the embodiments described below. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention. Only this embodiment is provided to complete the disclosure of the present invention and to fully inform those skilled in the art, the scope of the present invention should be understood by the claims of the present application. In addition, when an arbitrary film is described as being formed on another film or on a semiconductor substrate, the arbitrary film may be formed in direct contact with the other film or the semiconductor substrate, or may be formed with a third film interposed therebetween. . In addition, the thickness or size of each layer shown in the drawings may be exaggerated for convenience and clarity of description.

1A to 1F are cross-sectional views of devices shown for explaining a device isolation film forming method of a semiconductor device of the present invention.

Referring to FIG. 1A, a screen oxide layer (not shown) is formed on a semiconductor substrate 102, and a well ion implantation process or a threshold voltage ion implantation process is performed on the semiconductor substrate 102. Here, the well ion implantation process is performed to form a well region in the semiconductor substrate 102, and the threshold voltage ion implantation process is performed to adjust the threshold voltage of a semiconductor device such as a transistor. In this case, the screen oxide layer (not shown) prevents the surface of the semiconductor substrate 102 from being damaged during the well ion implantation process or the threshold voltage ion implantation process. As a result, a well region (not shown) may be formed in the semiconductor substrate 102, and the well region may be formed in a triple structure.

After the screen oxide film (not shown) is removed, the tunnel insulating film 103 is formed on the semiconductor substrate 102 in order to manufacture the NAND flash device among the semiconductor devices. The tunnel insulating layer 103 may pass electrons through a F / N tunneling phenomenon. Accordingly, electrons may move from the channel region formed under the tunnel insulating layer 103 to the floating gate formed on the tunnel insulating layer 103, or electrons included in the floating gate may move to the channel region. The tunnel insulating film 103 may be formed of an oxide film.

A floating gate conductive film 104 is formed on the tunnel insulating film 103. The conductive layer 104 may accumulate or emit electrons. Accordingly, electrons moved from the semiconductor substrate 102 through the tunnel insulating film 103 during the programming operation are accumulated and programmed in the conductive film 104, or charge stored in the conductive film 104 during the erase operation is stored in the tunnel insulating film 103. Through the semiconductor substrate 102 may be emitted through. The conductive film 104 is preferably formed of polysilicon.

Next, a hard mask film 106 is formed on the conductive film 104. The hard mask layer 106 may be used as a subsequent trench etching process etching mask and may be formed of a nitride film.

Referring to FIG. 1B, a photoresist pattern (not shown) is formed on the hard mask film 106. The photoresist pattern may be formed such that the upper portion of the device isolation region of the semiconductor substrate 102 is opened. The hard mask film 106, the conductive film 104, the tunnel insulating film 103, and the semiconductor substrate 102 are etched by an etching process using a photoresist pattern. As a result, a trench 108 is formed on the isolation region of the semiconductor substrate 102. The photoresist pattern is then removed.

Referring to FIG. 1C, the first insulating layer 110 is formed on the semiconductor substrate 102 including the trench 108. The first insulating layer 110 is formed along a step formed by the trench 108, and is formed to a thickness capable of maintaining the step formed by the trench 108. The first insulating layer 110 may fill a portion of the bottom surface of the trench 108 to reduce the depth at which the trench 108 should be gapfilled in a subsequent process to further secure a margin of the trench 108 gapfill process. In addition, the first insulating layer 110 may be formed on the sidewalls of the trench 108 to prevent the tunnel insulating layer 103 and the conductive layer 106 exposed on the sidewalls of the trench 108 from being damaged in a subsequent process. . The first insulating layer 110 may be formed of a high aspect ratio process (HARP) oxide film, a high temperature oxidation (HTO) film, or a heat treated polysilazane (PSZ) film.

Meanwhile, after the first insulating film 110 is formed, a post treatment process is performed on the first insulating film 110 in order to volatilize and remove impurity gases such as fumes remaining in the first insulating film 110. Impurity gas removal process is carried out through. The impurity gas removing process may be performed by a cleaning process or a heat treatment process for the first insulating film 110.

When the cleaning process is performed on the first insulating film 110 as an impurity gas removing process, in order to minimize the amount of loss of the first insulating film 110, the BN solution (without using HF solution, RON solution, or BON solution) is used. H 2 SO 4 + NH 4 OH). In addition, mega sonic may be added to the bath of the multi-tank type so as to more easily remove the fume during the cleaning process.

In addition, when the heat treatment process is performed on the first insulating film 110 as an impurity gas removing process, it may be performed by a plasma treatment method, a hard bake method, or a UV erasing method. In this heat treatment process, the film quality of the first insulating layer 110 may be made more dense, thereby lowering the etch rate of the first insulating layer 110. Accordingly, the first insulating layer 110 may be removed during the subsequent wet process to prevent the conductive layer 106 from being exposed and damaged. If the sidewalls of the conductive layer 106 are exposed and lost, the sidewalls of the conductive layer 106 may be recessed and thus overhang may occur due to the sidewall profile of the conductive layer 106 in a subsequent insulating gap fill process.

When the plasma treatment method is applied to the first insulating film 110, it can be carried out at an oxygen gas or a mixed gas atmosphere of oxygen gas and nitrogen gas at a temperature of 230 ° C. to 950 ° C. In this case, any one of a chamber using a microwave as a plasma source, an inductively coupled plasma (ICP), a capacitively coupled plasma (CCP), a transformer coupled plasma (TCP), and a magnetically enhanced reactive ion etching (MERIE) are used. The plasma treatment method may be performed in a chamber.

In addition, when the hard bake method is applied to the first insulating film 110, the bake oven may be performed in a baking oven at a temperature of 150 ° C. to 450 ° C. for 10 minutes to 1 hour. In addition, when the UV erasing method is applied to the first insulating film 110, the UV insulating method may be performed in a UV chamber at a temperature of 150 to 450 ° C. for 30 seconds to 150 seconds.

Meanwhile, an impurity gas such as fume, which has already been generated in the process before forming the first insulating layer 110, remains in the front opening unified POD (FOUP) and is formed in the first insulating layer 110. Along with the impurity gas of the defect may occur more large. Therefore, it is preferable to replace the FOUP after forming the first insulating film 110 to block adverse effects from impurity gases such as fumes remaining in the FOUP.

Referring to FIG. 1D, a second insulating film 112 is formed on the first insulating film 110 to gap fill the trench 108. The second insulating layer 112 is preferably formed of a HARP oxide film or a PSZ oxide film having excellent step coverage so as to easily gap fill the trench 108 having a large aspect ratio due to the reduction of the semiconductor device. Then, a heat treatment process is performed on the second insulating film 112 to make the film quality more dense. When the heat treatment process is performed on the second insulating film 112, impurities such as moisture included in the film are removed, thereby making the film quality more dense, and the etching rate may be reduced to about 40 to 60% before the heat treatment. Thus, by forming the film quality densely, it is possible to prevent the voids exposed in the subsequent etching or cleaning process for the insulating film.

Meanwhile, since all the impurity gases such as fume included in the first insulating film 110 are removed in the above-described impurity gas removing process, the impurity gas is expanded during the heat treatment process with respect to the second insulating film 112. A space may be formed inside the insulating layer 112 to prevent an insulating role as an isolation layer or to prevent an active region from bending. Accordingly, a single row fail can be prevented from occurring, thereby reducing the number of invalid blocks and improving the maximum yield.

Referring to FIG. 1E, a planarization process, such as a chemical mechanical polishing (CMP) method, may be performed on the second insulating layer 112, and an additional etching process such as etch back may be performed. Lower the height of 112). As a result, the height of the second insulating layer 112 is formed to be lower than that of the tunnel insulating layer 103 of the semiconductor substrate 102. In this case, the first insulating film 110 may be removed together, but in the above-described process, since the film quality of the first insulating film 110 is dense, the etching speed may be significantly lower than that of the second insulating film. Accordingly, the conductive layer 104 may be damaged by delaying the time point at which the sidewall of the conductive layer 104 is exposed during the etching process of the second insulating layer 112, thereby minimizing the time that the sidewall of the conductive layer 104 is exposed to the etchant. The problem can be recalled.

Referring to FIG. 1F, the third insulating layer 114 is formed on the second insulating layer 112 to gap fill the trench 108 with the third insulating layer 114. As a result, an isolation layer including the first insulating layer 110, the second insulating layer 112, and the third insulating layer 114 is formed in the trench 108. A portion of the upper portion of the third insulating layer 114 may be etched to lower the height of the third insulating layer 114.

On the other hand, although the embodiment of the present invention has been described as performing the impurity gas removing process for the liner insulating film 110 of the insulating film formed in the trench 108, the fume (fume) of the insulating film formed in the trench 108 It is natural that any of the insulating films on which the impurity gas may be formed may be subjected to a treatment step for removing the insulating film. This impurity gas removing step is preferably performed before forming another insulating film on the insulating film.

1A to 1F are cross-sectional views of devices shown for explaining a device isolation film forming method of a semiconductor device of the present invention.

<Description of the symbols for the main parts of the drawings>

102 semiconductor substrate 103 tunnel insulating film

104: conductive film for floating gate 106: hard mask film

108: trench 110: first insulating film

112: second insulating film 114: third insulating film

Claims (12)

Forming a trench in the device isolation region of the semiconductor substrate; Forming an insulating film in the trench; And And removing the impurity gas from the insulating film. The method of claim 1, And removing the impurity gas from the semiconductor device. The method of forming an isolation layer of a semiconductor device includes cleaning the insulating film. The method of claim 2, The cleaning step is a device isolation film forming method of a semiconductor device performed by BN solution (H 2 SO 4 + NH 4 OH). The method of claim 2, The method of forming a device isolation film of a semiconductor device, wherein the cleaning step is performed by applying mega sonic to a multi-bath type bath. The method of claim 1, The method of removing an impurity gas may include a heat treatment process for the insulating layer. The method of claim 5, And the heat treatment step includes a plasma treatment method. The method of claim 6, The plasma processing method may be any one of a chamber using a microwave as a plasma source, an inductively coupled plasma (ICP), a capacitively coupled plasma (CCP), a transformer coupled plasma (TCP), and a magnetically enhanced reactive ion etching (MERIE). A device isolation film formation method for a semiconductor device carried out in a chamber using one. The method of claim 6, The plasma treatment method is a device isolation film forming method of a semiconductor device carried out in an oxygen gas or a mixed gas atmosphere of oxygen gas and nitrogen gas at a temperature of 230 ℃ to 950 ℃. The method of claim 5, The heat treatment process is a device isolation film forming method of a semiconductor device comprising a hard bake (hard bake) method. The method of claim 9, The hard bake method is a device isolation film forming method of a semiconductor device performed for 10 minutes to 1 hour in a baking oven at a temperature of 150 ℃ to 450 ℃. The method of claim 5, The heat treatment step is a device isolation film forming method of a semiconductor device comprising a UV erasing method. The method of claim 11, The UV erasing method is a device isolation film forming method of a semiconductor device performed for 30 seconds to 150 seconds in a UV chamber at a temperature of 150 ~ 450 ℃.
KR1020080013337A 2008-02-14 2008-02-14 Method of forming the trench isolation layer for semiconductor device KR20090088038A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020080013337A KR20090088038A (en) 2008-02-14 2008-02-14 Method of forming the trench isolation layer for semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020080013337A KR20090088038A (en) 2008-02-14 2008-02-14 Method of forming the trench isolation layer for semiconductor device

Publications (1)

Publication Number Publication Date
KR20090088038A true KR20090088038A (en) 2009-08-19

Family

ID=41206822

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020080013337A KR20090088038A (en) 2008-02-14 2008-02-14 Method of forming the trench isolation layer for semiconductor device

Country Status (1)

Country Link
KR (1) KR20090088038A (en)

Similar Documents

Publication Publication Date Title
CN1217404C (en) Method for making flashing storage element
KR20080031076A (en) Method for manufacturing a non volatile memory device
KR20030053317A (en) Method of manufacturing a flash memory cell
KR100406179B1 (en) Method of forming a self aligned floating gate in flash memory cell
US20050233521A1 (en) Method for forming dielectric layer between gates in flash memory device
US20090170280A1 (en) Method of Forming Isolation Layer of Semiconductor Device
KR20080095621A (en) Method of forming an isolation layer in semiconductor device
KR20060135219A (en) Method for fabricating dielectric layer in flash memory device
KR20110010628A (en) Semiconductor device manufacturing method
KR100745954B1 (en) Method for fabricating flash memory device
KR20060122139A (en) Method for fabricating flash memory device
US20090068818A1 (en) Method of forming an isolation layer of a semiconductor device
KR20090088038A (en) Method of forming the trench isolation layer for semiconductor device
KR100611469B1 (en) Method of forming a isolation layer in a semiconductor device
KR101008986B1 (en) Method for forming gate of transistor
KR100482760B1 (en) Method of manufacturing a flash memory device
KR100545207B1 (en) A method for isolating a semiconductor device
KR100854896B1 (en) Method for manufacturing flash memory device
KR100598334B1 (en) Method of forming a isolation layer in semiconductor device
KR20100013969A (en) Method of forming a isolation layer in semiconductor device
KR100590391B1 (en) Method of manufacturing flash memory device
KR100691943B1 (en) Method of manufacturing a semiconductor device
KR100278681B1 (en) Method of making trench isolation
KR100741275B1 (en) Method for fabrication of semiconductor device
KR20080002062A (en) Method of manufacturing flash memory device

Legal Events

Date Code Title Description
WITN Withdrawal due to no request for examination