KR20090082674A - Pattern forming method using top surface imaging and double patterning technology - Google Patents

Abstract

A pattern formation method using TSI and double patterning process for improving a process margin is provided to prevent a pattern collapse by using the excellent etching selectivity of an SiO2 layer. A pattern formation method of a semiconductor device applies a top surface imaging process in a double patterning process. An etched layer(13) is formed at the upper part of the semiconductor substrate(11). The photo-resist composition is coated on the etched layer and the first photo-resist is formed. The exposed first photo-resist is silylation and the silylation film is formed. The silylation layer pattern is to the etching mask and the first photo-resist is etched and the first photo-resist pattern is formed. After the second photosensitive film is formed on the first photo-resist pattern upper, the second photosensitive pattern is taken shape in order not to overlap with the first photo-resist pattern.

Description

Pattern forming method using TSI and double patterning process {Pattern forming method using top surface imaging and double patterning technology}

The present invention relates to a method of forming a pattern of a semiconductor device, and more particularly, to a method of forming a fine pattern in which a top surface imaging (TSI) process is applied during a double patterning process.

The exposure equipment currently used by device manufacturers uses KrF light sources at 100 nm nodes and ArF light sources at 60 nm nodes. However, research is currently being conducted on the formation of fine contact holes and lines / spaces of 45nm node devices, and an accurate roadmap for smaller 30nm node pattern formation has not been formed. Much research is being done on the development of sub-60nm patterns, i.e. devices below 45nm or 30nm nodes, and the most promising methods are EUV and nanoimprint methods as the most likely alternatives to immersion lithography using ArF light sources. have.

However, due to the delay in the development of new EUV equipment and the investment cost of applying new lithography, there are many shortcomings in applying the EUV and nanoimprint methods to the actual process. Therefore, as part of an effort to form a smaller pattern while extending the ArF light source as much as possible, studies are being actively applied to apply the double patterning process.

However, current double patterning methods have limitations in the resolution of 193 nm light sources, lack pattern reproducibility (poor pattern fidelity), insufficient process margin (insufficient process window margin), and line edge roughness: LER), lack of overlay margin due to double pattern formation, and complicated and difficult process application. Therefore, even when applying the double patterning method, the 40nm line width is the limit.

In addition, a negative type photosensitive agent is mainly applied to the primary patterning, and in general, a negative type photosensitive agent has a lower resolution than a positive type photosensitive agent, and a rounding phenomenon of a pattern line occurs, which is an obstacle to active application.

In particular, the photoresist pattern formed during the primary patterning should have an excellent etching selectivity at the same time as the photoresist pattern formed by the secondary patterning.

Meanwhile, the current double patterning method performs a process of curing the primary photoresist pattern by totally irradiating the first patterned photoresist pattern to prevent intermixing of the first patterned photoresist pattern and the photoresist applied during the second patterning. Doing.

The present invention relates to a method of forming a fine pattern of a semiconductor device, which prevents mixing between photoresist layers when applying a double patterning process, and improves resolution and process margins by having an excellent etching selectivity of primary and secondary photoresist patterns. .

In order to solve the above problems, the present invention provides a method of forming a pattern of a semiconductor device, a method of forming a pattern of the semiconductor device, applying a TSI process during the double patterning process.

The TSI process may be a sillation process.

The TSI process may be applied only in the first patterning in the double patterning process, only in the second patterning, or in both.

The pattern forming method is specifically,

Forming an etched layer on the semiconductor substrate;

Forming a first photoresist film by applying a photoresist composition on the etched layer;

Exposing the first photosensitive film;

Silylating the exposed first photosensitive film to form a silylation film;

Patterning the silylation film;

Forming a first photoresist pattern by etching the first photoresist layer using the silicide film pattern as an etching mask;

Forming a second photoresist layer pattern on the first photoresist layer pattern so as not to overlap the first photoresist layer pattern; And

And etching the etched layer using the first photoresist pattern and the second photoresist pattern as an etching mask.

In addition, the pattern forming method is

Forming an etched layer on the semiconductor substrate;

Forming a first photoresist film by applying a photoresist composition on the etched layer;

Exposing and developing the first photoresist film to form a first photoresist pattern;

Forming a second photoresist layer on the first photoresist pattern;

Exposing the second photosensitive film;

Silylating the exposed second photosensitive film to form a silylation film;

Patterning the silylation film;

Forming a second photoresist pattern so that the second photoresist layer is etched using the silicide film pattern as an etch mask so as not to overlap the first photoresist pattern; And

And etching the etched layer using the first photoresist pattern and the second photoresist pattern as an etching mask.

The silylation process is preferably carried out in the liquid or gas phase for 30 to 300 seconds at a temperature of 90 to 250 ℃ using a silylating agent.

The silylating agent is hexamethyl disilazane, tetramethyl disilazane, bisdimethylamino dimethylsilane, bisdimethylamino methylsilane, dimethylsilyl dimethylamine, dimethylsilyl diethylamine, trimethylsilyl dimethylamine, trimethylsilyl diethylamine Or dimethylamino pentamethyldisilane may be used.

The method may further include presilylation baking for 30 to 300 seconds at a temperature of 90 to 250 ° C. in order to cure the photosensitive film after the post-exposure sililation.

In addition, in the process of applying the silylation process to the second photoresist pattern, after forming the first photoresist pattern and before forming the second photoresist on the first photoresist pattern, the entire surface of the first photoresist pattern is irradiated with the E-beam. By further including the step of increasing the etching selectivity of the first photosensitive film pattern.

On the other hand, in the said pattern formation method, the 1st photosensitive film or the 2nd photosensitive film to be used can select suitably a positive photosensitive agent or a negative photosensitive agent suitably depending on a case.

The method of the invention a double patterning process during the first photosensitive pattern or a second by forming a SiO ₂ layer is formed by the chamber correlation process to the photoresist pattern upper prevent pattern collapse with a superior etching selectivity of the SiO ₂ layer is not resolution and process margin It is very effective in improving the topology and forming the topology of deep and narrow steps. Thus, according to the method of the present invention, it is possible to manufacture semiconductor devices with improved and stable yields.

In addition, when applying the TSI process in the double patterning as in the present invention, there is no need to apply the organic anti-reflection film to the lower photosensitive film can be expected to simplify the process and cost reduction.

Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.

1A to 1H are cross-sectional views of a double patterning process to which silylation is applied during primary patterning.

The etched layer 13 and the first photosensitive film 15 are sequentially formed on the semiconductor substrate 11 (see FIG. 1A), and an exposure process is performed (see FIG. 1B).

Then, the silylation process is carried out using a silylating agent to form a silylation film 17 (see FIG. 1C), which is used for the subsequent etching process depending on the photoresist liquid after the reaction with the photoresist film. A silicon oxide film, that is, an SiO ₂ layer, is formed in the exposed or non-exposed areas by the O ₂ gas.

For example, in the case of using a negative photoresist, an SiO ₂ layer 19 is formed in the non-exposed region, although not shown, the silication film 17 is patterned according to a conventional process to form the SiO ₂ layer 19 ), A first photosensitive film 15 is etched using the patterned SiO ₂ layer 19 as an etch mask to form a first photosensitive film pattern 15 '(see FIG. 1D).

Then, the second photoresist film 21 is formed on the entire structure. When the SiO ₂ layer is formed on the first photoresist pattern 15 ', the first photoresist film and the second photoresist film are not easily mixed (Fig. 1e).

Then, when the second photoresist pattern 21 'is formed by secondary exposure and development, the first photoresist pattern 15' and the second photoresist pattern 21 'having the SiO ₂ layer 19 formed thereon alternately. The structure formed can be obtained (see FIG. 1G).

The etched layer 13 is etched by using the first photoresist pattern 15 ′ and the second photoresist pattern 21 ′ having the SiO ₂ layer 19 formed thereon as an etching mask. (See FIG. 1H). Since the first photoresist pattern 15 ′ having the SiO ₂ layer 19 formed thereon has an excellent etching selectivity, the lower hard mask layer can be formed to a low thickness, which is very advantageous for selecting a hard mask, thereby effectively forming a fine pattern. Can be.

1A to 1H illustrate a case in which a negative photosensitive agent is used for primary patterning, that is, a silylation process, and a positive photosensitive agent is used for secondary patterning, but the present invention is not limited thereto, and a positive or negative photosensitive agent is used. Can be selected according to the use.

2A to 2H are cross-sectional views of a double patterning process using sililation during secondary patterning.

An etched layer 13 and a first photosensitive film 15 are sequentially formed on the semiconductor substrate 11 (see FIG. 2A), a first exposure process is performed (see FIG. 2B), and developed to form a first photosensitive film pattern. (15 ') (see Figure 2c).

The second photosensitive film 21 is coated on the first photosensitive film pattern 15 '(see FIG. 2D) and subjected to secondary exposure (see FIG. 2E).

Then, the silylation process is performed using a silylating agent to form a silylation film 17 (see FIG. 2F), which is used for the subsequent etching process depending on the photoresist liquid after the reaction with the photoresist film. A silicon oxide film, that is, an SiO ₂ layer, is formed in the exposed or non-exposed areas by the O ₂ gas.

For example, in the case of using a negative photoresist, an SiO ₂ layer 19 is formed in the non-exposed region, although not shown, the silication film 17 is patterned according to a conventional process to form the SiO ₂ layer 19 ), And the second photosensitive film 21 is etched using the patterned SiO ₂ layer 19 as an etch mask to form a second photosensitive film pattern 21 '(see FIG. 2G). As can be seen in FIG. 2G, a structure in which the first photoresist pattern 15 'and the second photoresist pattern 21' having the SiO ₂ layer 19 formed thereon are alternately formed.

The etched layer 13 is etched using the first photoresist pattern 15 'and the second photoresist pattern 21' having the SiO ₂ layer 19 formed thereon as an etch mask, thereby etching the etched layer pattern 13 '. (See FIG. 2H).

As described above, the application of the silylation process during the second patterning has an excellent advantage of improving the pattern collapse caused by the high aspect ratio during the second patterning. When the silylation process is applied during the second patterning, the first photoresist pattern 15 'is formed and then the E-beam entire surface is irradiated before the application of the second photoresist 21 to etch the primary photoresist pattern 15'. It is more preferable to increase the resistance.

On the other hand, when the primary photosensitive film is formed using a negative photosensitive agent, the photoresist pattern is crosslinked, so there is no problem in etching resistance even if the E-beam entire surface is not irradiated.

2A to 2H illustrate a case in which a positive photosensitive agent is used for primary patterning and a negative photosensitive agent is used for secondary patterning, that is, a silylation process, but the present invention is not limited thereto, and a positive or negative photosensitive agent is used. Can be selected according to the use.

The following example describes a specific method capable of forming a stable fine pattern by applying a double patterning process and a TSI process according to the present invention.

Example 1.

After coating, baking and exposing NTS4, which is an ArF resist for TSI, on top of the hard mask nitride, and exposing, a presilylation bake process was performed at 120 ° C. for 90 seconds. Then, tetramethyl disilazane was used to silylate the gas phase at 170 ° C. for 150 seconds. Subsequently, in the etching chamber, the wafer is placed in one step with fluorine / O ₂ / SO _2. It was etched in an etching chamber at -10 ° C using a mixed gas of. At this time, the silicon dioxide layer is formed in a portion where the chemical bond with tetramethyl disilazane in the non-exposed area. O ₂ / SO ₂ in the subsequent etching process The first pattern was formed by dry etching the non-exposed areas with the silicon dioxide layer as a barrier. Subsequently, in order to form a second pattern, a fine pattern as illustrated in FIG. 3 was formed by coating, baking, exposing, and developing a HAS4473 of Shin-Etsu Co., Ltd., an ArF resist, on the first pattern.

Example 2.

After coating, baking and exposing NTS4 of Sumitomos, an ArF resist for TSI, to the top of the hard mask nitride, a presilylation bake process was performed at 130 ° C. for 90 seconds. Then, tetramethyl disilazane was used to silylate the gas phase at 170 ° C. for 150 seconds. Subsequently, in the etching chamber, the wafer is placed in one step with fluorine / O ₂ / SO _2. It was etched in an etching chamber at -10 ° C using a mixed gas of. At this time, the silicon dioxide layer is formed in a portion where the chemical bond with tetramethyl disilazane in the non-exposed area. O ₂ / SO ₂ in the subsequent etching process The first pattern was formed by dry etching the non-exposed areas with the silicon dioxide layer as a barrier. Subsequently, to form a second pattern, a fine pattern as illustrated in FIG. 4 was formed by coating, baking, exposing, and developing a HAS4473 of Shin-Etsu Co., Ltd., an ArF resist, on the first pattern.

Example 3.

After coating, baking and exposing NTS4 of Sumitomo Co., Ltd., an ArF resist for TSI, onto the hardmask poly, the presilylation bake process was performed at 120 ° C. for 80 seconds. Then, hexamethyl disilazane was used to silylate the gas phase at 160 ° C. for 140 seconds. The wafer was then etched in an etch chamber at −15 ° C. using a mixed gas of fluorine / O ₂ / SO ₂ in one step. At this time, the silicon dioxide layer is formed in a portion that is chemically bonded to hexamethyl disilazane in the non-exposure region. O ₂ / SO ₂ in the subsequent etching process The first pattern was formed by dry etching the non-exposed areas with the silicon dioxide layer as a barrier. Subsequently, in order to form a second pattern, a fine pattern as illustrated in FIG. 5 was formed by coating, baking, exposing, and developing the SXM4096 of Shin-Etsu, an ArF resist, on the first pattern.

Example 4.

After coating, baking and exposing NTS4 of Sumitomos, an ArF resist for TSI, to the hardmask nitride, the presilylation bake process was performed at 140 ° C. for 70 seconds. Then, hexamethyl disilazane was used to silylate at 150 ° C. for 150 seconds. Subsequently, in the etching chamber, the wafer is placed in one step with fluorine / O ₂ / SO _2. It was etched in the etching chamber at -15 degreeC using the mixed gas of. At this time, the silicon dioxide layer is formed in a portion that is chemically bonded to hexamethyl disilazane in the non-exposure region. O ₂ / SO ₂ in the subsequent etching process The first pattern was formed by dry etching the non-exposed areas with the silicon dioxide layer as a barrier. Subsequently, in order to form a secondary pattern, a fine pattern as illustrated in FIG. 6 was formed by coating, baking, exposing, and developing the SXM4096 of Shin-Etsu, an ArF resist, on the first pattern.

Example 5.

After coating, baking and exposing NTS4 of Sumitomo Inc., an ArF resist for TSI, to the top of the hard mask nitride, a presilylation bake process was performed at 150 ° C. for 60 seconds. Then, tetramethyl disilazane was used to silylate the gas phase at 160 ° C. for 130 seconds. Subsequently, in the etching chamber, the wafer is placed in one step with fluorine / O ₂ / SO _2. It was etched in the etching chamber at -20 degreeC using the mixed gas of. At this time, the silicon dioxide layer is formed in a portion where the chemical bond with tetramethyl disilazane in the non-exposed area. O ₂ / SO ₂ in the subsequent etching process The first pattern was formed by dry etching the non-exposed areas with the silicon dioxide layer as a barrier. Subsequently, in order to form a secondary pattern, a fine pattern as illustrated in FIG. 6 was formed by coating, baking, exposing, and developing the SXM4096 of Shin-Etsu, an ArF resist, on the first pattern.

Example 6.

Shin-Etsu SXM4096, an ArF resist, was coated on the hardmask poly and baked, followed by exposure to form a fine pattern. After coating and baking the NTS4 of TSI ArF resist, Sumitomos Inc., after the exposure step, the presiliation baking process was performed at 120 ° C. for 80 seconds, followed by vapor phase at 160 ° C. for 140 seconds using nuxamethyl disilazane. Silicate as. The wafer was then etched in an etch chamber at −15 ° C. using a mixed gas of fluorine / O ₂ / SO ₂ in one step. At this point, the chemically bonded portion of the nucleated methyl disilazane in the non-exposed area is turned into a silicon dioxide layer. Subsequently, in the etching process of the second step, a second pattern was formed by dry etching the exposure area using a barrier layer of silicon dioxide with O ₂ / SO ₂ gas.

Example 7.

The hard mask nitride was coated with ArF resist HAS4473 Co., Ltd. HAS4473 and baked to form a fine pattern primarily through an exposure process. Subsequently, the NTS4 of Sumitomos, an ArF resist for TSI, was coated and baked, followed by an exposure step, followed by a presilicate baking process at 130 ° C. for 60 seconds, followed by vapor phase at 150 ° C. for 150 seconds using nuxamethyl disilazane. Silicate as. The wafer was then etched in an etching chamber at −20 ° C. using a mixed gas of fluorine / O ₂ / SO ₂ in one step. At this point, the chemically bonded portion of the nucleated methyl disilazane in the non-exposed area is turned into a silicon dioxide layer. Subsequently, in the etching process of the second step, a second pattern was formed by dry etching the exposure area using a barrier layer of silicon dioxide with O ₂ / SO ₂ gas.

Example 8.

On top of the hard mask nitride, ASR5076, an ArF resist, was coated and baked, followed by exposure to form a fine pattern. Subsequently, the NTS4 of Sumitomos, an ArF resist for TSI, was coated and baked, followed by an exposure step, followed by a presiliency baking process at 140 ° C. for 60 seconds, followed by vapor phase at 160 ° C. for 140 seconds using nuxamethyl disilazane. Silicate as. Thereafter, in the etching chamber, the wafer was etched in an etching chamber at −15 ° C. using a mixed gas of fluorine / O ₂ / SO ₂ in one step. At this point, the chemically bonded portion of the nucleated methyl disilazane in the non-exposed area is turned into a silicon dioxide layer. Subsequently, in the etching process of the second step, a second pattern was formed by dry etching the exposure area with a barrier of silicon dioxide layer using a gas of O ₂ / SO ₂ .

Preferred embodiments of the present invention are for the purpose of illustration, and those skilled in the art will be able to make various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, and such modifications may be made by the following claims. Should be seen as belonging to.

1A to 1H are cross-sectional views of a double patterning process to which silylation is applied during primary patterning.

2A to 2H are cross-sectional views of a double patterning process using sililation during secondary patterning.

3 to 7 are fine pattern photographs obtained in Examples 1 to 5, respectively.

<Description of the code>

11: semiconductor substrate

13: etched layer

13 ': Etch layer pattern

15: first photosensitive film

15 ': first photosensitive film pattern

17: silication film

19: silicon oxide film

21: second photosensitive film

21 ': second photosensitive film pattern

Claims (9)

A pattern forming method of a semiconductor device, comprising: applying a top surface imaging process during a double patterning process. The method according to claim 1, The top surface imaging process is a silicide process, characterized in that the pattern forming method of a semiconductor device. The method according to claim 1, The top surface imaging process is a pattern forming method of a semiconductor device, characterized in that applied to the first patterning process or the second patterning process in the double patterning process. The method of claim 1, wherein the pattern forming method Forming an etched layer on the semiconductor substrate; Forming a first photoresist film by applying a photoresist composition on the etched layer; Exposing the first photosensitive film; Silylating the exposed first photosensitive film to form a silylation film; Patterning the silylation film; Forming a first photoresist pattern by etching the first photoresist layer using the silicide film pattern as an etching mask; Forming a second photoresist layer pattern on the first photoresist layer pattern so as not to overlap the first photoresist layer pattern; And And etching the etched layer by using the first photoresist pattern and the second photoresist pattern as an etching mask. The method of claim 1, wherein the pattern forming method Forming an etched layer on the semiconductor substrate; Forming a first photoresist film by applying a photoresist composition on the etched layer; Exposing and developing the first photoresist film to form a first photoresist pattern; Forming a second photoresist layer on the first photoresist pattern; Exposing the second photosensitive film; Silylating the exposed second photosensitive film to form a silylation film; Patterning the silylation film; Forming a second photoresist pattern so that the second photoresist layer is etched using the silicide film pattern as an etch mask so as not to overlap the first photoresist pattern; And And etching the etched layer by using the first photoresist pattern and the second photoresist pattern as an etching mask. The method according to claim 4 or 5, The silylation process is a pattern forming method of a semiconductor device, characterized in that carried out in the liquid or gas phase for 30 to 300 seconds at a temperature of 90 to 250 ℃ using a silylating agent. The method according to claim 6, The silylating agents are hexamethyl disilazane, tetramethyl disilazane, bisdimethylamino dimethylsilane, bisdimethylamino methylsilane, dimethylsilyl dimethylamine, dimethylsilyl diethylamine, trimethylsilyl dimethylamine, trimethylsilyl diethylamine and dimethyl A method of forming a pattern of a semiconductor device, characterized in that it is selected from the group consisting of amino pentamethyldisilane. The method according to claim 4 or 5, And presilyling bake for 30 to 300 seconds at a temperature of 90 to 250 ° C. after the exposure after siliculation. The method according to claim 5, And forming an entire surface of the first photoresist pattern and then irradiating an E-beam to the first photoresist pattern before forming the second photoresist on the first photoresist pattern.

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