KR20090081687A - Dynamic logic circuit and inverter therof with multi-threshold cmos circuit - Google Patents

Abstract

A dynamic logic circuit having a MTCMOS(Multi-Threshold CMOS) circuit and an inverter thereof are provided to increase an operating speed and to reduce relatively constant power by forming transistors having one of at least two critical voltages. A dynamic logic circuit having a MTCMOS circuit includes a pre-charge transistor, an evaluation circuit(10), and an inverter(20). The pre-charge transistor is used for pre-charging a first node to a first voltage according to a first clock signal. The evaluation circuit is connected with the first node in order to receive the first clock signal and one or more logic input signal. The evaluation circuit is operated to induce a second voltage to the first node according to the first clock signal and the logic input signal. The inverter includes an input terminal connected to the first node and an output terminal connected to an output node. The inverter is installed between a first voltage node and a second voltage node in order to invert an input signal controlling a conducting state according to the second clock signal.

Description

DYNAMIC LOGIC CIRCUIT AND INVERTER THEROF WITH MULTI-THRESHOLD CMOS CIRCUIT}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dynamic logic circuit and an inverter of a dynamic logic circuit. The present invention relates to a dynamic logic circuit and a dynamic logic circuit having a multi-threshold CMOS (MTCMOS) circuit which can reduce the constant power consumption while increasing the operation speed. Relates to an inverter.

The two primary considerations in the design of integrated circuits are reduced power consumption and improved operating speed. In general, increasing the operating speed of a circuit increases power consumption. Likewise, reducing the power consumption of a circuit reduces operating speed.

Dynamic logic circuits are often used to increase the operating speed of integrated circuits. The dynamic logic circuit is precharged to the first voltage during the first phase of the clock signal, and optionally to the second voltage in response to one or more inputs of the dynamic logic circuit during the second phase of the clock signal. The circuit is discharged. In dynamic logic circuits, each input is configured to be connected to one transistor, which is generally contrasted with the use of two transistors to receive one input in a static logic circuit. In this way, the dynamic logic circuit can increase the operation speed by reducing the load on the input signal, and the discharge operation also proceeds relatively fast because the load on the circuit itself is small.

However, dynamic logic circuits have a disadvantage in that they typically consume more power than static circuits because they are designed to repeat precharge and discharge for a given clock cycle to represent various output states.

In addition, as a method for further improving the operation speed of a circuit in a dynamic logic circuit, a technique of lowering the threshold voltage of all the transistors constituting the circuit is known, but the low threshold voltage of the transistor causes an increase in leakage current and thus the standby power as a whole. There was a problem that increased consumption. Accordingly, there has been a demand for the development of a technology capable of maximizing the effect of speed improvement compared to power consumption by finding an optimal tradeoff between two conflicting factors such as an improvement in operating speed and a reduction in power consumption.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and by configuring the transistors constituting the dynamic logic circuit to have one of at least two threshold voltages, it is possible to increase the operation speed while relatively reducing the power consumption. It is an object of the present invention to provide a dynamic logic circuit having an MTCMOS (Multi-Threshold CMOS) circuit and an inverter of the dynamic logic circuit.

According to an aspect of the invention, a precharge transistor for precharging the first node to a first voltage according to the first clock signal; An evaluation circuit coupled to the first node and coupled to receive the first clock signal and one or more logic input signals, the evaluation circuit operative to induce a second voltage to the first node in accordance with the first clock signal and the logic input signal; And an input terminal connected to the first node and an output terminal connected to the output node, and installed between the first voltage node and the second voltage node, the conduction state is controlled according to the second clock signal, thereby inverting the input signal. Including an inverter for outputting, wherein the inverter,

A first transistor having a source connected to a first voltage node, a drain, and a gate connected to receive a second clock signal; A second transistor having a source connected to the drain of the first transistor, a gate connected to an input terminal of the inverter, and a drain connected to an output terminal of the inverter; A third transistor having a drain connected to an output terminal of the inverter, a gate connected to an input terminal of the inverter, and a source connected to a source of the fourth transistor; And a fourth transistor having a source connected to a source of a third transistor, a gate connected to receive the second clock signal, and a drain connected to a second voltage node, wherein the threshold voltage of the second transistor is the second voltage. There is provided a dynamic logic circuit having an MTCMOS circuit, which is configured to be lower than threshold voltages of the 1, 3, 4 transistors.

In the dynamic logic circuit, the first, second, and fourth transistors may be configured as PMOS transistors, and the third transistor may be configured as NMOS transistors, in which case the precharge transistor is a PMOS transistor, and the evaluation circuit is connected in series. It is preferable to configure one or more NMOS transistors. The precharge transistor and the transistor of the evaluation circuit may be configured to have substantially the same threshold voltage as the first, third and fourth transistors. Meanwhile, a power supply voltage is applied to the first voltage node and a ground voltage is applied to the second voltage node during use.

In the dynamic logic circuit, the first, second, and fourth transistors may be NMOS transistors, and the third transistor may be PMOS transistors. In this case, it is preferable that the precharge transistor is an NMOS transistor, and the evaluation circuit is a PMOS transistor. In addition, the precharge transistor and the transistor of the evaluation circuit may be configured to have substantially the same threshold voltage as the first, third, and fourth transistors, a ground voltage is applied to the first voltage node during use, and the The power supply voltage is configured to be applied to the two voltage node.

According to another aspect of the present invention, a dynamic logic having an input terminal and an output terminal, which is provided between a first voltage node and a second voltage node, and whose conduction state is controlled according to a clock signal, inverts and outputs the input signal. As an inverter in the circuit,

A first transistor having a source connected to the first voltage node, a drain, and a gate connected to receive a clock signal; A second transistor having a source connected to the drain of the first transistor, a gate connected to an input terminal of the inverter, and a drain connected to an output terminal of the inverter; A third transistor having a drain connected to an output terminal of the inverter, a gate connected to an input terminal of the inverter, and a source connected to a source of the fourth transistor; And a fourth transistor having a source connected to a source of a third transistor, a gate connected to receive the clock signal, and a drain connected to a second voltage node, wherein the threshold voltage of the second transistor includes: the first, An inverter of a dynamic logic circuit having an MTCMOS circuit configured to be lower than threshold voltages of three and four transistors is provided.

In the inverter of the dynamic logic circuit, the first, second, and fourth transistors may be configured as PMOS transistors, and the third transistor may be configured as NMOS transistors. In this case, a power supply voltage is preferably applied to the first voltage node and a ground voltage is applied to the second voltage node during use.

In the inverter of the dynamic logic circuit, the first, second, and fourth transistors may be configured as NMOS transistors, and the third transistor may be configured as PMOS transistors. At this time, a ground voltage is applied to the first voltage node and a power supply voltage is applied to the second voltage node during use.

According to the dynamic logic circuit including the MTCMOS circuit and the inverter of the dynamic logic circuit of the present invention, the circuit is provided with a high threshold voltage (high-V _T ) transistor and a low threshold voltage (low-V _T ) transistor in the circuit to prevent leakage of the circuit. The operation speed of the circuit can be improved without significantly increasing the current, thereby maximizing the effect of improving the operation speed of the circuit compared to power consumption.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention in more detail.

1 shows a configuration of a dynamic logic circuit according to an embodiment of the present invention.

In the embodiment of FIG. 1, the dynamic logic circuit includes transistors T1 to T9, wherein transistors T1, T5, T6, T8, and T9 are P-type MOS transistors (PMOS), and the remaining transistors are N-type MOS transistors (NMOS). It consisted of. However, the configuration is not particularly limited, and according to a specific embodiment, it is possible to achieve the same configuration and operation as the present invention by varying the number and / or type of transistors.

As shown in FIG. 1, the dynamic logic circuit according to the present invention may be largely divided into a precharge transistor unit, an evaluation circuit unit 10, and an inverter unit 20.

Specifically, the precharge transistor unit receives a first clock signal Clk1 at a gate, a source is connected to a voltage node to which a voltage Vdd is applied during use, and a drain is formed of a transistor T1 connected to a node N. In addition, a transistor T9 connected to the precharge transistor unit such that an output from an output node Out is applied to a gate, a source is connected to a voltage node to which a voltage Vdd is applied, and a drain is connected to a node N. It may be further provided.

The evaluation circuit unit 10 includes a series connection structure of NMOS transistors connected to the node N to receive the first clock signal Clk1 and one or more logic input signals A and B. For example, the evaluation circuit unit 10 may be configured of transistors T2 to T4 connected in series. At this time, the drain of the transistor T2 is connected to the node N, the source is connected to the drain of the transistor T3, the gate is connected to receive the first dynamic logic input signal (A). In addition, the source of transistor T3 is connected to the drain of transistor T4, the gate is connected to receive a second dynamic logic input signal B, the source of transistor T4 is connected to a voltage node to which a ground voltage is applied during use, and the gate May be connected to receive the clock signal Clk1.

The inverter unit 20 has an input terminal connected to the node N and an output terminal connected to the output node Out of the circuit, and between the voltage node to which the voltage Vdd is applied and the voltage node to which the ground voltage is applied during use. And a conduction state is controlled in accordance with the clock signal to invert and output the input signal. Specifically, the inverter unit 20 includes: a transistor T5 having a source connected to a voltage node to which a voltage Vdd is applied, a drain, and a gate connected to receive a second clock signal Clk2 during use; A transistor T6 having a source connected to the drain of the transistor T5, a gate connected to the input terminal of the inverter, and a drain connected to the output terminal of the inverter; A transistor T7 having a drain connected to the output terminal of the inverter, a gate connected to the input terminal of the inverter, and a source connected to the source of the transistor T8; And a transistor T8 having a source connected to the source of the transistor T7, a gate connected to receive the second clock signal Clk2, and a drain connected to a voltage node to which a ground voltage is applied during use.

In particular, in a dynamic logic circuit having a multi-threshold CMOS (MTCMOS) circuit according to the present invention, the transistor T6 is configured to have a threshold voltage lower than that of the transistors T5, T7, and T8. In addition, the transistors constituting the precharge transistor and the evaluation circuit section 10 are preferably configured to have substantially the same threshold voltage as the transistors T5, T7, and T8.

A general CMOS circuit is configured such that the threshold voltages of the transistors exhibit approximately the same values by changing the manufacturing process and operating conditions of the transistors. However, as described above, the dynamic logic circuit according to the present invention is characterized in that each transistor is configured to have one of at least two different threshold voltages. Here, a transistor having a relatively high threshold voltage will be referred to as a high threshold voltage (high-V _T ) transistor, and a transistor having a low threshold voltage will be referred to as a low threshold voltage (low-V _T ) transistor. In the present invention, it should be noted that the term "high threshold voltage" or "low threshold voltage" is merely used to indicate a value of a relative threshold voltage between transistors constituting a circuit, and does not indicate any absolute value. In the exemplary embodiments of the present invention, the low threshold voltage transistors, such as the transistor T6, are shown by dot in the center.

The operation of the dynamic logic circuit of FIG. 1 configured as described above is as follows.

First, when the first clock signal Clk1 is set to a level at which the transistor T1 connected thereto is conducted along its conductive path (source / drain), the circuit of FIG. 1 is in the precharge phase. That is, when the first clock signal Clk1 is at a low level, the transistor T1 is turned on, and the node N is precharged with a voltage approximately equal to the power supply voltage Vdd. Accordingly, the transistor T7 is turned on by the voltage Vdd of the node N. When the transistor T8 is turned on, the transistor T7 induces an approximately ground voltage to the output node Out. Transistor T9 is turned on by the ground voltage of the output node, and maintains node N at the precharge voltage in the absence of logic inputs A and B. For example, transistor T9 serves to cancel any effect that might be caused by leakage current at node N.

Next, when the first clock signal Clk1 is at a high level, the circuit is in an evaluation phase. In this case, the transistor T1 is turned off and the transistor T4 is turned on. During the evaluation phase, when there are logic inputs A and B at a high level or approximately supply voltage Vdd, transistors T2 through T4 operate to derive approximately ground voltage at node N. At this time, the transistor T9 has a relatively small current capacity when compared to the transistors T2 to T4, so that the node N is discharged. As node N is discharged, transistor T7 goes off and transistor T6 goes on. At this time, when the transistor T5 is in the on state, the transistor T6 draws a high level output near the power supply voltage Vdd to the output node Out. When the output node Out transitions to a high state, the transistor T9 is turned off.

In general, in CMOS circuits, the lower the threshold voltage of the transistors, the faster the circuit responds to changes in the gate voltage input of the transistor. That is, when the threshold voltage is low, since the voltage to be overcome before the flow of current starts is small, the transistor can quickly transition from the off state to the on state. On the other hand, the lower the threshold voltage of the transistors constituting the circuit, the more the leakage current of the transistor increases, causing a problem that the constant power consumption of the circuit becomes larger.

In the embodiment of FIG. 1 according to the present invention, the transistor T6 is configured as a low threshold voltage (low-V _T ) transistor and the remaining transistors are configured as a high threshold voltage (high-V _T ) transistor. As described above, the present invention is that since the majority of transistors in the circuit are made of high threshold voltage transistors, a standby mode, for example, a precharge phase or a circuit is normal when compared with a low threshold voltage transistor. There is an advantage that the leakage current of the circuit becomes relatively low in the state of being kept in the) state.

Further, in the present invention, the evaluation phase through transistors T2 to T4 and T6 and the transition to the high level of discharge and output node Out of node N are optimized for low power and high speed operation in dynamic logic circuits. It was noted that it could be a path that can be made. That is, according to the present invention, since the transistor T6 is configured as a low threshold voltage (low-V _T ) transistor, the transistor T6 responds to the discharge of the node N faster than the high threshold voltage (high-V _T ) transistor. Also, by connecting transistor T6 in series with the high threshold voltage transistor T5, the reduced leakage current inside transistor T5 will allow the circuit to operate at lower power, which will limit the leakage current in transistor T6. It becomes possible. Therefore, the dynamic logic circuit according to the present invention can exhibit fast response speed and low power consumption.

Meanwhile, in the embodiment of FIG. 1, the transistors T5, T6, T7, and T8 may be considered as inverter circuits having an input terminal connected to the node N and an output terminal connected to the output node Out. That is, when the second clock signal Clk2 is at a low level, the output of the inverter is represented as a logical inversion with respect to the input. For example, an input of about a high level or a power supply voltage Vdd represents an output of a low level or a ground voltage, and conversely, an output of a high level or a power supply voltage of an input of a low level or a ground voltage is represented. In particular, the series connection structure of transistors T6 and T7 consists of a low threshold voltage transistor and a high threshold voltage transistor, each having a different threshold voltage, thereby enabling fast logic operation while minimizing power consumption for the input. . However, when the second clock signal Clk2 is at a high level, the output signal does not appear inverted with respect to the input signal.

In general, the dynamic logic circuit has at least two modes of operation, an active mode and a standby mode. In the dynamic logic circuit of FIG. 1, transistors T2 to T4 of evaluation circuit section 10 will be used to evaluate logic inputs A and B in active mode and will not be used to evaluate the logic input in standby mode. Therefore, in the standby mode, the first clock signal Clk1 may be at a low level, and in the active mode, the first clock signal Clk1 may be at a high level. In addition, during the active mode, the second clock signal Clk2 keeps transistor T5 on and thus becomes a low level that can allow current to flow through transistor T6 when it is on. will be. On the other hand, in the standby mode, the second clock signal Clk2 will be at a high level in which the transistors T5 and T8 are turned off.

As described above, in the embodiment of FIG. 1, logic inputs A and B are applied to the gates of transistors T2 and T3, thereby discharging node N, resulting in charging of the output node Out. Thus, the circuit of FIG. 1 can be a dynamic logic circuit implementing the logic of A AND B. Meanwhile, instead of the series connection structure of transistors T2 and T3, the evaluation circuit unit 10 according to the present invention has a parallel connection structure in which one transistor receives a logic input A and the other transistor receives an input B. By configuring to be connected in series, it is also possible to implement the logic of A OR B. As such, the configuration of the evaluation circuit portion in the present invention may be made in parallel and / or series combination of various transistors that receive various inputs in order to perform a desired logic function for the input.

According to an exemplary embodiment, a beta ratio between T6 and T7 may benefit from transistor T6 to cause skew. Further, the embodiment may be configured such that in standby mode transistor T6 draws an output above Vdd to the output node and transistor T5 draws an output below ground (or Vss). In this case, the circuit may be a high speed circuit capable of reducing noise margin and slow reset of the output.

In addition, in FIG. 1, it is also possible to configure an embodiment such that a transistor receiving an input to a dynamic logic circuit, such as transistors T2 and T3, behaves like a low threshold voltage transistor. As such, various transistors may be configured to operate as a low threshold voltage or high threshold voltage transistor.

As described above, according to the dynamic logic circuit having the MTCMOS circuit according to the present invention, by providing the high threshold voltage transistor and the low threshold voltage transistor in the circuit, the operation speed of the circuit can be increased without significantly increasing the leakage current of the circuit. It is possible to maximize the effect of improving the operation speed of the circuit compared to the power consumption.

FIG. 2 illustrates a complementary circuit configuration of FIG. 1 as another embodiment of the present invention.

In the embodiment of FIG. 2, the precharge transistor unit may include a transistor T13 and a transistor T18. The transistor T13 is configured such that its gate is connected to receive the first clock signal Clk1, the drain is connected to the node N, and the source is connected to the ground voltage. The transistor T18 is connected to its gate such that an output from the output node Out is applied, the drain is connected to the node N, and the source is connected to the ground voltage.

In addition, the parallel structure of the transistors T11 and T12 and the transistor T10 connected in series with the parallel structure constitute an evaluation circuit section 10 '. The transistors T11 and T12 are connected to receive logic inputs A and B at their gates, and the transistor T10 is connected to receive a first clock signal Clk1 at their gates.

On the other hand, the inverter unit 20 'is made of a series connection structure of the transistors T14 to T17. As shown, the drain of the transistor T14 is connected to the Vdd voltage node, the gate is connected to receive the second clock signal Clk2, and the source is connected to the source of the transistor T15. The gate of the transistor T15 is connected to the node N, the drain is connected to the output node (Out). In addition, the gate of the transistor T16 is connected to the node N, the drain is connected to the output node (Out), the source is connected to the drain of the transistor T17. In addition, the source of the transistor T17 is connected to the ground voltage node, the gate is connected to receive the second clock signal (Clk2).

In the embodiment of FIG. 2, transistors T10, T11, T12, and T15 are PMOS transistors, and the remaining transistors are NMOS transistors.

In addition, the transistor T16 includes a low threshold voltage (low-V _T ) transistor having a threshold voltage lower than that of the transistors T14, T15, and T17, and the transistors constituting the remaining precharge transistor unit and the evaluation circuit unit 10 ′, It is preferable to configure a high threshold voltage (high-V _T ) transistor having approximately the same threshold voltage as the transistors T14, T15, and T17.

In the embodiment of FIG. 2, the precharge phase is when the first clock signal Clk1 is at a high level, and the evaluation phase is when the first clock signal is at a low level. When During the precharge phase, node N is prechred to ground voltage by transistor T13, and the precharge voltage of node N is maintained by transistor T18. The operation of transistors T13 and T18 is similar to transistors T1 and T9 in the embodiment of FIG. 1, respectively. In addition, during the evaluation phase, transistor T10 is turned on, and transistors T11 or T12 and T10 charge node N for low level logic inputs A and B. On the other hand, the transistors T14 to T17 can be considered as inverter circuits.

As discussed in the embodiment of Fig. 1, in the embodiment of Fig. 2, for example, it is possible to configure transistors T11 and T12 or other transistors of the evaluation circuit section as low threshold voltage transistors. In addition, in order to implement various logic equations, parallel, series, or a combination of parallel and series connection of various transistors may be applied to the evaluation circuit unit.

3 illustrates how the output changes during the precharge and evaluation cycles when the second clock signal Clk2 is set to a low level. When the FIG. 3 is applied to the timing diagram of FIG. 2, the precharge phase is when the first clock signal Clk1 is at a high level, and the evaluation phase is when the first clock signal is low. At low level. In addition, the inverter 20 'operates when the second clock signal CLK2 is at a high level.

4 also shows how the output changes during the precharge and evaluation cycles when the second clock signal Clk2 changes. As shown in FIG. 3 and FIG. 4, the first clock signal Clk1 and the second clock signal Clk2 input to the dynamic logic circuit of the present invention are asynchronous clock signals, and the first clock signal CLK1. The second clock signal CLK2 is input with a time difference with respect to the input of. For example, the second clock signal CLK2 is input after being delayed for a predetermined time from an input point of the first clock signal CLK1. This is to reduce current consumption such as charge sharing with the inverter 20 or blocking leakage current in the inverter during the operation of the evaluation circuit unit 10 or the precharge operation of the node N.

Since the first clock signal CLK1 and the second clock signal CLK2 are an asynchronous clock signal, the first clock signal CLK1 and the second clock signal CLK2 input to the circuit may have a low level '0'. Possible combinations of high level ('1') signals, with the four cases of '0' and '0', '0' and '1', '1' and '0', and '1' and '1', respectively. Can be entered.

Four cases will be described below.

First, when the first clock signal CLK1 has a low level '0' and the second clock signal CLK2 has a low level '0', the circuit includes the first clock signal CLK1. In response, the transistor T1 is operated to perform a precharge operation on the node N. FIG. In addition, since the transistors T5 and T8 operate in response to the second clock signal CLK2, an inverting operation of the precharge voltage Vdd of the node N is performed. The output Out according to the inverting operation operates the transistor T9 to compensate for the precharge voltage of the node N. That is, normal precharge operation is performed. In this case, since the node N is in the precharge state, the output Out always has a low level regardless of the input levels of the logic input signals A and B.

In this case, since the transistors T5, T7, and T8 are high threshold voltage transistors, the leakage current of the node N can be relatively reduced.

Next, a case in which the first clock signal CLK1 has a low level '0' and the second clock signal CLK2 has a high level '1' will be described.

In this case, the transistor T1 is operated in response to the first clock signal CLK1 to perform a precharge operation on the node N. FIG. However, since the second clock signal CLK2 has a high level, the transistors T5 and T8 do not operate and thus the inverter 20 does not operate. At this time, the operation of the transistor T9 is unclear, but if the output Out is already at the low level, the transistor T9 may operate to compensate for the leakage current of the node N. . At this time, since the node N is in the precharge state and the inverter 20 does not operate, the output Out is at a previous low level (the level of the precharge state) regardless of the input levels of the logic input signals A and B. Will have

In this case, since the transistor T7 is a high threshold voltage transistor, the leakage current of the node N can be relatively reduced. In addition, since the transistors T5 and T8 do not operate, the leakage current through the current path of the inverter 20 may be blocked.

Next, a case where the first clock signal CLK1 is at a high level ('1') and the second clock signal CLK2 is at a low level ('0') will be described.

At this time, the transistor T4 of the evaluation circuit unit 10 is operated by the first clock signal CLK1, and the level of the node N changes depending on the states of the logic inputs A and B. FIG. For example, when implemented as an AND circuit as shown in FIG. 1, the node N is discharged to a low level only when the logic inputs A and B are all input at a high level. If the logic inputs A and B are not all input at the high level, the node N will maintain the high level. In addition, since the second clock CLK2 has a low level, the inverter 20 performs a normal inverting operation. That is, when the logic inputs A and B are all input at the high level, the output Out is at the high level, and in other cases, the output Out is at the low level.

In this case, since the transistor T6 is a low threshold voltage transistor, even if the discharge level of the node N is slightly high, the transistor T6 operates. In addition, since the transistors T5, T7, and T8 are high threshold voltage transistors, there is an advantage that the leakage current can be relatively small.

Finally, the case where the first clock signal CLK1 has a high level '1' and the second clock signal CLK2 has a high level '1' will be described.

At this time, the transistor T4 of the evaluation circuit unit 10 is operated by the first clock signal CLK1, and the level of the node N changes depending on the states of the logic inputs A and B. FIG. For example, when implemented as an AND circuit as shown in FIG. 1, the node N is discharged to a low level only when both logic inputs A and B are input at a high level. If the logic inputs A and B are not all input at the high level, the node N will maintain the high level. However, since the second clock CLK2 has a high level, the inverter 20 does not perform normal operation. In this case, the output Out may maintain the previous level state.

In this case, since the transistor T7 is a high threshold voltage transistor, the leakage current of the node N can be relatively reduced. In addition, since the transistors T5 and T8 do not operate, the leakage current through the current path of the inverter 20 may be blocked.

As a result, as shown in the four cases, even if the level of the first clock signal CLK1 and the second clock signal CLK2 has any state, the circuit operates in a direction of reducing power consumption.

In the above, the present invention has been shown and described with respect to certain preferred embodiments. However, the present invention is not limited to the above-described embodiment, and those skilled in the art to which the present invention pertains can variously change variously without departing from the technical spirit of the present invention described in the following claims. You can do it.

1 illustrates a dynamic logic circuit in accordance with an embodiment of the present invention;

FIG. 2 shows a complementary circuit of FIG. 1;

3 is a view illustrating a change in output when the second clock signal Clk2 is at a low level in the embodiment of FIG. 1;

4 is a view illustrating a change in output according to a change in the second clock signal Clk2 in the embodiment of FIG. 1.

Claims (20)

A precharge transistor for precharging the first node to a first voltage according to the first clock signal; An evaluation circuit coupled to the first node and coupled to receive the first clock signal and one or more logic input signals, the evaluation circuit operative to induce a second voltage to the first node in accordance with the first clock signal and the logic input signal; And It has an input terminal connected to the first node and an output terminal connected to the output node, and is installed between the first voltage node and the second voltage node, the conduction state is controlled in accordance with the second clock signal to output the inverted input signal Is provided with an inverter, the inverter, A first transistor having a source connected to a first voltage node, a drain, and a gate connected to receive a second clock signal; A second transistor having a source connected to the drain of the first transistor, a gate connected to an input terminal of the inverter, and a drain connected to an output terminal of the inverter; A third transistor having a drain connected to an output terminal of the inverter, a gate connected to an input terminal of the inverter, and a source connected to a source of the fourth transistor; And A fourth transistor having a source connected to a source of a third transistor, a gate connected to receive the second clock signal, and a drain connected to a second voltage node, The threshold voltage of the second transistor is configured to be lower than the threshold voltages of the first, third and fourth transistors. According to claim 1, Wherein the first, second, and fourth transistors are PMOS transistors, and the third transistor is an NMOS transistor. The method of claim 2, The precharge transistor is a PMOS transistor, Wherein said evaluation circuit comprises one or more NMOS transistors connected in series. The method of claim 3, wherein And the transistors of the precharge transistor and the evaluation circuit have substantially the same threshold voltage as the first, third and fourth transistors. The method of claim 4, wherein A dynamic logic circuit with an MTCMOS circuit, wherein a power supply voltage is applied to the first voltage node and a ground voltage to the second voltage node during use. According to claim 1, Wherein the first, second, and fourth transistors are NMOS transistors, and the third transistor is a PMOS transistor. The method of claim 6, The precharge transistor is an NMOS transistor, And said evaluation circuit comprises a PMOS transistor. The method of claim 7, wherein And the transistors of the precharge transistor and the evaluation circuit have substantially the same threshold voltage as the first, third and fourth transistors. The method of claim 8, And a ground voltage is applied to said first voltage node and a power supply voltage to said second voltage node during use. An inverter of a dynamic logic circuit having an input terminal and an output terminal, provided between a first voltage node and a second voltage node, the conduction state is controlled according to a clock signal, and inverting and outputting an input signal. A first transistor having a source connected to the first voltage node, a drain, and a gate connected to receive a clock signal; A second transistor having a source connected to the drain of the first transistor, a gate connected to an input terminal of the inverter, and a drain connected to an output terminal of the inverter; A third transistor having a drain connected to an output terminal of the inverter, a gate connected to an input terminal of the inverter, and a source connected to a source of the fourth transistor; And A fourth transistor having a source connected to a source of a third transistor, a gate connected to receive the clock signal, and a drain connected to a second voltage node, The threshold voltage of the second transistor is configured to be lower than the threshold voltages of the first, third and fourth transistors. An inverter of a dynamic logic circuit having an MTCMOS circuit. The method of claim 10, And the first, second, and fourth transistors are PMOS transistors, and the third transistors are NMOS transistors. The method of claim 11, wherein A power supply voltage is applied to said first voltage node and a ground voltage is applied to said second voltage node during use. The method of claim 10, And wherein the first, second, and fourth transistors are NMOS transistors, and the third transistors are PMOS transistors. The method of claim 13, An inverter of a dynamic logic circuit having an MTCMOS circuit, wherein a ground voltage is applied to the first voltage node and a power supply voltage is applied to the second voltage node during use. A precharge transistor for precharging the first node to a first voltage according to the first clock signal; An evaluation circuit coupled to the first node and coupled to receive the first clock signal and one or more logic input signals, the evaluation circuit operative to induce a second voltage to the first node in accordance with the first clock signal and the logic input signal; And An input terminal connected to the first node and an output terminal connected to the output node, the transistor having a threshold voltage different from each other between the first voltage node and the second voltage node, and a conductive state of the transistor according to the second clock signal Is controlled to have an inverter for inverting and outputting an input signal, And the first clock signal and the second clock signal are asynchronous clock signals. The method of claim 15, wherein the inverter, A first transistor having a source connected to a first voltage node, a drain, and a gate connected to receive a second clock signal; A second transistor having a source connected to the drain of the first transistor, a gate connected to an input terminal of the inverter, and a drain connected to an output terminal of the inverter; A third transistor having a drain connected to an output terminal of the inverter, a gate connected to an input terminal of the inverter, and a source connected to a source of the fourth transistor; And A fourth transistor having a source connected to a source of a third transistor, a gate connected to receive the second clock signal, and a drain connected to a second voltage node, The threshold voltage of the second transistor is configured to be lower than the threshold voltages of the first, third and fourth transistors. The method of claim 16, And the first clock signal and the second clock signal are at a low level. The method of claim 16, And said first clock signal is at a low level and said second clock signal is at a high level. The method of claim 16, And wherein the first clock signal is at a high level and the second clock signal is at a low level. The method of claim 16, And the first clock signal and the second clock signal are at a high level.

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