JP2024056139A - D-type flip-flop - Google Patents

Abstract

[Problem] A static D-type flip-flop is realized that achieves both low clock signal load for low power consumption and high speed surpassing that of conventional circuits. [Solution] By driving N-channel FETs 12, 12a and 19, 19a, whose gate terminals are connected to nodes 1, 1a, which are connected to a power supply via a clocked FET 16 and non-clocked FETs 15, 15a, both of which are P-channel and connected in series at node 2, and to ground via N-channel non-clocked FETs 11, 11a, respectively, writing to a cross-coupled inverter pair 50 via pass transistors 14, 14a of the N-channel clocked FETs is accelerated. In addition, if nodes 1, 1a are at a low level when the clock signal rises, the low level is maintained by N-channel feedback FETs 13, 13a and clocked FET 18 during the high level period of the clock signal, thereby suppressing an increase in leakage current. [Selected Figure] Fig. 12

Description

The present invention relates to a static D-type flip-flop (hereinafter referred to as DFF) with a low clock signal load that contributes to reducing the power consumption of CMOS LSIs.

DFFs are one of the most frequently used basic logic circuits, and because the individual circuits consume a lot of power, they account for a significant proportion of the power consumption in the logic section of CMOS LSIs. For this reason, DFFs with low clock signal loads, such as ACFFs, TCFFs, LLFFs [see Non-Patent Document 1] and LRFFs [see Non-Patent Document 2], have been proposed to reduce the clock signal load, which accounts for a large proportion of power consumption inside the DFFs.

For example, the LRFF shown in Figure 1 uses an inverter with a half-latch function (corresponding to the clocked CMOS inverter described in paragraph 0007) with a node that can only hold a low level (hereinafter referred to as a half-latch node) instead of a transparent static latch, which allows it to achieve a low clock signal load with four gate terminals for the clock signal input and a configuration with only 19 field effect transistors (FETs). However, in terms of speed performance, it has a weakness that is inferior to the transmission gate flip-flop (hereinafter referred to as TGFF) consisting of inverters and pass transistors that has been the mainstream up until now. This is because the drive of pass transistor 14 and inverter 24 from the power supply (Vdd) side relies on three series P-channel FETs, including P-channel FETs 161 and 31 that are in the process of switching off under the worst case conditions.

Here, a transparent static latch is a circuit that switches between a latched state in which it holds the input at the time of switching to that state and continues to output, and a transparent state in which it passes the input to itself and continues to output, depending on the logic level of the clock signal, and is also called a static D latch. In addition, the reason why it has to rely on the P-channel FETs 161 and 31 in the middle of switching off when driven from the Vdd side is to prevent through current from occurring even if the P-channel rear-stage latch driving FET (hereinafter referred to as the rear-stage driving FET) 151, whose gate terminal is connected to the output node of the first-stage inverter with half-latch function, which only holds a low level in the latched state, turns on in the middle of the latched state. The reason why the P-channel rear-stage driving FET 151 can turn on in the middle of the latched state is because the output of the first-stage inverter with half-latch function cannot hold a high level, so it falls to the low level as soon as the D signal input switches from low to high. Furthermore, although series generally means that FETs with the same channel polarity are connected together with their drains and sources facing each other, in the following, as long as the channel polarity is the same, it will also be described as series when the drain of one FET faces the sources of multiple FETs, or when the source of one FET faces the drains of multiple FETs. Note that when the term "connected" is used, it includes not only series connection, but also the case where FETs with opposite channel polarities are connected with their drains facing each other.

DFFs with low clock signal loads other than this LRFF also have problems such as inferior speed performance to TGFFs, and the circuit of the LSSD type scan flip-flop becomes complicated, compromising the small number of constituent FETs, although the reasons for each are different. In this situation, the only solution to these problems is a two-stage DFF that connects a pair of front-stage latches with a split output configuration of True Single-Phase Clock type (hereinafter abbreviated as TSPC) and a rear-stage latch consisting of a pair of pass transistors of clocked FETs that connect one of their own input/output terminal pairs to one of the cross-coupled inverter pairs and the cross-coupled node pair [see Non-Patent Document 3]. Here, a clocked FET is a FET whose gate terminal receives a clock signal as an input.

Figure 2 is a circuit diagram of one form of the two-stage DFF, where 1 and 1a are first nodes of the half latch node, 2 and 2a are second nodes of the half latch node, 3 and 4 are output nodes of the previous stage latch, 5 and 5a are cross-coupled node pairs of the cross-coupled inverter pair 50, 11 and 11a are N-channel source-grounded FETs, 12 and 12a are N-channel source-grounded rear-stage driving FETs, 14 and 14a are N-channel clocked FETs operating as pass transistors, 15 and 15a are P-channel source-grounded FETs, 16 and 16a are P-channel clocked FETs, and 20 and 20a are P-channel source-grounded rear-stage driving FETs. Also, 25 and 26 are inverters, which are cross-coupled to each other to form the cross-coupled inverter pair 50 of the memory circuit. 27 is an inverter for inverting the input signal (D signal) of the D terminal 41, and 28 is a buffer inverter for output to the QB terminal 42. Furthermore, 51 and 51a are clocked CMOS inverters of the simplest clocked CMOS logic circuits, consisting of 11, 15, and 16, and 11a, 15a, and 16a, respectively, and a clock signal is input from the clock (CLK) terminal 40 to the gate terminals of the clocked FETs 16 and 16a.

The clocked CMOS logic circuit under consideration here is a logic circuit with a half-latch function that limits the number of clocked FETs inserted in the drive current path of the output node to one. As is clear from the configuration of 51 and 51a, specifically, if the clocked FET is a P-channel, the logic circuit forms a Vdd-side drive current path with the clocked P-channel FET and a P-channel FET connected in series to it whose gate terminal is not clocked (not clocked) and a ground (GND)-side drive current path with a non-clocked N-channel FET, respectively, to the half-latch node (1, 1a). Alternatively, the logic circuit forms a Vdd-side drive current path with a non-clocked P-channel FET, and a GND-side drive current path with a connected clocked P-channel FET and non-clocked N-channel FET, respectively, to the half-latch node (2, 2a). On the other hand, if the clocked FET is N-channel, then the logic circuit forms a GND drive current path with the clocked N-channel FET and a non-clocked N-channel FET connected in series with it, and a Vdd drive current path with a non-clocked P-channel FET, respectively, to the half-latch node. Alternatively, the logic circuit forms a GND drive current path with a non-clocked N-channel FET, and a Vdd drive current path with the connected clocked N-channel FET and non-clocked P-channel FET, respectively, to another half-latch node. Of these clocked CMOS logic circuits, the clocked CMOS inverter is the simplest, because the non-clocked FETs are composed of one P-channel FET and one N-channel FET.

As shown in Figure 2, this DFF is configured so that the pair of rear-stage driver FETs 12, 20 and 12a, 20a drive the cross-coupled nodes 5, 5a via the clocked FETs 14, 14a of the pass transistors of the rear-stage latch, respectively, to write to the pair of cross-coupled inverters. With this configuration, the DFF operates as a master-slave type DFF in which the held D signal or the inversion of the D signal is transferred (written) to the rear-stage latch during the hold period. Here, the hold period is the period from the time when the clock signal rises from low to high (when the DFF state in which the front-stage latch is transparent and the rear-stage latch is latched [hereinafter referred to as the transparent latch state] changes to the DFF state in which the front-stage latch is latched and the rear-stage latch is transparent [hereinafter referred to as the latch transparent state or simply the latch state when referring to the front-stage latch]) until the hold time of the D signal input has elapsed. In addition, the rear-stage driver FET pairs 12, 20 and 12a, 20a are output drivers for the front-stage latch for D signal input consisting of elements with numbers not including an a (hereafter referred to as the front-stage latch without an a) in the TSPC split output configuration, and the front-stage latch for D signal inverted input consisting of elements with numbers including an a (hereafter referred to as the front-stage latch with an a).

When the clock signal is at low level, the D signal and the signal inverted by the inverter 27 are input to the front-stage latch without a and with a, respectively, and the D signal appears at the first and second nodes 1a and 2a of the clocked CMOS inverter, and its inversion appears at 1 and 2, respectively. This is because the clocked CMOS inverters 51 and 51a operate simply as inverters when the first clocked FET is on. When the clock signal rises from low level to high level, the first clocked FETs 16 and 16a are turned off and this DFF moves to the latch transparent state, if the logic level at that time is low, the first nodes 1 and 1a continue to hold the low level, but if it is high, they cannot continue to hold it and drop to low as soon as the D signal input switches. Similarly, if the logic level at that time is high, the second nodes 2 and 2a continue to hold the high level, but if it is low, they cannot continue to hold it and rise to high as soon as the D signal input switches. This is because the first and second nodes 1, 1a, 2, 2a are all half-latch nodes that can only hold one side of the logic level. Therefore, the post-drive FET pairs 12, 20 and 12a, 20a output high and low levels, respectively, in a complementary manner, only while the D signal input after the transition to the latch transparent state is maintained. Then, this output writes and drives the cross-coupled inverter pair via the N-channel FETs 14, 14a of the first and second pass transistors that turn on in the latch transparent state. In other words, while the D signal input or its inverted input just before the transition to the latch transparent state is maintained, the inverted signals are held at the first and second nodes 1, 1a, 2, 2a and written to the cross-coupled inverter pair. Due to this non-permanent write drive limited to the hold period, it is necessary to extend the hold time of the D signal input until the write is completed. However, since the write time is very short, the extension of the hold time does not impair the advantages of this DFF. In addition, the written data will not be destroyed after the hold time has elapsed and the D signal has switched. This is because when the D signal input switches, all of the rear-stage drive FETs 12, 12a, 20, and 20a turn off, and the driving capability for the rear-stage latch is lost.

Here, the reason why all of the post-stage driving FETs 12, 12a, 20, and 20a are turned off is because the first and second nodes 1, 2, 1a, and 2a do not hold the logic level that turns them on, but can only continue to hold the logic level that turns them off. In other words, the post-stage driving FETs 12, 12a, 20, and 20a do not include FETs with channel polarity that turn on at the logic level that can be continued to be held at the first and second nodes 1, 2, 1a, and 2a. However, the holding of the logic level that turns off the source-grounded post-stage driving FETs at the first and second nodes 1, 2, 1a, and 2a is dynamic due to the charge accumulated in the parasitic capacitance of the first and second nodes 1, 2, 1a, and 2a, which become high impedance, so it is not guaranteed to last forever (dynamic half-latch node). For this reason, if the latched period of the previous stage latch is extended, the logic level that turns it off may shift to the logic level that turns it on due to leakage current or noise, and the basic requirement of a CMOS circuit that either the P-channel or N-channel FET must be off may no longer be met. As a result, not only may the leakage current become excessive or a shoot-through current flow out, but in some cases, the written contents may be destroyed.

Therefore, a DFF with a TSPC split output latch configuration as the latch preceding this cross-coupled inverter pair can only be used to the extent that the increase in leakage current during the high-level period of the clock signal can be ignored, in other words, it can only be used as a semi-static DFF that can limit the high-level period of the clock signal to a short period. Semi-static DFFs not only impose design restrictions compared to static DFFs, but also have problems such as being an obstacle to quality selection tests and being prone to causing leakage current increases and malfunctions when the potential of high-impedance nodes that are held for half a clock cycle due to parasitic capacitance is affected by noise. For this reason, their use has not become widespread, despite the fact that they combine top-level low clock signal load with high-speed operation.

A. Khorami, M. Sachdev, and M. Sharifkhani, “A contention-free, static, single-phase flip-flop for low data activity applications,” in 2019 32nd IEEE International System-on-Chip Conference (SOCC), pp.11-16, 2019. J. Lin, M. Sheu, Y. Hwang, C. Wong and M. Tsai, “Low-Power 19-Transistor True Single-Phase Clocking Flip-Flop Design Based on Logic Structure Reduction Schemes,” in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 25, no. 11, pp.3033-3044, 2017. Tomoyuki Nakabayashi, Takahiro Sasaki, Kazuhiko Ohno, Toshio Kondo, "Proposal and Evaluation of Semi-static TSPC DFF Using Split-output Latch", IEICE Technical Report, Vol.VLD2010-125, 2010.

The problem that this invention aims to solve is to realize a static DFF that combines three characteristics: a low clock signal load that helps reduce power consumption, high speed comparable to a TGFF, and sufficient noise resistance.

By combining the retention and persistence of only one of the logic levels with subsequent drive (non-persistent drive) limited to the logic level side where the retention is not persistent, the logic level that cannot be written and driven does not shift to the side that can be written and driven while in the latched state, preventing the contents written with non-persistent drive during the hold period from being destroyed by overwriting. This also prevents an increase in leakage current and the occurrence of through current after the hold period.

The latch in the previous stage is not configured as a completely transparent static latch in which the write drive capability for the subsequent stage is persistent in the latched state, as in the case of conventional master-slave DFFs. This is because it would be difficult to achieve both low clock signal load and high-speed operation.

In addition, depending on the requirements for noise resistance, it can make it difficult for noise to cause a decrease in the driving ability of the subsequent stage, and it can delay or prevent the half latch node from becoming high impedance, which is sensitive to noise, while holding the logic level of the side that cannot be permanently held.

The most important feature of this invention is to adopt the following 16 measures based on the above ideas.

(1) A configuration in which two stages, a front-stage and a rear-stage latch, are linked, and at least one of the front-stage latches is configured with a static half-latch node in which retention in the latched state persists at only one of the logical levels, and one or more rear-stage drive FETs that do not include a FET that is turned on at the persistent logical level (only a FET that is turned off at the persistent logical level and turned on at the other non-persistent logical level), thereby forming a non-persistent drive latch in which write drive to the rear-stage latch does not persist in the latched state. The rear-stage latch is configured with a cross-coupled inverter pair and a clocked FET pass transistor that connects one of its own input/output terminal pairs to one of the cross-coupled node pairs.

(2) The static half-latch node is realized by making the dynamic half-latch node static by adding a feedback FET with the same channel polarity as the source-grounded rear-stage driving FET, which connects its gate terminal to the drain terminal of the first rear-stage driving FET, which is a source-grounded FET among the rear-stage driving FETs, and connects its drain terminal to the half-latch node.

(3) Write drive for the cross-coupled inverter pair is performed via two pass transistors, first and second, that connect one of the input/output terminal pairs to each of the cross-coupled node pairs of the cross-coupled inverter pair.

(4) A split output configuration in which the gate terminals of the first and second rear-stage driving FETs, each of which has its source grounded, are connected to two half-latch nodes driven by a first clocked FET, a non-clocked FET having the same channel polarity as the first clocked FET (hereinafter abbreviated as the first same channel) and a non-clocked FET having the opposite channel polarity (hereinafter abbreviated as the first opposite channel), specifically, a first node connecting the drain terminals of the first clocked FET and the non-clocked first opposite channel FET in the driving circuit, and a second node connecting the source terminal of the first clocked FET and the drain terminal of the non-clocked first same channel FET, is one configuration of a non-persistent driving latch.

(5) The drain terminal of the first or second rear-stage driving FET with a source ground of one of the two non-persistent drive latches and the drain terminal of the first or second rear-stage driving FET with a source ground of the other non-persistent drive latch are connected to the other of the input/output terminal pair of the first pass transistor and the other of the input/output terminal pair of the second pass transistor, respectively.

(6) The gate terminal and drain terminal of the first reverse channel common-source FET are connected to a first node of one of the two non-persistent drive latches having a split output configuration and a second node of the other non-persistent drive latch having a split output configuration, respectively. In addition, the gate terminal and drain terminal of another common-source FET of the first reverse channel are connected to a first node of the other of the two non-persistent drive latches having a split output configuration and a second node of the other non-persistent drive latch having a split output configuration, respectively.

(7) The drain terminal and gate terminal of a first common-channel source-grounded FET are connected to a first node of one of the two non-persistent drive latches having a split output configuration and a second node of the other non-persistent drive latch having a split output configuration. In addition, the drain terminal and gate terminal of another common-source FET of the first common channel are connected to a first node of the other of the two non-persistent drive latches having a split output configuration and a second node of the one non-persistent drive latch having a split output configuration.

(8) In a configuration in which a non-persistent drive latch with a split output configuration drives a subsequent latch by itself for writing, the drain terminal of a first subsequent drive FET with a common source whose gate terminal is connected to a first node is connected to the other of the input/output terminal pair of the first pass transistor, and the source terminal of a third subsequent drive FET with a common drain, which is one of the subsequent drive FETs with a gate terminal connected to the first node, is connected to the other of the input/output terminal pair of the second pass transistor.

(9) Another configuration of a non-persistently driven latch is a normal output configuration in which a first rear-stage driving FET is connected to a half-latch node driven by a first clocked FET, a first non-clocked same-channel FET, and a first non-clocked opposite-channel FET, specifically, a first node connecting the drain terminals of non-clocked FETs with different channel polarities in this driving circuit.

(10) The gate terminal and drain terminal of the first common-channel source-grounded FET are connected to the drain terminal of the first common-channel source-grounded subsequent-stage driving FET of one of the two non-persistent drive latches having a normal output configuration, and the drain terminal of the first common-channel source-grounded subsequent-stage driving FET of the other non-persistent drive latch having a normal output configuration, as well as the drain terminal and gate terminal of the other common-channel source-grounded FET.

(11) The source terminals of a first non-clocked same-channel FET, the drain terminal of each of which is connected to a first node of two non-persistently driven latches having a normal output configuration, are both connected to the drain terminal of a first clocked FET whose source is grounded.

(12) The source terminal of the drain-grounded third rear-stage driving FET of one of the two non-persistent drive latches having a normal output configuration is connected to the other of the input/output terminal pair of the second pass transistor, and the source terminal of the drain-grounded third rear-stage driving FET of the other non-persistent drive latch having a normal output configuration is connected to the other of the input/output terminal pair of the first pass transistor.

(13) Two first same-channel series-connected FETs are connected in parallel to a first clocked FET shared between two non-persistent drive latches of normal output configuration, with the drain and source terminals of the FET not used in the series connection being connected to the drain and source terminals of the other FET, respectively. Here, the gate terminals of the two series-connected FETs are connected to the drain terminal of the first back-stage drive FET of one of the two non-persistent drive latches of normal output configuration, and to a cross-coupled node driven by the first back-stage drive FET of the source-grounded non-persistent drive latch of the other non-persistent drive latch of normal output configuration via a pass transistor.

(14) Add a second clocked FET with the same channel polarity as the feedback FET and a common source that connects its drain terminal to the source terminal of the feedback FET of each of the two non-persistent drive latches.

(15) The drain and source terminals of a first same-channel FET that is not clocked and is connected in series with a first clocked FET are connected to the source and drain terminals of a first opposite-channel FET, the gate terminal of which receives the inverse of the signal input to the gate terminal of the first same-channel FET.

(16) A delayed clock signal, the phase of which is delayed from the clock signal input to the gate terminal of the pass transistor via the write drive for the cross-coupled inverter pair, is input to the gate terminal of the clocked FET in the non-persistent back-drive latch.

The DFF of the present invention has the advantage that, while it has a half-latch node-based configuration that allows the preceding latch to minimize the clock signal load, it operates as a completely static DFF in which leakage current does not increase or the written contents are not destroyed even if the latch transparent state in which the first clocked FET is off continues. This is because the means described in paragraph 0018 (1) prevents the subsequent driving FET, which is off when switching to the latch transparent state, from floating to the on side. Also, even if a logic level that cannot be permanently held switches to the other logic level after the hold period, the subsequent driving FET will not turn on and destroy the contents of the subsequent latch.

In addition, by using the method described in paragraph 0019 (2) to make a dynamic half-latch node into a static half-latch node, that is, by replacing each of the first and second rear-stage driving FETs with a feedback-equipped common-source FET in the split-output configuration non-persistent driving latch used in FIG. 2, a non-persistent driving latch with a static half-latch node is realized. In this non-persistent driving latch, whether the first or second node of the half-latch node is at high or low level when switching to the latch transparent state, either the first or second rear-stage driving FET whose gate terminal is connected to the respective node turns on, enabling driving of the rear stage. This makes it possible to configure the front-stage latch with a single non-persistent driving latch, which has the advantage of reducing the number of FETs in the configuration.

Furthermore, in the case of adopting a configuration in which the non-persistent drive latch is duplicated as in the semi-static DFF shown in Figure 2, the first and second clocked FETs are each combined into one by the means in paragraph 0028 (11) and paragraph 0031 (14), thereby reducing the number of gate terminals that act as a load on the clock signal, which is the main cause of power consumption, by up to two.

In addition, by using the method described in paragraph 0025 (8) to configure the rear-stage driving FET with a first source-grounded and a third drain-grounded rear-stage driving FET, in a configuration in which the non-persistent driving latch is not duplicated, there is an advantage that it is not necessary to drive the other of the input/output terminal pair of the second pass transistor with the first same-channel source-grounded FET, which generates subthreshold leakage current when its gate terminal is connected to the output node of the non-persistent driving latch. This is because the other of the input/output terminal pair of the second pass transistor is driven by the drain-grounded third rear-stage driving FET, whose gate terminal is connected to the first node.

Another advantage is that it can achieve a delay between input and output that is comparable to that of a TGFF. This is because not only can the number of series stages of P-channel FETs that form the drive current path of the half-latch node from the Vdd side be reduced from three to two by the means of paragraphs 0021(4) and 0028(11), but also the number of inversions of the propagation signal from the input to the output of the speed determining factor can be effectively reduced by the means of paragraphs 0018(1) and 0020(3) in which the post-stage driving FET writes and drives the cross-coupled inverter pair via the pass transistor in paragraph 0022(5), the means of duplicating the non-persistent driving latch in paragraphs 0025(8) or 0029(12) in which the input/output terminal of the pass transistor that is not driven by the first post-stage driving FET with a grounded source is driven by a third post-stage driving FET with a grounded drain in paragraph 0032(15), and the means of connecting a first opposite-channel FET with a grounded drain in parallel to the first same-channel FET that is not clocked and connected in series with the first clocked FET in paragraph 0032(15), etc.

In addition, the measures described in paragraphs 0023 (6), 0024 (7), 0026 (9), 0027 (10), 0030 (13), and 0033 (16) have the advantage of ensuring sufficient noise resistance while using circuits in which the half-latch node can become high impedance and sensitive to noise when in the latched state. The five noise resistance improvements achieved by these measures are described below.

First, the measures described in paragraphs 0023(6) and 0024(7) make it difficult for noise to disrupt the write drive. This is because the half-latch node is driven even during the hold period and does not become high impedance, making it less susceptible to electrostatic induction noise.

Secondly, by using the means of 0026(9), the half-latch node related to the next stage drive can be the first node only, which is not affected by positive electrostatic induction noise, so that resistance to positive electrostatic induction noise is sufficiently ensured. This eliminates the effects of positive electrostatic induction noise caused by the rising edge of the clock signal that appears in the first half of the hold period, which is the timing most sensitive to noise. Since negative electrostatic induction noise caused by the falling edge of the clock signal is not generated within the DFF cell during the hold period, ultimately, operation is not disturbed by noise caused by the clock signal, which is one of the main noises within the cell. In addition, for noise other than the clock signal, if the layout within the DFF cell is appropriately performed and clock skew is appropriately suppressed to prevent extra-cell noise from occurring in the first half of the hold period, which is sensitive to noise, then this means alone can prevent malfunctions due to noise.

The third advantage is that the write drive is less likely to be disturbed by noise due to the measures described in paragraph 0027 (10). This is because the drive capability of the subsequent drive FET is less likely to decrease even if the logic level of the half latch node of the non-persistent drive latch becomes insufficient, making it less susceptible to the effects of noise during the hold period.

Fourthly, the method described in paragraph 0030 (13) prevents the half-latch node from going to high impedance during the hold period, making it less susceptible to noise. This is because both FET pairs connected in parallel to the first clocked FET are turned on while the cross-coupled inverter pair is being rewritten, preventing the half-latch node drive from the Vdd side from stopping during the hold period after switching to the latch state.

The fifth point is that the measures described in paragraph 0033 (16) can suppress the effect of noise on writing to the subsequent latch during the hold period. This is because a delayed clock signal is distributed to the non-persistent drive latch, which delays the switch to the latched state and prevents the first or second node from becoming high impedance until the middle of the hold period, when it is sensitive to noise.

FIG. 1 is a circuit diagram of an LRFF. FIG. 2 is a circuit diagram of a DFF whose preceding latch has a TSPC split output latch configuration. 3 is a circuit diagram of a configuration example of a DFF according to the first embodiment. 4 is a circuit diagram of a configuration example of a DFF according to the second embodiment. 5 is a circuit diagram of a configuration example of a DFF according to the third embodiment. 6 is a circuit diagram of a DFF configuration example according to the fourth embodiment. 7 is a circuit diagram of a DFF configuration example according to the fifth embodiment. 8 is a circuit diagram of a configuration example of a DFF according to the sixth embodiment. 9 is a circuit diagram of a DFF configuration example according to the seventh embodiment. 10 is a circuit diagram of a DFF configuration example according to the eighth embodiment. FIG. 11 is a circuit diagram of a DFF configuration example according to the ninth embodiment. 12 is a circuit diagram of a DFF configuration example according to a tenth embodiment. 13 is a circuit diagram of a DFF configuration example according to an eleventh embodiment. 14 is a circuit diagram of a DFF configuration example according to a twelfth embodiment. 15 is a circuit diagram of a DFF configuration example according to a thirteenth embodiment. 15 is a circuit diagram of a DFF configuration example according to the thirteenth embodiment. 15 is a circuit diagram of a DFF configuration example according to a thirteenth embodiment. 16 is a circuit diagram of a scan flip-flop configuration example according to a fourteenth embodiment.

We discovered a circuit configuration that takes advantage of the characteristics of CMOS logic circuits with a semi-latch function that can minimize the clock signal load, and realized a static DFF with a low clock signal load that achieves both low power consumption and high-speed operation.

Figure 3 is a circuit diagram of a DFF configuration example (Example 1) related to the first embodiment of the present invention, in which 1 and 1a are first nodes of the half latch node, 2 and 2a are second nodes of the half latch node, 3 and 4 are non-persistent drive latch output nodes, 5 and 5a are a cross-coupled node pair of the cross-coupled inverter pair 50, 11 and 11a are non-clocked first reverse channel N-channel source-grounded FETs, 12 and 12a are N-channel source-grounded first post-stage drive FETs, 13 and 13a are N-channel feedback FETs, and 14 is a first 1 is an N-channel clocked FET of the pass transistor, 14a is an N-channel clocked FET of the second pass transistor, FETs 15 and 15a are first same-channel P-channel common-source FETs that are not clocked, 16 and 16a are first P-channel clocked FETs, 18 and 18a are second N-channel clocked FETs, 20 and 20a are P-channel common-source second post-drive FETs, and 22 and 22a are P-channel feedback FETs that connect their drain terminals to the second nodes 2 and 2a. In this Figure 1, the main nodes are concentrated at one point using diagonal connection lines for ease of understanding, but even if they are divided into multiple points, they are combined into one node if they are connected to each other with solid lines.

25 and 26 are inverters, each cross-coupled to each other at cross-coupled nodes 5 and 5a to form a cross-coupled inverter pair 50. 27 is an inverter for inverting the D signal, 28 is an inverter for outputting the QB signal, 40 is a clock (CLK) terminal, 41 is a D terminal, 42 is a QB terminal, and 51 and 51a are clocked CMOS inverters in which the P-channel first clocked FETs 16 and 16a and the non-clocked P-channel FETs 15 and 15a are connected in series at the second nodes 2 and 2a to form a drive current path on the Vdd side for the first node 1. 52, which is composed of 13 and 18, and 52a, which is composed of 13a and 18a, are feedback circuits for the first nodes 1 and 1a.

This embodiment operates as a master-slave type DFF in which the D signal held at the first node 1, 1a and the second node 2, 2a or the inversion of the D signal is written to the subsequent latch after the clock signal rises from low level to high level and the non-persistent drive latch switches to the latched state and the subsequent latch switches to the transparent state (switched to the latch transparent state). When the hold period ends and the input D signal switches, the first and second subsequent drive FETs 12, 12a, 20, 20a, which are source-grounded and connect the gate terminals to the first node 1, 1a and the second node 2, 2a, do not necessarily maintain their on state until after the hold time, so writing to the cross-coupled inverter pair must be completed during the hold period, just like the semi-static DFF in FIG. 2.

The difference from the semi-static DFF in Figure 2 is that feedback circuits 52, 52a and feedback FETs 22, 22a have been added so that if the rear-stage drive FET turns off during the hold period, the off state will persist even after the hold time. This means that the low and high levels can be maintained without relying on the charge accumulated in the parasitic capacitance, so even if the latched state period is extended in the non-persistent drive latch, the logic level that turned off the rear-stage drive FET during the hold period will not float to the logic level that turns it on. Therefore, even if the latched state period is extended, there will be no excessive leakage current, shoot-through current, or destruction of written contents, as in the conventional example in Figure 2.

When the non-persistent drive latch enters the latched state due to the added feedback circuit and feedback FET, if the first and second nodes 1 and 2 or 1a and 2a are at a low level, the first node 1 or 1a will hold that low level, and if the first and second nodes 1 and 2 or 1a and 2a are at a high level, the second node 2 or 2a will hold that high level, becoming static half-latch nodes. The following two paragraphs 0052 and 0053 will explain this holding operation in detail. However, since there is no difference in the holding operation of the non-persistent drive latch itself between the side without a and the side with a, only the side without a will be explained.

The persistent retention of the low level at the first node 1 begins when the path consisting of the second clocked FET 18, which is turned on in the latch state, and the feedback FET 13 connected in series thereto, switches to the latch state and simultaneously conducts at the low level at the first and second nodes 1 and 2. This is because the source-grounded rear-stage driving FETs 12 and 20 operate as inverters at least during the hold period, causing the non-persistent driving latch output node 3 to which the gate terminal of the feedback FET 13 is connected to become high level. The high level of this non-persistent driving latch output node 3 continues during the latch state. This is because when the non-persistent driving latch output node 3 becomes high level, even if the second rear-stage driving FET 20 turns off, the high level of the cross-coupled node 5 written to the cross-coupled inverter pair 50 during the previous hold period returns via the pass transistor 14 in the on state. Due to the persistence of the high level of this non-persistent drive latch output node 3, the feedback FET 13 remains on during the latched state, and continues to pull the potential of the gate terminal of the first post-stage drive FET 12, i.e., the first node 1, to the source terminal side, i.e., GND side, resulting in the first node 1 being maintained at a low level in the latched state.

The persistent holding of the high level of the second node 2 is similar to the case of the low level, and starts with the feedback FET 22 being on if the first and second nodes 1 and 2 are at high level at the time of entering the latch state. This is because the source-grounded rear-stage driving FETs 12 and 20 operate as inverters at least during the hold period of the D signal input, causing the non-persistent driving latch output node 3 to which the gate terminal of the feedback FET 22 is connected to be at low level. This low level is then written to the cross-coupled inverter pair 50, and continues during the latch state. When the non-persistent driving latch output node 3 becomes low level, even if the first rear-stage driving FET 12 is turned off, the low level of the cross-coupled node 5 written to the cross-coupled inverter pair 50 during the hold period returns via the pass transistor 14 in the on state. Due to the persistence of the low level of this non-persistent drive latch output node 3, the feedback FET 22 remains on during the latched state, and continues to pull the potential of the gate terminal of the second post-stage drive FET 20, i.e., the second node 2, to the source terminal side, i.e., Vdd side, so that the high level of the second node 2 in the latched state is maintained.

As described above, when the clock signal rises from low to high and the non-persistent drive latch enters the latched state, if the first and second nodes 1 and 2 are at low level and 1a and 2a are at high level, the low level of the first node 1 and the high level of the second node 2a are maintained, and if the first and second nodes 1 and 2 are at high level and 1a and 2a are at low level, the high level of the second node 2 and the low level of the first node 1a are maintained. In the end, in the latched state of the non-persistent drive latch, the (low level, high level) of either the first and second node (1, 2a) or (1a, 2) pair is maintained, so that either the first and second rear-stage drive FET (12, 20a) or (12a, 20) pair is maintained off, and the increase in leakage current and the generation of through current are suppressed, thereby achieving a completely static operation.

In this embodiment, for simplicity, the clocked CMOS logic circuit on the side without a is configured as a clocked CMOS inverter, but other clocked CMOS logic circuits can also be used. However, the logic levels of the side without a and the side with a of the first and second nodes 1, 2 and 1a, 2a must be inverted to each other so that the outputs of the non-persistent drive latch output nodes 3, 4 are complementary. For example, if the clocked CMOS logic circuit on the side without a is a clocked CMOS NAND to which the D1 and D2 signals are input, the clocked CMOS logic circuit on the side with a must be a clocked CMOS inverter to which the output of the NAND gate to which the D1 and D2 signals are input is input.

Figure 4 is a circuit diagram of a DFF configuration example (Example 2) related to the second embodiment of the present invention. The difference from Example 1 is that the second clocked FETs 18, 18a are combined into one 18, and the source terminals of the feedback FETs 13, 13a are connected to the drain terminal of the one 18, so that it is shared between both the non-a side and the a side of the non-persistent drive latch, thereby reducing the number of gate terminals that serve as clock signal loads by one. As a result, although the source terminals of the source-grounded FETs 18, 18a are connected to each other, this does not affect the operation of the feedback circuit. This is because when one is turned on, the other is always turned off and does not form a conductive path between the first nodes 1, 1a. This second example has the advantage of reducing the number of gate terminals that serve as clock signal loads by one, which is lower power than the first example.

Figure 5 is a circuit diagram of a DFF configuration example (Example 3) according to the third embodiment of the present invention. The difference from Example 2 is that the source terminal and drain terminal of the N-channel FET 38a, whose gate terminal receives the D signal (the inverted signal of the signal input to the gate terminal of the P-channel FET 15a), are connected to the drain terminal and source terminal of the P-channel FET 15a, which is connected in series with the first clocked FET, whose gate terminal receives the inverted D signal. This parallel connection of the N-channel FETs 38a effectively reduces the setup time of the D signal input. This is because the delay of one inverter stage with respect to the pull-up of the first and second nodes 1a and 2a on the a-attached side is compensated for by the drain grounding operation of the N-channel FET 38a, whose gate terminal receives the D signal without delay. This parallel connection can also be made to the P-channel FET 15 on the non-a-attached side, but since the inverted D signal delayed by one inverter stage must be input to the gate terminal of the N-channel FET, the setup time is not necessarily reduced.

Figure 6 is a circuit diagram of a DFF configuration example (Example 4) related to the fourth embodiment of the present invention. The difference from Example 3 is that a first reverse channel N-channel type source-grounded FET 71 is added to connect the gate terminal to the first node 1 of the non-persistent drive latch without a and the drain terminal to the second node 2a of the non-persistent drive latch with a, and a first reverse channel N-channel type source-grounded FET 71a is added to connect the gate terminal to the first node 1a of the non-persistent drive latch with a and the drain terminal to the second node 2 of the non-persistent drive latch without a. These additions prevent the second nodes 2 and 2a from becoming high impedance during the hold period. If the second nodes 2 and 2a to which the drain terminals are connected are at low level by the time of switching to the latch state, the first nodes 1a and 1 to which the gate terminals are connected are at the opposite high level, so the FETs 71a and 71 are turned on to pull the second nodes 2 and 2a to the low level side. By no longer being in high impedance during the hold period, not only does the second node 2, 2a have significantly improved noise resistance, but the low level is also sufficiently lowered, which has the advantage of increasing the drive capability of the second post-stage driver FET 20, 20a and improving the write speed.

Figure 7 is a circuit diagram of a DFF configuration example (Example 5) related to the fourth embodiment of the present invention. The difference from Example 4 is that a first same-channel P-channel type source-grounded FET 72 is added, which connects the gate terminal to the second node 2 of the non-persistent drive latch without a and the drain terminal to the first node 1a of the non-persistent drive latch with a, and a first same-channel P-channel type source-grounded FET 72a is added, which connects the gate terminal to the second node 2a of the non-persistent drive latch with a and the drain terminal to the first node 1 of the non-persistent drive latch without a. These additions prevent the first nodes 1 and 1a from becoming high impedance during the hold period. If the first nodes 1 and 1a are at a high level by the time they are switched to the latch state, the second nodes 2a and 2 to which the gate terminals are connected are at the opposite low level, so the FETs 72a and 72 are turned on to pull the first nodes 1 and 1a to the high level side. By not becoming high impedance during the hold period, the noise resistance of the first nodes 1 and 1a is improved.

8 is a circuit diagram of a DFF configuration example (Example 6) according to the sixth embodiment of the present invention. The difference from Example 1 is that
(1) The non-persistent drive latch output node 4 is pulled up to the Vdd side by a first reverse channel N-channel third post-stage drive FET 19 with its gate terminal connected to the first node 1 and its source terminal connected to the non-persistent drive latch output node 4, and its drain is grounded.
(2) The non-persistent drive latch output node 4 is pulled down to the GND side by a fourth post-stage drive FET 21 with a common source and an N-channel whose gate terminal is connected to the non-persistent drive latch output node 3 and whose drain terminal is connected to the non-persistent drive latch output node 4.
These two points make it possible to write to the cross-coupled inverter pair without a non-persistent drive latch on the a-side.

Compared to Example 1, Example 6 has the advantage of reducing the number of FETs constituting the DFF by 8. This is because only one non-persistent drive latch is required, and in the latch transparent state, the pull-up means for raising the non-persistent drive latch output node 3 to a completely high level can be eliminated. This pull-up means can be eliminated because the drain-grounded third post-stage drive FET 19 is used to drive the non-persistent drive latch output node 4 to the Vdd side, so that even if the high level of the non-persistent drive latch output node 3 becomes insufficient, it is no longer necessary to connect the gate terminal of the source-grounded P-channel FET that generates a subthreshold leakage current.

Figure 9 is a circuit diagram of a DFF configuration example (Example 7) according to the seventh embodiment of the present invention. The difference from Example 6 is that the second clocked FET 18 of the feedback circuit 52 is replaced with a diode-connected P-channel FET 17 to form a feedback circuit 521, and a diode-connected P-channel FET 23 is inserted between the source terminal of the P-channel feedback FET 22 and Vdd to form a feedback circuit 53. As a result, the clock signal load is reduced by one gate terminal, and the feedback circuit portion of the load on the FETs 11 and 16 that pull the second node 2 to the GND side can be sufficiently reduced even when the channel width cannot be reduced like in the FinFET. The former advantage is due to the replacement of the second clocked FET with a diode-connected P-channel FET 17 with a large impedance. The latter advantage is also due to the insertion of a diode-connected P-channel FET 23 with a large impedance.

Figure 10 is a circuit diagram of a DFF configuration example (Example 8) according to the eighth embodiment of the present invention. The difference from Example 6 is that a delayed clock signal delayed by a delay circuit 54 consisting of two stages of inverters 29 and 30 is distributed to the gate terminals of the first and second clocked FETs in the non-persistent drive latch. Due to the delayed distribution of this clock signal, the latter stage latch enters a transparent state and writing to the cross-coupled inverter pair begins before the non-persistent drive latch enters a latched state. This makes it possible to significantly improve the noise resistance of the first and second nodes 1 and 2. Even if the latter stage latch enters a transparent state, the transparent state of the non-persistent drive latch continues for the delay time, and nodes 1 and 2 continue to be driven by FETs 11 and 15, so that the first and second nodes 1 and 2 do not become high impedance, which is sensitive to noise, until the writing to the cross-coupled inverter pair reaches its final stage.

Figure 11 is a circuit diagram of a DFF configuration example (Example 9) according to the ninth embodiment of the present invention. The difference from Example 2 is that the non-persistent drive latch is replaced with one with a normal output configuration used in the LRFF, and instead of the P-channel second post-stage drive FETs 20, 20a whose gate terminals were connected to the second node, P-channel FETs 73, 73a are provided, each of which connects its gate terminal to the drain terminal of one of the two non-persistent drive latches and the other post-stage drive FET, and its drain terminal to the drain terminal of the other post-stage drive FET. This P-channel FET does not directly connect its gate terminal to the half latch node, so the response is delayed by one stage, but it allows the high level of the latch output to be raised to Vdd. This completely turns off the P-channel FETs 31, 31a, which prevent a collision between the drive of the half latch node and the feedback for low level persistence, and no leakage current occurs between the feedback FETs 13, 13a. In this LRFF non-persistent drive latch, when latching, the P-channel FET 31, 31a that does not collide with the low level hold of the half latch node is turned on, so that the drive from the Vdd side to the half latch node 1, 1a is not cut off in the latched state. This prevents the half latch node from becoming high impedance during the hold period. However, to keep this inhibition effective until sufficient noise resistance is obtained, it is necessary to extend the setup time until the P-channel FETs 31, 31a are switched on and off by the arrival of the D signal at the gate terminal and a power supply path to the half latch node is established. For this reason, the setup time becomes significantly longer than the value required for writing to the cross-coupled inverter pair.

Figure 12 is a circuit diagram of a DFF configuration example (Example 10) according to the tenth embodiment of the present invention. The difference from Example 2 is that the P-channel second post-stage driving FET 20, 20a whose gate terminal is connected to the second node 2, 2a is replaced with the N-channel drain-grounded third post-stage driving FET 19a, 19 whose gate terminal is connected to the first node 1, 1a, and that the first clocked FET 16, 16a is replaced from between the drain terminals of the non-clocked FET 11, 15 and FET 11a, 15a to between the source terminal of the non-clocked P-channel FET 15, 15a and Vdd. The former replacement makes it unnecessary to make the second node 2, 2a a static half-latch node, and as a result, the feedback FET 22, 22a is not required. This results in a normal output configuration in which the number of transistors constituting the DFF is reduced by two. If the channel width is not reduced like in the FinFET and the load reduction effect of the absence of the feedback circuit is not small, the speed is significantly increased. In addition, since there is no node that holds a low level with high impedance, there is no influence of positive electrostatic induction noise caused by the rising edge of the clock signal, which is the main noise in the cell during the hold period, and this has the advantage of making the cell layout easier. On the other hand, the latter swap is possible by eliminating the connection of the gate terminal to the second node 2, 2a. This is because the swap is between FETs with the same channel polarity connected in series, so it does not affect the output of the first node 1, 1a to which the gate terminal is connected. Of course, the latter swap does not need to be performed in this embodiment. This is because the configuration in which the first clocked FET is provided individually for each non-persistent drive latch does not affect the operation as a DFF.

Figure 13 is a circuit diagram of a DFF configuration example (Example 11) related to the 11th embodiment of the present invention. The difference from Example 10 is that the first clocked FETs 16 and 16a are consolidated into 16, which is shared between both the non-a side and the a side of the non-persistent drive latch, thereby reducing the number of gate terminals that serve as clock signal loads by one. As a result, the source terminals of the first same channel P-channel FETs 15 and 15a that are not clocked are both connected to the drain terminal of the first clocked FET, so that the source terminals are connected to each other, but this does not affect the latch operation. This is because the inputs to the gate terminals of the FETs 15 and 15a are inverted signals, so the on and off are reversed and no conductive path is formed between the first nodes 1 and 1a. This 11th example has the advantage of being less power-consuming than the 10th example, since one gate terminal that serves as a clock signal load is reduced.

Figure 14 is a circuit diagram of a DFF configuration example (Example 12) according to the twelfth embodiment of the present invention. The difference from Example 11 is that the third N-channel drain-grounded post-stage driving FET 19, 19a, whose gate terminals are connected to the half latch nodes 1, 1a, is replaced with a first same-channel P-channel source-grounded FET 73, whose gate terminals and drain terminals are connected to the drain terminals of the first source-grounded post-stage driving FETs 12, 12a, respectively, and a first same-channel P-channel source-grounded FET 73a, whose gate terminals and drain terminals are connected to the drain terminals of the first source-grounded post-stage driving FETs 12a, 12, respectively. By changing two N-channel FETs to two P-channel FETs, the imbalance of the N-channel and P-channel of the constituent FETs is improved, which has the advantage of reducing the layout area of the DFF cell.

Figure 15 is a circuit diagram of a DFF configuration example (Example 13) according to the thirteenth embodiment of the present invention. The difference from Example 11 is that the drain terminal and source terminal of the P-channel FET 15a connected in series to the first clocked FET 16, the gate terminal of which receives an inverted D signal, are connected in parallel to the source terminal and drain terminal of the first reverse channel N-channel FET 38a, the gate terminal of which receives the D signal (the inverted signal of the signal input to the gate terminal of the P-channel FET 15a), and that P-channel source-grounded FETs 73 and 73a are added, which connect their gate terminals to the drain terminals of the first rear-stage driving FETs 12 and 12a, which are source-grounded, and their drain terminals to the drain terminals of 12a and 12, respectively. In the former parallel connection to the P-channel FET 15a, although the connected N-channel FET 38a operates as a drain-grounded FET, the input to the gate terminal precedes the source-grounded P-channel FET by one inverter stage, thereby accelerating the pulling up of the first node 1a on the a-attached side and improving the operating speed as a DFF. The addition of the latter P-channel common-source FETs 73 and 73a improves the write capability of the non-persistent drive latch and makes write failures caused by electrostatic induction noise on the half latch node less likely to occur.

Figure 16 is a circuit diagram of a DFF configuration example (Example 14) according to the 14th embodiment of the present invention. The difference from Example 13 is that a pair of FETs 74, 75 connected in series with each other by the P-channel of the first same channel are connected in parallel to the first clocked FET 16. The gate terminals of the pair of P-channel FETs 74, 75 connected in series are respectively connected to the output node 4 of the non-persistent drive latch with a and the cross-coupled node 5 (the node to which the output node 3 of the non-persistent drive latch without a is connected via the first pass transistor 14). When the latch is switched to the transparent state and the cross-coupled inverter pair starts to be rewritten by the low-level output from the non-persistent drive latch with a, the voltage level of the cross-coupled node 5 gradually rises from the low level held until it reaches a high level. However, the P-channel FET 75 remains on until the writing passes the middle stage and the low-level side is left. The P-channel FET 74 is also on during the hold period because the low-level input from the non-persistent drive latch with a to its gate terminal is maintained. As a result, even if the latch goes into a transparent state and the first clocked FET is turned off, the series-connected FET pair 74, 75 will both remain on until the write operation is halfway through, and the pull-up by the FETs 15a, 38a to the first node 1a of the half latch node will continue. As a result, the first node 1a will not be in high impedance for most of the write operation, and the drive capability of the post-stage drive FETs 12a, 19a will be improved, the output delay time of the DFF will be reduced, and the noise resistance will be significantly improved. Note that when the cross-coupled node 5a is at a low level and rewriting does not occur with the low-level output from the non-persistent drive latch with a, the input to the gate terminal of the FET 75 is at a high level, so that the series-connected FET pair 74, 75 will not both be on. In addition, in this embodiment, only the series-connected FET pair 74, 75 whose gate terminals are connected to the non-persistent drive latch output node 4 and the cross-coupled node 5 are connected in parallel to the first clocked FET 16, but the series-connected P-channel FET pair whose gate terminals are connected to the non-persistent drive latch output node 3 and the cross-coupled node 5a can also be connected in parallel to the first clocked FET 16 to prevent the first node 1 from becoming high impedance during writing.

Figure 17 is a circuit diagram of a DFF configuration example (Example 15) related to the 15th embodiment of the present invention. The difference from Example 11 is that a delayed clock signal delayed by a delay circuit 54 consisting of two stages of inverters 29 and 30 is distributed to the gate terminals of the first and second clocked FETs 16 and 18 in the non-persistent drive latch. Due to the delayed distribution of this clock signal, the latter stage latch enters a transparent state and starts writing to the cross-coupled inverter pair before the non-persistent drive latch enters a latched state. This increases the noise resistance of the first nodes 1 and 1a during writing to the cross-coupled inverter pair. Even if the latter stage latch enters a transparent state, the transparent state of the non-persistent drive latch continues for the delay time, and during that time, the first clocked FETs 16 and 16a in the middle of the drive current path on the Vdd side do not turn off, so that the first nodes 1 and 1a do not become high impedance, which is sensitive to noise, until the writing to the cross-coupled inverter pair reaches the end.

Figure 18 is a circuit diagram of a DFF configuration example (Example 16) according to the 16th embodiment of the present invention. The difference from Example 13 is that it is integrated with an LSSD-type scan flip-flop, and the cross-coupled inverter pair 50 can also be written to via N-channel FETs 62 and 63 controlled by a clock signal (CLKB), so that it functions as a rear-stage latch of the LSSD-type scan FF. Since the D-QB path is composed of the DFF of the present invention, both capture mode operation and high-speed, low-power normal mode operation can be achieved with just 16 additional FETs. Here, the normal mode is realized by setting CLKB to low level, and the capture mode is realized by setting CLK to low level and adding appropriate pulses to CLKA and CLKB.

The circuits of the above embodiments 1 to 16 can also be configured so that the channel polarity of each of the constituent FETs is all reversed (the first same channel is changed from P channel to N channel, and the first opposite channel is changed from N channel to P channel) and the Vdd and GND power supplies are swapped. However, in this configuration where all are reversed, the trigger edge of the DFF becomes the falling edge of the clock signal instead of the rising edge.

In addition, in Examples 1 to 5 and Examples 9 to 16, the input terminal (gate terminal of FETs 11a and 15a) of the clocked CMOS inverter of the non-persistent drive latch with a is connected to the output of inverter 27, but it can also be connected to the first node 1 of the non-persistent drive latch without a instead. Although the setup time increases slightly, there is an advantage in that the number of constituent FETs is reduced by two since inverter 27 can be omitted.

It is expected to be widely used as a low-power DFF to replace TGFF. Although the cell area may increase slightly, under average usage conditions of a data activation rate of 10% or less, it achieves a power-delay product of about 1/3 that of a TGFF while also providing sufficient noise immunity.

1, 1a First node 2, 2a Second node 3 Third node 4 Fourth node 5, 5a Cross-coupled nodes 11, 11a, 13, 13a, 33, 36, 71, 71a, 110, 111 Common-source N-channel FET
12, 12a N-channel, source-grounded first post-drive FET
20, 20a P-channel, common-source, second post-drive FET
21 N-channel, source-grounded fourth post-drive FET
15, 15a, 22, 31, 32, 34, 35, 37, 72, 72a, 73, 73a, 74, 75, 150, 151 Common-source P-channel FET
17, 17a, 23 Diode-connected P-channel FET
19, 19a N-channel, drain-grounded third post-drive FET
38a Common-drain N-channel FET
14 First pass transistor N-channel FET
14a Second pass transistor N-channel FET
16, 16a, 161 P-channel first clocked FET
18, 18a N-channel second clocked FET
37 Pass Transistor P-Channel FET
24-30, 65-70 Inverter 60-63 Pass transistor N-channel FET
40 Clock (CLK) terminal 41 D terminal 42 QB terminal 43 Scan input (IB) terminal 44 Scan clock A (CLKA) terminal 45 Scan clock B (CLKB) terminal 50 Cross-coupled inverter pair 51, 51a Clocked CMOS inverters 52, 52a, 521, 53 Feedback circuit 54 Delay clock signal generating circuit

Claims (17)

A D-type flip-flop consisting of two stages of latches, front and rear, which take either a latched or transparent state depending on the logic level of a clock signal, characterized in that the front latch includes a half-latch node that permanently holds only one of the logic levels in the latched state and a latch with a FET for driving the rear latch whose gate terminal is connected to the half-latch node, the latch with the rear-stage drive FET is a non-persistent drive latch that does not persist in the latched state, and the rear latch includes a cross-coupled inverter pair and a pass transistor that is a clocked FET via drive from the non-persistent drive latch to the cross-coupled node of the inverter pair. The D-type flip-flop according to claim 1, characterized in that the non-persistent drive latch includes a feedback FET having the same channel polarity as the source-grounded post-drive FET, which is one of the post-drive FETs, and which connects its gate terminal to the drain terminal of the source-grounded post-drive FET and its drain terminal to the half-latch node, and the pass transistors include a first pass transistor that connects one of its input/output terminal pair to one of the pair of cross-coupled nodes and a second pass transistor that connects one of its input/output terminal pair to the other of the pair of cross-coupled nodes. The D-type flip-flop according to claim 2, characterized in that the non-persistent drive latch includes a first clocked FET and a non-clocked FET as FETs forming a path through which a current flows to drive the half-latch node, the non-clocked FETs are composed of a first same-channel FET having the same channel polarity as the first clocked FET and a first reverse-channel FET having the reverse channel polarity, and the circuit composed of the drive current path forming FETs is configured such that the half-latch node is a first node connecting the drain terminal of the first clocked FET and the drain terminal of the first non-clocked reverse-channel FET, and a second node connecting the source terminal of the first clocked FET and the drain terminal of the first non-clocked same-channel FET. The D-type flip-flop according to claim 3, characterized in that it has two non-persistent drive latches as the front-stage latches, and the other of the input/output terminal pair of the first pass transistor and the other of the input/output terminal pair of the second pass transistor are connected to the drain terminal of the source-grounded rear-stage drive FET of one of the two non-persistent drive latches and the drain terminal of the source-grounded rear-stage drive FET of the other of the two non-persistent drive latches, respectively. The D-type flip-flop according to claim 4, characterized in that it comprises a first reverse-channel common-source FET having a gate terminal connected to a first node of the one non-persistent drive latch and a drain terminal connected to a second node of the other non-persistent drive latch, and a first reverse-channel common-source FET having a gate terminal connected to the first node of the other non-persistent drive latch and a drain terminal connected to the second node of the one non-persistent drive latch. The D-type flip-flop according to claim 5, further comprising a first common-channel common-source FET having a gate terminal connected to the second node of the one non-persistent drive latch and a drain terminal connected to the first node of the other non-persistent drive latch, and a first common-channel common-source FET having a gate terminal connected to the second node of the other non-persistent drive latch and a drain terminal connected to the first node of the one non-persistent drive latch. The D-type flip-flop according to claim 3, characterized in that the drain terminal of the common-source post-drive FET, the gate terminal of which is connected to the first node, is connected to the other of the pair of input/output terminals of the first pass transistor, and the source terminal of a common-drain post-drive FET, one of the post-drive FETs, the gate terminal of which is connected to the first node, is connected to the other of the pair of input/output terminals of the second pass transistor. The D-type flip-flop according to claim 2, characterized in that it comprises two non-persistent drive latches as the front-stage latches, the two non-persistent drive latches comprise a first clocked FET and a non-clocked FET as FETs forming a path through which a current flows to drive a half-latch node, the non-clocked FET comprises a first reverse-channel FET having a channel polarity opposite to that of a first same-channel FET having the same polarity as that of the first clocked FET, the circuit consisting of the drive current path forming FETs is configured such that the half-latch node is a node connecting the drain terminal of the first same-channel FET not clocked and the drain terminal of the first reverse-channel FET not clocked, and the drain terminal of the common-source rear-stage drive FET of one of the two non-persistent drive latches and the drain terminal of the common-source rear-stage drive FET of the other of the two non-persistent drive latches are connected to the other of the input/output terminal pairs of the first and second pass transistors, respectively. The D-type flip-flop according to claim 8, further comprising a first common-channel common-source FET that connects its gate terminal to the drain terminal of the common-source rear-stage driving FET of the one non-persistent drive latch and its drain terminal to the drain terminal of the common-source rear-stage driving FET of the other non-persistent drive latch, and a first common-channel common-source FET that connects its gate terminal to the drain terminal of the common-source rear-stage driving FET of the other non-persistent drive latch and its drain terminal to the drain terminal of the common-source rear-stage driving FET of the one non-persistent drive latch. The D-type flip-flop according to claim 8, characterized in that the other of the input/output terminal pair of the first pass transistor is connected to the source terminal of a common-drain FET that is one of the rear-stage driving FETs of the other non-persistent drive latch, and the other of the input/output terminal pair of the second pass transistor is connected to the source terminal of a common-drain FET that is one of the rear-stage driving FETs of the one non-persistent drive latch. The D-type flip-flop according to claim 9, characterized in that the other of the input/output terminal pair of the first pass transistor is connected to the source terminal of a common-drain FET that is one of the rear-stage driving FETs of the other non-persistent drive latch, and the other of the input/output terminal pair of the second pass transistor is connected to the source terminal of a common-drain FET that is one of the rear-stage driving FETs of the one non-persistent drive latch. The D-type flip-flop of claim 11, characterized in that the first clocked FET is a common-source FET, and the drain terminal of the clocked FET is connected to the source terminal of a first non-clocked same-channel FET that connects a drain terminal to the half-latch node of each of the two non-persistent latches. The D-type flip-flop according to claim 13, characterized in that it comprises two first same-channel FETs connected in series with each other, the drain terminal and source terminal of the FET not used in the series connection of the two FETs are connected to the drain terminal and source terminal of the first clocked FET, respectively, and the gate terminals of each of the two FETs are connected to the drain terminal of the common-source post-drive FET of one of the two non-persistent drive latches and to a cross-coupled node driven by the common-source post-drive FET of the other non-persistent drive latch via the pass transistor, respectively. A D-type flip-flop as described in any one of claims 4 to 6 or 8 to 13, characterized in that it comprises a first same-channel second clocked FET with a common source that connects the source terminal of the feedback FET of each of the two non-persistent drive latches to its own drain terminal. The D-type flip-flop of claim 14, characterized in that the non-persistent drive latch includes a first reverse-channel FET that inputs to its gate terminal an inverted signal input to a gate terminal of a first non-clocked same-channel FET connected in series with the first clocked FET, and connects its source terminal and drain terminal to the drain terminal and source terminal of the first non-clocked same-channel FET, respectively. The D-type flip-flop of claim 14, characterized in that a delayed clock signal, the phase of which is delayed from the clock signal input to the gate terminal of the pass transistor, is input to the gate terminal of the clocked FET in the non-persistent drive latch. A D-type flip-flop according to any one of claims 3 and 7, characterized in that a delayed clock signal having a phase delay with respect to the clock signal input to the gate terminal of the pass transistor is input to the gate terminal of the clocked FET in the non-persistent drive latch.

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