KR20090080338A - Flip-Flop - Google Patents

Abstract

A flip-flop is provided to reduce power consumption by reducing an area thereof. A flip-flop(100) includes a first latch unit(110), a first transmission gate(120), and a second latch unit(130). The first latch unit includes a first transistor which is turned on or off by a clock signal. The first latch latches input data in response to the clock signal. The first transmission gate is serially connected with an output terminal of the first latch unit. The first transmission gate is operated according to the clock signal. The second latch unit is serially connected with the first transmission gate. The second latch unit includes a second transistor which is turned on or off by the clock signal. The second latch unit latches input data in response to the clock signal.

Description

Flip-Flops

The present invention relates to a flip flop, and more particularly to a flip flop that can reduce the area by reducing the number of transistors provided therein.

Flip-flops are storage elements that store and output data, and are widely used in various semiconductor devices. The flip-flop stores the input data and outputs the input data stored in response to the input clock signal.

The flip-flop has a plurality of transistors internally and adjusts the input and output of data by turning on or off the transistors.

Mobile devices are becoming smaller and lower in power, and it is important to reduce the area and reduce power consumption. Therefore, in mobile devices, it is also important to reduce the power consumption of the mounted flip flop. The effect of flip flops on power is huge. In the power consumption of the embedded microprocessor core, the power consumption of the flip flop accounts for about 50% of the total power consumption.

In addition, as the number of transistors internally provided in the flip flop increases, the amount of delay generated during signal transmission increases. Signal delays result in performance degradation in high speed operation of flip flops.

The technical problem to be achieved by the present invention is to provide a flip-flop that can reduce the area and power consumption.

A flip flop according to an embodiment of the present invention includes a first latch portion, a second transfer gate, and a second latch portion.

The first latch unit includes a first transistor turned on and off by a clock signal, and latches input data in response to the clock signal.

The first transfer gate is serially connected to the output terminal of the first latch unit and operates in response to the clock signal.

The second latch unit is connected in series with a first transfer gate and includes a second transistor turned on or off by the clock signal, and latches data input in response to the clock signal.

Preferably, the first latch unit is connected to the first node, one end of which is connected to the first node to which the input terminal and the output terminal are respectively input, and a second node which is an output terminal of the first latch unit. The first transistor receives the clock signal through a gate terminal, and a second inverter having an input terminal and an output terminal connected to the second node and the other end of the first transistor, respectively.

Preferably, the second latch unit includes a third inverter having an input terminal and an output terminal connected to a third node which is an output terminal of the first transmission gate and a fourth node which is an output terminal of the flip flop, respectively, one end of which is the third inverter. And a fourth inverter connected to a node, the second transistor receiving the clock signal through a gate terminal, and a fourth inverter connected to an input terminal and an output terminal of the fourth node and the other end of the second transistor, respectively.

The first transistor may be a P-type MOS transistor, the second transistor may be an N-type MOS transistor, and the clock signal may be a signal obtained by inverting an externally input clock signal.

Preferably, the first transistor is an N-type MOS transistor, the second transistor is a P-type MOS transistor, the clock signal is characterized in that the same as the externally input clock signal.

Preferably, the switching point of the first inverter is adjusted in consideration of the threshold voltage value of the first transistor, and the adjustment of the switching point is made by adjusting the widths of the P-type MOS transistor and the N-type MOS transistor in the first inverter.

Preferably, the switching point of the third inverter is adjusted in consideration of the threshold voltage value of the second transistor, and the adjustment of the switching point is made by adjusting the widths of the P-type MOS transistor and the N-type MOS transistor in the third inverter.

Preferably, the flip flop further includes a second transmission gate connected in series with a front end of the first latch unit and operating in response to the clock signal.

The flip-flop according to an embodiment of the present invention can reduce the area by minimizing the number of transistors provided. It can also reduce internal delays and reduce power consumption.

DETAILED DESCRIPTION In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings which illustrate preferred embodiments of the present invention and the contents described in the drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals in the drawings denote like elements.

1 illustrates a flip flop according to an embodiment of the present invention.

Referring to FIG. 1, the flip flop 100 according to the present invention includes a first latch unit 110, a second latch unit 120, and a first transmission gate 130. The flip flop 100 according to the present invention may further include a second transmission gate 140.

The second transmission gate 140 transmits the input data D to the first node N1.

The first latch unit 110 includes a first transistor 112 that is turned on and off by the clock signal CK, and latches a signal applied to the first node N1, which is an input terminal, in response to the clock signal.

Preferably, the first latch unit 110 includes a first inverter 116, a second inverter 114, and a first transistor 112. The connection relationship of each configuration is as shown in FIG.

The first transfer gate 130 is serially connected to the second node N2, which is an output terminal of the first latch unit 110, and is turned on or off in response to a clock signal. Specifically, the first transfer gate

The second latch unit 120 is connected in series with the third node N3, which is an output terminal of the first transmission gate 130. And a second transistor 122 that is turned on or off in response to the clock signal, and latches input data (ie, a signal transmitted to the third node N3) in response to the clock signal.

Preferably, the second latch unit 120 includes a third inverter 126, a fourth inverter 124, and a second transistor 122. The connection relationship of each configuration is as shown in FIG.

Here, the first and second transfer gates 130 and 140 have a form in which a P-type MOS transistor and an N-type MOS transistor are respectively combined.

In FIG. 1, the first and second transistors are P-type MOS transistors MOS1 and N-type MOS transistors MOS2, respectively. The clock signal applied to the gates of the first and second transistors 112 and 114 at this time becomes an inverted clock signal / CK (a signal obtained by logically inverting the clock signal CK).

Hereinafter, the first and second transistors become P-type MOS transistors MOS1 and N-type MOS transistors MOS2, respectively, and clock signals applied to gates of the first and second transistors 112 and 114 are inverted clocks. The case where it becomes a signal / CK is demonstrated as an example.

First, the case where the clock signal CK is applied to the logic low level 0 will be described. When the clock signal CK is in the logic low period, the first transfer gate 130 is turned off and the second transfer gate 140 is turned on. The first transistor 112 is turned off and the second transistor 122 is turned on.

Referring to the operation of the flip flop 100, first, the data signal D is applied to the input terminal of the second transmission gate 140. Since the second transmission gate 140 is turned on, the data signal D is transmitted to the first node N1. The data signal transmitted to the first node N1 is inverted and output while passing through the first inverter 116. Therefore, the signal applied to the second node N2 becomes the inverted data signal / D.

Since the first transmission gate 130 is turned off, the signal applied to the second node N2 may not be transmitted to the third node N3. Therefore, the second latch unit 120 outputs a signal previously transmitted (a signal applied to the third node N3).

Then, the clock signal CK transitions from the logic low level 0 to the logic high level 1 and is applied. When the clock signal CK is in a logic high period, the first transfer gate 130 is turned on and the second transfer gate 140 is turned off. The first transistor 112 is turned on and the second transistor 122 is turned off.

Since the clock signal CK is at a logic high level, the first transistor 112 is turned on, and a signal applied to the fifth node N5 is transmitted to the first node N1. Accordingly, the first latch unit 110 latches data signals of the first and second nodes N1 and N2.

Since the first transmission gate 130 is turned on, the inverted data signal / D, which is a signal applied to the second node N2, is transmitted to the third node N3. The inverter passes through the third inverter 126 and is output as a data signal D. Therefore, the data signal D is output to the fourth node N4, which is an output terminal of the flip flop 100.

In addition, the first and second transistors 112 and 114 may be N-type MOS transistors and P-type MOS transistors, respectively. In this case, the signals applied to the gate terminals of the first and second transistors 112 and 114 may be clock signals CK itself. In the case where the first and second transistors 112 and 114 become N-type MOS transistors and P-type MOS transistors, respectively, the operation described above (the first and second transistors are P-type MOS transistors MOS1 and N-type, respectively) In the case of a MOS transistor (MOS2). Therefore, detailed description thereof will be omitted.

FIG. 2 is a diagram illustrating a detailed structure of the inverter included in FIG. 1.

Referring to FIG. 2, the first to third inverters 116, 114, 126, and 124, which are the inverters of FIG. 1, each use one P-type MOS transistor PM and one N-type MOS transistor NM. Equipped.

The inverter 200 inverts the signal S_in when the signal S_in is applied to the input terminal and outputs the inverted signal S_out. Specifically, when the input signal S_in is at a logic high level, the P-type MOS transistor PM is turned off and the N-type MOS transistor NM is turned on. Therefore, the twelfth node N12 is connected to the ground voltage Vground so that the logic low level signal is output as the S_out signal. In contrast, when the input signal S_in is at a logic low level, the P-type MOS transistor PM is turned on and the N-type MOS transistor NM is turned off. Therefore, the high power supply voltage Vdd is connected to the twelfth node N12, so that the logic high level signal is output as the S_out signal.

As described above, each inverter has two MOS transistors, and the flip-flop 100 has only 14 MOS transistors in total. Accordingly, the number of MOS transistors required to hold, shift, and release the data may be calculated using the first transfer gate 130 and the first through second transistors 112 and 122. Can be minimized.

Therefore, it is possible to minimize the area of the flip flop and the power consumption (Area / Power), and to minimize the signal delay (when the number of MOS transistors provided is reduced, the number of MOS transistors to pass through in the signal movement is increased. As a result, signal delay in data movement can be minimized.) Data transmission speed can be improved.

For reference, a conventional flip-flop uses a tri-state buffer or a transmission gate in a loop used to maintain a data value. In contrast, in the present invention, by using one transistor (first or second transistor) in a loop used to maintain data values, the circuit can be simplified and miniaturized.

In addition, in the flip-flop 100 according to an embodiment of the present invention, the latching performance may be further improved by adjusting switching points of the first and third inverters 116 and 126. A description with reference to FIGS. 3a and 3b below.

3A is a diagram illustrating a voltage of the first node N1 of FIG. 1. In FIG. 3A, the case where the first transistor 112 becomes a P-type MOS transistor will be described as an example.

In the flip-flop 100 shown in FIG. 1, the switching point of the first inverter 116 is adjusted in consideration of the threshold voltage value of the first transistor 112. The switching point of the first inverter 116 is achieved by adjusting the widths (preferably ratios of the widths) of the P-type MOS transistors and the N-type MOS transistors provided in the first inverter 116.

Here, the switching point refers to a threshold value that must be applied in order for the inverter to detect a change in outputting a signal varying from 0 to 1 or from 1 to 0. For example, assume that a signal recognized as logic high is a high power supply voltage Vdd, and a signal recognized as a logic low is a ground voltage Vground. At this time, if a value exceeding the value of Vdd / 2 is recognized as a logic high, and if a value less than the value of Vdd / 2 is recognized as a logic low, Vdd / 2 becomes the switching point of the inverter. .

Referring to FIG. 3A, the first transistor 112 is a P-type MOS transistor, and the threshold voltage of the P-type MOS transistor at this time is illustrated as Vthp. The threshold voltage Vthp of the P-type MOS transistor affects a constant voltage value from the ground terminal (ground). That is, the first section illustrated in FIG. 3A is a weak section of the PMOS discharge of the P-type MOS transistor, and the voltage control is very weak. Therefore, the switching point of the first inverter 116 may be increased by Vthp / 2 to Vthp at the existing switching point in consideration of the threshold voltage value of the first transistor 112.

In FIG. 3A, when the existing switching point is Vdd / 2, a point of increasing <th> by Vthp / 2 may be the switching point of the first inverter 116. As described above, when the switching point of the first inverter 116 is increased, the inverter may stably perform the switching operation without being affected by the threshold voltage value of the P-type MOS transistor 112 even when operating at a low voltage.

Here, the switching point of the inverter can be adjusted by adjusting the ratio (W: width) of the P-type MOS transistor and the N-type MOS transistor provided in the inverter.

For example, assume that the threshold voltage value of the P-type MOS transistor manufactured in the 45 nm process is Vthp = 0.27V, and the switching point of the first inverter 116 is Vdd / 2. The width (W) ratio of the P-type MOS transistor and the N-type MOS transistor for which the switching point is Vdd / 2 is 2.5: 1 (the width (W) of the P-type MOS transistor is 2.5 times the width (W) of the N-type MOS transistor). A) In this case, in order to change the switching point of the first inverter 116 by Vthp / 2, the width W ratio of the P-type MOS transistor and the N-type MOS transistor included in the inverter may be changed to be 3.5: 1. That is, the switching point of the inverter can be adjusted by adjusting the width ratio of the P-type MOS transistor and the N-type MOS transistor provided in the inverter.

3B is a diagram illustrating the voltage of the third node N3 of FIG. 1. In FIG. 3B, the case where the second transistor 122 is an NGud MOS transistor will be described as an example.

In the flip-flop 100 shown in FIG. 1, the switching point of the third inverter 126 is adjusted in consideration of the threshold voltage value of the second transistor 122. The switching point of the third inverter 126 is formed by adjusting the widths (preferably ratios of the widths) of the P-type MOS transistors and the N-type MOS transistors provided in the third inverter 126. The definition of the switching point is as described in FIG. 3A.

Referring to FIG. 3B, the second transistor 122 is an N-type MOS transistor, and the threshold voltage value of the N-type MOS transistor at this time is illustrated as Vthn. The threshold voltage Vthn of the N-type MOS transistor affects a constant voltage value from the high power supply voltage Vdd. That is, the second section illustrated in FIG. 3B is a weak section of the NMOS discharge of the N-type MOS transistor, and the voltage control is very weak. Therefore, in consideration of the threshold voltage value of the second transistor 122 of the switching point of the third inverter 126, the third inverter 126 reduces the point <b> that is reduced by Vthn / 2 to Vthn at the existing switching point. Can be a switching point of.

As described above, if the switching point of the third inverter 126 is reduced, the inverter may perform the switching operation stably without being influenced by the threshold voltage value of the N-type MOS transistor 122 even when operating at a low voltage.

Here, the switching pointer of the inverter can be adjusted by adjusting the ratio of the width (W) of the P-type MOS transistor and the N-type MOS transistor provided in the inverter as described above with reference to FIG. 3A.

For example, assume that the threshold voltage value Vthn = 0.25V of the N-type MOS transistor fabricated in the 45 nm process and the switching point of the third inverter 126 are Vdd / 2. The width ratio that causes the switching point to be Vdd / 2 is 2.5: 1 as in FIG. 3A. In this case, in order to change the switching point of the second inverter 126 by Vthn / 2 (to reduce it to the point <b>), the width (W) ratio of the P-type MOS transistor and the N-type MOS transistor provided in the inverter is 1.7. You can change it to: 1. That is, the switching point of the inverter can be adjusted by adjusting the width ratio of the P-type MOS transistor and the N-type MOS transistor provided in the inverter.

The threshold voltage value is not limited to vary depending on the fabrication specification (W, L, etc.) of the MOS transistor used. In addition, the change of the switching point according to the width ratio of the P-type MOS transistor and the N-type MOS transistor in the inverter can be obtained experimentally.

4A shows a flip flop element.

Referring to FIG. 4A, the D terminal is a terminal to which data is input. The Q and / Q terminals are terminals through which input data is output, Q denotes output data itself, and / Q denotes a terminal on which inverted output data is output.

The flip flop operates in synchronization with the clock signal CK. That is, when the clock signal CK transitions to logic high, the applied data signal is output to the output terminal Q.

Figure 4b is a view showing the area and power consumption of the flip flop according to the present invention.

의 단위가 이용되었다. 4A and 4B, DQ denotes a time taken for the D terminal to enter and exit the Q terminal, and a unit of ps (pico sec.) Is used. CQ means the time taken to transmit to the Q terminal after the clock signal CK is applied high, and the unit of ps is used. Pwr represents the amount of power consumed, and a unit of uW (micro watt) is used. PDP is the product of power and delay.

The unit of was used.

Referring to FIG. 4B, the area, D-Q, C-Q, power, and PDP values in the flip flop according to the present invention and the flip flop in the prior art are comparatively shown. Looking at the area, the area was reduced by about 20% and the D-Q and C-Q values were reduced by about 9%. The power was reduced by 17% and the PDP value was reduced by 22)%. Accordingly, the flip flop according to the exemplary embodiment of the present invention can reduce the area and power consumption and reduce the signal delay compared to the conventional flip flop.

As described above, optimal embodiments have been disclosed in the drawings and the specification. Although specific terms have been used herein, these terms are only used for the purpose of describing the present invention and are not intended to limit the scope of the present invention as defined in the claims or the claims. Therefore, those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

1 illustrates a flip flop according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating a detailed structure of the inverter included in FIG. 1.

3A is a diagram illustrating a voltage of the first node N1 of FIG. 1.

3B is a diagram illustrating the voltage of the third node N3 of FIG. 1.

4A shows a flip flop element.

Figure 4b is a view showing the area and power consumption of the flip flop according to the present invention.

Claims (8)

A first latch unit having a first transistor turned on and off by a clock signal, the first latch unit latching data input in response to the clock signal; A first transmission gate connected in series with an output terminal of the first latch unit and operating in response to the clock signal; And And a second transistor connected in series with the first transfer gate, the second transistor being turned on or off by the clock signal, and having a second latch unit configured to latch data input in response to the clock signal. . The method of claim 1, wherein the first latch portion A first inverter having an input terminal and an output terminal connected to a first node to which the data is input and a second node which is an output terminal of the first latch unit, respectively; The first transistor having one end connected to the first node and receiving the clock signal through a gate terminal; And And a second inverter having an input terminal and an output terminal respectively connected to the second node and the other end of the first transistor. The method of claim 2, wherein the second latch portion A third inverter having an input terminal and an output terminal connected to a third node which is an output terminal of the first transmission gate and a fourth node which is an output terminal of the flip flop, respectively; The second transistor having one end connected to the third node and receiving the clock signal through a gate terminal; And And a fourth inverter having an input terminal and an output terminal connected to the fourth node and the other end of the second transistor, respectively. The method of claim 3, In the flip flop, The first transistor is a P-type MOS transistor, The second transistor is an N-type MOS transistor, The clock signal is A flip flop, which is a signal inverted from an externally input clock signal. The method of claim 3, In the flip flop, The first transistor is an N-type MOS transistor, The second transistor is a P-type MOS transistor, And the clock signal is identical to an externally input clock signal. The method of claim 3, The switching point of the first inverter is In consideration of the threshold voltage value of the first transistor, Adjustment of the switching point is And a width of the P-type MOS transistor and the N-type MOS transistor in the first inverter. The method of claim 3, The switching point of the third inverter is In consideration of the threshold voltage value of the second transistor, Adjustment of the switching point is And a width of the P-type MOS transistor and the N-type MOS transistor in the third inverter. The method of claim 1, wherein the flip flop And a second transmission gate connected in series with a front end of the first latch unit and operating in response to the clock signal.

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