KR20090077245A - Wafer's defect control method - Google Patents

Abstract

A wafer defect control method is provided, which prevents the defect from being generated from the second wafer in the backside surface of wafer. The wafer defect control method controlling defect of the wafer(101) surface is as follows. Etchant is supplied to the inside of the chamber and the inner surface of the chamber is etched. The etched inner surface of the chamber is coated by supplying the coating agent to the inside of the chamber. The supplying period of the coating agent is 40-60 seconds. The supplying period of etchant is 40-60 seconds. The inner temperature of the chamber is 1100-1200 deg.C. Etchant includes the hydrochloride.

Description

Wafer defect control method

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wafer defect control method, and to a wafer defect control method capable of controlling haze, halo, and comb line defects generated during an epitaxial process.

Today, a silicon wafer, which is widely used as a material for manufacturing a semiconductor device, refers to a crystalline silicon thin film made of polycrystalline silicon as a raw material.

Silicon wafers are classified into polished wafers, epitaxial wafers, silicon on insulator wafers, diffused wafers, and high wafers, depending on the processing method. .

The epitaxial wafer refers to a wafer in which a thin film is formed by stacking a silicon single crystal, which is the same as a substrate using a chemical vapor deposition method, on the surface of a silicon single crystal polished wafer (PW) as a substrate to about 1 to 100 μm. At this time, the chemical vapor deposition method supplies a silicon raw material to a gas in a gaseous state and decomposes the reaction gas into radical atoms from a high-temperature energy source and deposits it on the surface of the substrate wafer. The atmosphere inside, that is, the flow of fluid and energy sources, and the carbon parts (susceptor, lift pin) that support the substrate wafer are all used as main management factors.

FIG. 1 is a schematic diagram illustrating a wafer force generated due to a temperature difference when loading a wafer, and FIG. 2 is a schematic diagram illustrating an autodoping phenomenon generated when manufacturing an epitaxial wafer by chemical vapor deposition. .

Recently, as the demand for mirror-like epitaxial wafers with large diameters and thin epitaxial layers for application of DRAM or CMOS logic devices increases, there is an urgent need for technology development. However, oxide film (LTO; When the protective film such as Low Temperature Oxide) and Poly is not applied, various problems may occur due to the high temperature process, considering that chemical vapor deposition proceeds at a high temperature of 1100 ° C. or more. That is, referring to FIG. 1, when the wafer 1 is loaded on the susceptor 2, thermal shock occurs on the contact surface of the wafer 1 due to the warpage of the wafer 1 due to the temperature difference between the wafer 1 and the chamber. It can cause damage to the back side. Looking at the temperature difference of each component in Figure 1, it can be seen that T1> T2> T3> T4> T5.

In addition, as shown in FIG. 2, when heat is supplied using the heat source 5 in the chamber, auto-doping may occur as a side reaction in addition to the epitaxy main reaction. Examples of such autodoping include external diffusion and diffusion into the epi layer 3 from the wafer 1 as in paths I and II, or diffusion into the wafer 1 from the susceptor 2 as in path III. Alternatively, as in the path IV, it may be externally diffused from the susceptor 2 to the epi layer 3. In this case, a pre-tuck ring 4 is positioned around the susceptor 2 to provide heat to the susceptor 2 or to keep the susceptor 2 warm.

This auto-doping consequently interferes with the concentration control of the epi layer, invades impurities and the like in the reactor system, and causes defects in the wafer 1.

FIG. 3 is a perspective view illustrating a scene in which a halo is generated on the back side of the wafer, and FIG. 4 is a perspective view illustrating a scene in which a scratchable defect occurs on the back side of the wafer.

As shown in the drawing, the wafer 1 is warped due to a temperature difference when the wafer 1 is loaded in the susceptor. That is, the wafer 1 is vulnerable to thermal shock. In addition, in the deposition step of forming the epitaxial layer, the coating occurs on the back surface of the wafer 1 due to the external diffusion of the negative reaction material coated in the susceptor, and the water branch existing in the chamber. To cause haze, or halo. In addition, the Cl- group is induced from the hydrogen chloride gas (HCl Gas) and the reaction gas TCS used for the chamber etching to form an etch pit on the back surface of the wafer 1, thereby causing a comb-tooth pattern defect. do. These defects result in lower wafer yields and increase production costs.

An object of the present invention for solving the above problems is to provide a wafer defect control method that can increase the yield by preventing haze, halo, or comb-patterned defects generated on the back of the wafer.

Another object of the present invention is to provide a wafer defect control method capable of controlling the defects on the back side of the wafer by adjusting the coating time after etching the inner surface of the chamber.

According to a preferred embodiment of the present invention for achieving the above object, the wafer defect control method of the present invention by supplying an etchant into the interior of the chamber to etch the inner surface of the chamber and the coating agent into the interior of the chamber Coating the inner surface of the chamber by supplying and etching. Here, the time for supplying the coating agent is preferably about 40 to 60 sec. And, the etchant is preferably supplied for about 40 to 60 sec.

On the other hand, the internal temperature of the chamber in the present invention is preferably maintained at about 1100 to 1200 ℃.

In addition, the etchant of the present invention includes hydrogen chloride (HCl), in addition to other materials capable of etching the inner surface of the chamber may be used.

As described above, according to the present invention, in the case of sequentially epitaxial processing of a plurality of wafers by coating the inner surface of the processor chamber in which the wafer is stored after the epitaxial process of the first wafer for about 40 to 60 seconds, From the second wafer, like the first wafer, there is an effect of preventing defects on the back side of the wafer.

In addition, even if no purging is performed after the inner surface of the processor chamber is etched or the purging time is shortened, haze, halo or line defects may be formed on the back side of the wafer during the epitaxial process. You can prevent this from happening.

As described above, although described with reference to the preferred embodiment of the present invention, those skilled in the art various modifications and variations of the present invention without departing from the spirit and scope of the invention described in the claims below I can understand that you can.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings, but the present invention is not limited or limited by the embodiments.

FIG. 5 is a perspective view illustrating an epitaxial wafer manufacturing apparatus according to an embodiment of the present invention, and FIG. 6 is a side view illustrating the process chamber of FIG. 5. FIG. 7 is a graph illustrating an epitaxial process in a process chamber, FIG. 8 is a perspective view illustrating a wafer back side state according to a purging time before wafer loading, and FIG. 9 is a chamber etching process. It is a perspective view shown in order to demonstrate the back surface state of the wafer which is not coated after.

The wafer manufacturing apparatus 1 of the present invention is not only an apparatus for epitaxial growth, but also chemical vapor deposition (CVD), low pressure chemical vapor deposition (LPCVD), and plasma chemistry. It may also be applied to deposition apparatuses such as plasma enhanced chemical vapor deposition (PECVD).

Hereinafter, an epitaxial wafer manufacturing apparatus and a manufacturing method will be described as an example of the wafer manufacturing apparatus.

Referring to the drawings, the wafer manufacturing apparatus includes an interface 10, a load-lock chamber 20, a transfer chamber 30, and a process chamber 50. Include. In addition, a blade 40 for loading and unloading the wafer 101 is provided.

The interface 10 is responsible for the automatic opening and closing of the transferable unit to accommodate a plurality of wafers (101). For example, the receiving unit of the wafer 101 is a front opening unified pod (FOUP) 6. That is, the interface 10 connects the FOUP 6 and the load lock chamber 20, and transfers the wafer 101 to the load lock chamber 20 by a handling robot.

The load lock chamber 20 introduces and exports the wafer 101 into the wafer fabrication apparatus.

Here, the wafer manufacturing process may be performed in a vacuum state. To this end, the inside of the wafer manufacturing apparatus is maintained in a vacuum state, and the vacuum of the wafer manufacturing apparatus may be destroyed when the wafer 101 enters and exits. Thus, the load lock chamber 20 forms a buffer region for entering and exiting the wafer 101 without breaking the vacuum of the wafer manufacturing apparatus.

However, when the wafer fabrication process is performed at atmospheric pressure instead of vacuum, the load lock chamber 20 may not be vacuumed.

The load lock chamber 20 is composed of upper and lower parts, and the upper part receives the wafer introduced by the handling robot of the interface 10. That is, in the upper portion of the load lock chamber 20, the wafer 101 before the wafer manufacturing process is performed is put in, and serves to hold the wafer 101 until the process is performed. In addition, the lower portion of the load lock chamber 20 is equipped with a low-temperature device for lowering the temperature, and serves to cool and take out the wafer 101 after the wafer manufacturing process is completed.

The transfer chamber 30 transfers the wafer 101 between the load lock chamber 20 and the process chamber 50. Here, a predetermined vacuum is provided inside the transfer chamber 30. In particular, the inside of the transfer chamber 30 is preferably formed with a vacuum similar to the process chamber 50. In addition, the temperature of the transfer chamber 30 is maintained at a temperature similar to room temperature 20 to 25 ℃.

The transfer chamber 30 is provided with a blade 40 for holding the wafer 101 to transfer between the load lock chamber 10 and the process chamber 50. The blade 40 may be a conventional robot arm (handler) or a handler (handler) capable of linear movement or rotational movement, the invention is limited or limited by the manner and structure of the blade 40 It is not.

A slit valve (not shown) is provided between the transfer chamber 30 and the process chamber 50 to serve to separate the space between the transfer chamber 30 and the process chamber 50. That is, the slit valve selectively closes the inlet of the process chamber 50 to isolate the process chamber 50 during the wafer manufacturing process, and allows the process chamber 50 to enter and exit the wafer 101. Open).

The process chamber 50 receives the wafer 101, and an epitaxial process is performed to grow a single crystal layer (hereinafter, an epitaxial layer) of a predetermined material on the surface of the wafer 101.

In detail, referring to FIG. 6, the process chamber 50 includes a reaction space 51 in which the wafer 101 is accommodated and an epitaxial process is performed, and a susceptor 53 and a heater 55. do.

In the reaction space 51, the wafer 101 is accommodated, and an epitaxial process is performed in a predetermined atmosphere. In the reaction space 51, the wafer 101 is introduced and the wafer 101 is heated to a predetermined process temperature, and silicon on the wafer 101 is provided by providing a source gas containing silicon together with hydrogen gas. The epitaxial layer is grown.

For example, the source gas may be silicon tetrachloride (SiCl 4), trichlorosilane (SiHCl 3, Trichlorosilane, TCS) or dichlorosilane (SiH 2 Cl 2, Dichlorosilane) or silane (SiH 4). The process temperature for growing the epitaxial layer using the trichlorosilane as a source gas is 1100 to 1200 ° C. On the other hand, when the epitaxial layer is grown using dichlorosilane or silane as a source gas in addition to the trichlorosilane, the epitaxial layer is grown at a temperature lower than the above-described process temperature.

In the present embodiment, an epitaxial layer growth process using trichlorosilane as a source gas will be described as an example of such an epitaxial layer growth process. However, when the epitaxial layer is grown by using a source gas other than trichlorosilane, the temperature conditions are different, and the other effects of the present embodiment may work in the same manner.

The heater 55 is provided in the reaction space 51 to heat the susceptor 53 and the wafer 101 to the process temperature.

The susceptor 53 is provided in the reaction space 51 to fix the wafer 101 during the epitaxial process.

The susceptor 53 is provided with a lift pin 57 for raising and lowering the wafer 101 when loading / unloading the wafer 101. For example, the lift pins 57 are disposed at three points to stably support the wafer 101.

Referring to FIG. 7, before the wafer 101 is seated in the susceptor 53 in the processor chamber 50, as in FIG. 6, the processor chamber 50 and the wafer as well as the wafer during the deposition of silicon from the previous wafer process. Since silicon is also deposited on the susceptor 53, etching and coating of the process chamber 50 are performed to clean the state of the processor chamber 50. The etching of the processor chamber 50 is to remove the side reaction material coated on the wall of the processor chamber 50 and the susceptor 53 after the epitaxy run.

After etching, the silicon coating is excessively etched from the susceptor 53 and the processor chamber 50 after etching to protect the wafer 101 from auto-doping impurities due to external diffusion during thermal processing. To coat. After the wafer 101 is seated in the processor chamber 50, a heat treatment step is performed using hydrogen (H 2) at about 1100 to 1200 ° C., which is a natural oxide film for epitaxial growth. (Native Oxide) removal, organic impurities removal and Bulk Micro Defect (BMD) formed on the wafer is a very important step to form a constant dezoned zone (DZ). After the heat treatment step is completed, the surface etching (pre-etching, surface etching) before the deposition depending on the level of epi-wafer particles, but generally proceeds directly to the epi layer formation process. Growth of the epi layer under normal pressure is carried out at 1100 ~ 1150 ℃. In addition, TCS (Trichlorosilane, SiHCl 3) is supplied as a source gas supplied into the processor chamber 50, and a dopant gas B 2 H 6 is added to control epitaxial resistance. Thereafter, after the process of etching and coating the processor chamber 50, purging is performed before the wafer 101 is seated in the susceptor 53. The difference occurs. That is, when the continuous run of the wafer 101 proceeds, the aspect of the back surface of the wafer from the first sheet and the second sheet is changed. Looking at it in detail as follows.

8A is a view of the back side of the wafer with a purging time of about 480 sec. As shown in FIG. 8A, during the continuous run, the first wafer 101 is seated under sufficient purging after completing the etching and coating steps of the processor chamber 50, and is free from previous defects. A mirror image can be obtained.

In addition, the second wafer 101 illustrated in FIG. 8B is a wafer in which a process is performed without purging after the first wafer 101 performs an epitaxial process, and FIG. 8C illustrates an epitaxial process of the first wafer. The wafer is processed after being purged for about 120 sec. The wafer 101 in FIGS. 8B and 8C corresponds to a wafer from the second sheet, and is a wafer in which no purging is performed or the purging time is insufficient. This is the case where the process of etching and coating the processor chamber 50 is completed at the same time, or after a short time from the completion time, the haze (Haze) on the back of the wafer 101 And comb defects occur.

These results indicate that the condition in the processor chamber 50 is a major factor in generating the back defect of the wafer 101.

Table 1 shows the test results for the backside defect of the wafer according to various process parameters, and the purging time is 0 sec as the purging condition at this time.

Table 1 shows the occurrence and extent of defects on the back side of the wafer as the test is performed under standard conditions, followed by changing each process variable.

As a result of the test, the main factor causing defects on the back surface of the wafer 101 can be identified as Cl −. This can be seen from the fourth condition as shown in FIG. 8 that the back side of the wafer 101 is further deteriorated. Excess hydrogen chloride gas (HCl) is used to etch the processor chamber 50, since Cl- generated therefrom etches the back side of the wafer 101. On the other hand, increasing the coating amount of silicon on the inner surface of the processor chamber 50 reduces the back defects of the wafer 101. This is because the amount of silicon coating in the processor chamber 50 increases to prevent side reactions of unwanted impurities (remaining components including Cl −) from occurring.

From this, the backside defect of the wafer 101 may be controlled by enhancing the coating conditions of the processor chamber 50 without purging after the etching and coating step of the processor chamber 50 or increasing the purging time. Can be.

In the present invention, the inner surface of the processor chamber 50 is coated with silicon for about 40 to 60 sec. At this time, the coating thickness of the coating agent coated on the inner surface of the processor chamber 50 is about 2.5 ~ 3㎛.

As such, even if the first wafer is not purged after the epitaxial process by coating the inner surface of the etched processor chamber 50, or the purging time is shortened, the second wafer from the second epitaxial process is completed on the rear surface thereof. Haze, halo or predecessors may be prevented from occurring.

1 is a schematic diagram illustrating a wafer force generated due to a temperature difference during wafer loading.

FIG. 2 is a schematic diagram illustrating an autodoping phenomenon generated during the manufacture of an epitaxial wafer by chemical vapor deposition.

3 is a perspective view illustrating a scene in which a halo is generated on the back surface of a wafer.

4 is a perspective view illustrating a scene in which scratchable defects are generated on a back surface of a wafer.

5 is a perspective view illustrating an epitaxial wafer manufacturing apparatus according to an embodiment of the present invention.

6 is a side view for describing the process chamber of FIG. 5.

7 is a graph depicting the epitaxial process in the process chamber.

8 is a perspective view illustrating a wafer back side state according to a purging time before wafer loading.

9 is a perspective view illustrating a back side of a wafer coated with a chamber after an etching process.

<Explanation of symbols for the main parts of the drawings>

1: wafer 2: susceptor

3: epi layer 4: pre- 힛 ring

5: heat source 6: FOUP

10: interface 20: load lock chamber

30: transfer chamber 40: blade

50: process chamber 53: susceptor

55: heater 57: lift pin

101: wafer

Claims (4)

In a wafer defect control method for controlling defects on a wafer surface, Supplying an etchant into the chamber to etch the inner surface of the chamber; And Supplying a coating agent into the chamber to coat an inner surface of the etched chamber; To include, wherein the supply time of the coating agent is a wafer defect control method, characterized in that 40 to 60sec. The method of claim 1, The supply time of the etchant is a wafer defect control method, characterized in that 40 to 60sec. The method of claim 1, The internal temperature of the chamber is a wafer defect control method, characterized in that 1100 to 1200 ℃. The method of claim 1, The etchant comprises hydrogen chloride (HCl) characterized in that the wafer defect control method.

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